Hello Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/23034
to review the following change.
Change subject: mainboard/google/zoombini: Fix some devicetree pci settings
......................................................................
mainboard/google/zoombini: Fix some devicetree pci settings
Enable I2C #2, #3, and #5.
Enable UART #2.
Enable GSPI #0 and #1.
Disable SATA.
Set pci 1f.0 to chromeec.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281
Signed-off-by: Nick Vaccaro <nvaccaro(a)chromium.org>
---
M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
1 file changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/23034/1
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index e71f15b..771bab2 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -16,18 +16,18 @@
device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on end # SATA
+ device pci 17.0 off end # SATA
device pci 19.0 on end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 off end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
@@ -44,11 +44,11 @@
device pci 1d.7 off end # PCI Express Port 16
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
end
end # LPC Interface
device pci 1f.1 on end # P2SB
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281
Gerrit-Change-Number: 23034
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Hello Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/23033
to review the following change.
Change subject: mainboard/google/zoombini: move gpio.c into variants/zoombini
......................................................................
mainboard/google/zoombini: move gpio.c into variants/zoombini
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I1f3eccd7345c01a1f314ba51927b9bf5c8edeea3
Signed-off-by: Nick Vaccaro <nvaccaro(a)chromium.org>
---
M src/mainboard/google/zoombini/variants/baseboard/Makefile.inc
A src/mainboard/google/zoombini/variants/zoombini/Makefile.inc
R src/mainboard/google/zoombini/variants/zoombini/gpio.c
3 files changed, 22 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/23033/1
diff --git a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc
index 3385b4c..ee25895 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc
@@ -13,9 +13,6 @@
## GNU General Public License for more details.
##
-bootblock-y += gpio.c
-
romstage-y += boardid.c
ramstage-y += boardid.c
-ramstage-y += gpio.c
diff --git a/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc b/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc
new file mode 100644
index 0000000..8f03114
--- /dev/null
+++ b/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2017 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/zoombini/gpio.c
similarity index 94%
rename from src/mainboard/google/zoombini/variants/baseboard/gpio.c
rename to src/mainboard/google/zoombini/variants/zoombini/gpio.c
index 1626c38..e9cfb42 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/gpio.c
+++ b/src/mainboard/google/zoombini/variants/zoombini/gpio.c
@@ -243,23 +243,16 @@
/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
NF1), /* PCH_SPI_H1_3V3_MOSI */
#endif
-#if IS_ENABLED(CONFIG_ZOOMBINI_USE_I2C_TPM)
-/* I2C5_SDA */
-/* I2C5_SCL */
-#endif
-/* Ensure UART pins are in native mode for H1. */
-/* UART0_RXD */ /* UART_PCH_RX_DEBUG_TX */
-/* UART0_TXD */ /* UART_PCH_RX_DEBUG_RX */
+/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* H1_PCH_INT_ODL */
};
-const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config *variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
-const struct pad_config *__attribute__((weak))
- variant_early_gpio_table(size_t *num)
+const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
@@ -269,7 +262,7 @@
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
};
-const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio *variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1f3eccd7345c01a1f314ba51927b9bf5c8edeea3
Gerrit-Change-Number: 23033
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Hello Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/23032
to review the following change.
Change subject: mainboard/google/zoombini: add mainboard_ops
......................................................................
mainboard/google/zoombini: add mainboard_ops
Add mainboard.c to ramstage.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: Ic7275b07f28a99a91b978d2e8c4118c6858705bc
Signed-off-by: Nick Vaccaro <nvaccaro(a)chromium.org>
---
M src/mainboard/google/zoombini/Makefile.inc
A src/mainboard/google/zoombini/mainboard.c
2 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/23032/1
diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc
index 38e10d0..b6fe25e 100644
--- a/src/mainboard/google/zoombini/Makefile.inc
+++ b/src/mainboard/google/zoombini/Makefile.inc
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright (C) 2017 Google Inc.
+## Copyright 2017 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -25,6 +25,7 @@
ramstage-y += boardid.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += mainboard.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/zoombini/mainboard.c b/src/mainboard/google/zoombini/mainboard.c
new file mode 100644
index 0000000..262e823
--- /dev/null
+++ b/src/mainboard/google/zoombini/mainboard.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <ec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+ dev->ops->write_acpi_tables = NULL;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic7275b07f28a99a91b978d2e8c4118c6858705bc
Gerrit-Change-Number: 23032
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>