coreboot-gerrit December 2017

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Change in coreboot[master]: nb/intel/i945: Clean up native VGA graphic init
by Arthur Heymans (Code Review) 29 Dec '17

29 Dec '17

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/17253 ) Change subject: nb/intel/i945: Clean up native VGA graphic init ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/17253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I68cf6c71670ed1050416c57369b0bf1a18b9f65c Gerrit-Change-Number: 17253 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]sandybridge/optimus: Incomplete Optimus port
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23041 ) Change subject: [WIP]sandybridge/optimus: Incomplete Optimus port ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/65090/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19839/ : SUCCESS -- To view, visit https://review.coreboot.org/23041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If1d46e063d1856db2fe7d71bc2219e3aded1f935 Gerrit-Change-Number: 23041 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 16:50:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]sandybridge/optimus: Incomplete Optimus port
by Patrick Rudolph (Code Review) 29 Dec '17

29 Dec '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23041 Change subject: [WIP]sandybridge/optimus: Incomplete Optimus port ...................................................................... [WIP]sandybridge/optimus: Incomplete Optimus port Change-Id: If1d46e063d1856db2fe7d71bc2219e3aded1f935 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t530/dsdt.asl M src/northbridge/intel/sandybridge/acpi/peg.asl 2 files changed, 411 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/23041/1 diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 7db8344..30a5119 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -49,6 +49,97 @@ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } + + Scope (\_SB.PCI0.PEGP.DEV0) { + Method (NVOP, 4, Serialized) { + If (LNotEqual (Arg1, 0x0100)) + { + Return (0x80000001) + } + + Store (ToInteger (Arg2), Local0) + + /* Supported Optimus functions advertisement */ + If (LEqual (Local0, 0x00)) + { + Return (Buffer (0x04) + { + 0x09, 0x00, 0x00, 0x06 + }) + } + /* NOUVEAU_DSM_OPTIMUS_CAPS */ + If (LEqual (Local0, 0x1A)) + { + CreateField (Arg3, 0x18, 0x02, OPCE) + CreateField (Arg3, 0x00, 0x01, FLCH) + If (ToInteger (FLCH)) + { + Store (OPCE, OMPR) + } + + Store (Buffer (0x04) + { + 0x00, 0x00, 0x00, 0x00 + }, Local0) + CreateField (Local0, 0x00, 0x01, OPEN) + CreateField (Local0, 0x03, 0x02, CGCS) + CreateField (Local0, 0x06, 0x01, SHPC) + CreateField (Local0, 0x18, 0x03, DGPC) + CreateField (Local0, 0x1B, 0x02, HDAC) + Store (One, OPEN) + Store (One, SHPC) + Store (One, DGPC) + If (\_SB.PCI0.PEG.DEV0._STA ()) + { + Store (0x03, CGCS) + } + + Store (0x02, HDAC) + Return (Local0) + } + /* NOUVEAU_DSM_OPTIMUS_FLAGS */ + If (LEqual (Local0, 0x1B)) + { + CreateField (Arg3, 0x00, 0x01, HDAU) + CreateField (Arg3, 0x01, 0x01, HDAR) + Store (Buffer (0x04) + { + 0x00, 0x00, 0x00, 0x00 + }, Local0) + CreateField (Local0, 0x02, 0x02, RQGS) + CreateField (Local0, 0x04, 0x01, PWST) + Store (One, PWST) + Store (Zero, RQGS) + If (ToInteger (HDAR)) + { + Store (ToInteger (HDAU), HDAS) + } + + Return (Local0) + } + /* NOUVEAU_DSM_POWER */ + If (LEqual (Local0, 3)) + { + } + + Return (0x80000002) + } + + Method (_DSM, 4, NotSerialized) { + /* NV DSM OPTIMUS */ + If (\CMPB (Arg0, Buffer (0x10) { + 0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47, + 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0})) + { + Return (NVOP (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (0x04) + { + 0x01, 0x00, 0x00, 0x80 + }) + } + } /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index ddacdba..6b0f9ce 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -28,6 +28,86 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, \_SB.PCI0.PEGP.LNKD) + Store(One, \_SB.PCI0.PEGP.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(\_SB.PCI0.PEGP.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, \_SB.PCI0.PEGP.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + \_SB.PCI0.PEGP._ON () + \_SB.PCI0.PEGP.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + \_SB.PCI0.PEGP.DEV0._OFF () + \_SB.PCI0.PEGP._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) } Device (PEG1) @@ -44,6 +124,86 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, \_SB.PCI0.PEG1.LNKD) + Store(One, \_SB.PCI0.PEG1.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(\_SB.PCI0.PEG1.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, \_SB.PCI0.PEG1.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + \_SB.PCI0.PEG1._ON () + \_SB.PCI0.PEG1.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + \_SB.PCI0.PEG1.DEV0._OFF () + \_SB.PCI0.PEG1._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) } Device (PEG2) @@ -60,6 +220,86 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, \_SB.PCI0.PEG2.LNKD) + Store(One, \_SB.PCI0.PEG2.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(\_SB.PCI0.PEG2.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, \_SB.PCI0.PEG2.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + \_SB.PCI0.PEG2._ON () + \_SB.PCI0.PEG2.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + \_SB.PCI0.PEG2.DEV0._OFF () + \_SB.PCI0.PEG2._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) } Device (PEG6) @@ -76,4 +316,84 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, \_SB.PCI0.PEG6.LNKD) + Store(One, \_SB.PCI0.PEG6.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(\_SB.PCI0.PEG6.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, \_SB.PCI0.PEG6.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + \_SB.PCI0.PEG6._ON () + \_SB.PCI0.PEG6.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + \_SB.PCI0.PEG6.DEV0._OFF () + \_SB.PCI0.PEG6._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) } -- To view, visit https://review.coreboot.org/23041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If1d46e063d1856db2fe7d71bc2219e3aded1f935 Gerrit-Change-Number: 23041 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mainboard/t530: Add "Hybrid Graphics" mode
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23040 ) Change subject: mainboard/t530: Add "Hybrid Graphics" mode ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19838/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65089/ : SUCCESS -- To view, visit https://review.coreboot.org/23040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d65a905306bed80d14e10a53dcdf3eb3ff86986 Gerrit-Change-Number: 23040 Gerrit-PatchSet: 1 Gerrit-Owner: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 16:48:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/t530: Add "Hybrid Graphics" mode
by Renze Nicolai (Code Review) 29 Dec '17

29 Dec '17

Renze Nicolai has uploaded this change for review. ( https://review.coreboot.org/23040 Change subject: mainboard/t530: Add "Hybrid Graphics" mode ...................................................................... mainboard/t530: Add "Hybrid Graphics" mode This patch adds a mode to the nvram settings that enables the discrete graphics card without switching the LVDS panel to the Nvidia card. This allows using the Nvidia GPU and the Intel GPU at the same time. Tested with Nouveau and "DRI_PRIME=1". It depends on patches 20547, 20548 and 22337 which allow Nouveau to load the VGA option ROM using an ACPI interface. The VGAROM needs to be added manually using cbfstool for now. Change-Id: I1d65a905306bed80d14e10a53dcdf3eb3ff86986 Signed-off-by: Renze Nicolai <renze(a)rnplus.nl> --- M src/mainboard/lenovo/t530/cmos.layout 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/23040/1 diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 8304d52..72fd7fb 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -129,6 +129,7 @@ 11 6 224M 12 0 Integrated Only 12 1 Discrete Only +12 2 Hybrid Graphics 13 0 Disable 13 1 AC and battery 13 2 AC only -- To view, visit https://review.coreboot.org/23040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1d65a905306bed80d14e10a53dcdf3eb3ff86986 Gerrit-Change-Number: 23040 Gerrit-PatchSet: 1 Gerrit-Owner: Renze Nicolai <renze(a)rnplus.nl>

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22337 ) Change subject: nb/intel/sandybridge/peg: Add PEG driver ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19837/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65088/ : SUCCESS -- To view, visit https://review.coreboot.org/22337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Gerrit-Change-Number: 22337 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 14:22:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: device/pci_rom: Write _ROM method for VGA devices
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20548 ) Change subject: device/pci_rom: Write _ROM method for VGA devices ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/65086/ : SUCCESS -- To view, visit https://review.coreboot.org/20548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Gerrit-Change-Number: 20548 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 14:15:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/x86/acpigen: Add generator for _ROM
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20547 ) Change subject: arch/x86/acpigen: Add generator for _ROM ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/65087/ : SUCCESS -- To view, visit https://review.coreboot.org/20547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie118b15257295b7133c8e585c0fd5218249dec8d Gerrit-Change-Number: 20547 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 14:01:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/x86/acpigen: Add generator for _ROM
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20547 ) Change subject: arch/x86/acpigen: Add generator for _ROM ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19836/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65085/ : SUCCESS -- To view, visit https://review.coreboot.org/20547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie118b15257295b7133c8e585c0fd5218249dec8d Gerrit-Change-Number: 20547 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 12:49:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]util/intelvbttool: Rewrite tool
by build bot (Jenkins) (Code Review) 29 Dec '17

29 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18902 ) Change subject: [WIP]util/intelvbttool: Rewrite tool ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19835/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65084/ : SUCCESS -- To view, visit https://review.coreboot.org/18902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76 Gerrit-Change-Number: 18902 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Dec 2017 12:30:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017