Kane Chen has uploaded this change for review. ( https://review.coreboot.org/23018
Change subject: soc/intel/skylake: Add device setting for sata power optimization ......................................................................
soc/intel/skylake: Add device setting for sata power optimization
This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose
BUG=b:70491485
Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23018/1
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 00088b9..4e8cb81 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -542,6 +542,9 @@
/* PCH Trip Temperature */ u8 pch_trip_temp; + + /* Enable/Disable Sata power optimization */ + u8 SataPwrOptEnable; };
typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 24a239e..ccda303 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -219,6 +219,7 @@ params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; + params->SataPwrOptEnable = config->SataPwrOptEnable;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;