coreboot-gerrit November 2017

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Change in coreboot[master]: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22568 ) Change subject: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18619/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63729/ : SUCCESS -- To view, visit https://review.coreboot.org/22568 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Gerrit-Change-Number: 22568 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 01:52:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Move intr_types[] table
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22476 ) Change subject: soc/amd/stoneyridge: Move intr_types[] table ...................................................................... Patch Set 12: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63728/ : SUCCESS -- To view, visit https://review.coreboot.org/22476 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I18907c93e1eec341d56cea13bb73a336d8e7b05b Gerrit-Change-Number: 22476 Gerrit-PatchSet: 12 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 01:30:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Replace msr(0x198) with msr(IA32_PERF_STATUS)
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22585 ) Change subject: Replace msr(0x198) with msr(IA32_PERF_STATUS) ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18618/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63727/ : SUCCESS -- To view, visit https://review.coreboot.org/22585 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Gerrit-Change-Number: 22585 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 20:39:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Replace msr(0x198) with msr(IA32_PERF_STATUS)
by Elyes HAOUAS (Code Review) 23 Nov '17

23 Nov '17

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/22585 Change subject: Replace msr(0x198) with msr(IA32_PERF_STATUS) ...................................................................... Replace msr(0x198) with msr(IA32_PERF_STATUS) Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/speedstep/speedstep.c M src/include/cpu/intel/speedstep.h M src/mainboard/intel/eagleheights/romstage.c M src/mainboard/intel/mtarvon/romstage.c M src/northbridge/intel/i945/udelay.c 7 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/22585/1 diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6e5b339..96830c4 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -86,7 +86,7 @@ wrmsr(IA32_MISC_ENABLE, msr); // set maximum CPU speed - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); int busratio_max = (msr.hi >> (40-32)) & 0x1f; msr = rdmsr(IA32_PLATFORM_ID); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index b5a68cc..a1433f6 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -94,7 +94,7 @@ wrmsr(IA32_MISC_ENABLE, msr); // set maximum CPU speed - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); int busratio_max = (msr.hi >> (40-32)) & 0x1f; msr = rdmsr(IA32_PLATFORM_ID); diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 96ac8e5..441f2a3 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -55,15 +55,15 @@ /* Read normal maximum parameters. */ /* Newer CPUs provide the normal maximum settings in - IA32_PLATFORM_ID. The values in IA32_PERF_STS change + IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change when using turbo mode. */ msr = rdmsr(IA32_PLATFORM_ID); params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); if (cpu_id == 0x006e) { /* Looks like Yonah CPUs don't have the frequency ratio in - IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading + IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading should be reliable as those CPUs don't have turbo mode. */ - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) >> SPEEDSTEP_RATIO_SHIFT; } diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 40234d5..bcf6918 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -36,7 +36,7 @@ /* Speedstep related MSRs */ #define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STS 0x198 +#define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index c254f17..21313eb 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -171,7 +171,7 @@ * bits 47:32, where BUS_RATIO_MAX and VID_MAX * are encoded */ - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); perf = msr.hi & 0x0000ffff; /* Write VID_MAX & BUS_RATIO_MAX to diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index cb3e870..13f425e 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -100,7 +100,7 @@ /* Set CPU frequency/voltage to maximum */ /* FIXME: move to Pentium M init code */ - msr = rdmsr(0x198); + msr = rdmsr(IA32_PERF_STATUS); perf = msr.hi & 0xffff; msr = rdmsr(0x199); msr.lo &= 0xffff0000; diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 90f2638..8447453 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -56,7 +56,7 @@ break; } - msr = rdmsr(0x198); + msr = rdmsr(IA32_PERF_STATUS); divisor = (msr.hi >> 8) & 0x1f; d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ -- To view, visit https://review.coreboot.org/22585 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Gerrit-Change-Number: 22585 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: acpi/tpm: remove non-existent IRQ for Infineon TPM chip
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22582 ) Change subject: acpi/tpm: remove non-existent IRQ for Infineon TPM chip ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63726/ : SUCCESS -- To view, visit https://review.coreboot.org/22582 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b Gerrit-Change-Number: 22582 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 18:54:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Set low maximum temperature threshold for Thermal ...
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22419 ) Change subject: soc/intel/skylake: Set low maximum temperature threshold for Thermal Device ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18617/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63725/ : SUCCESS -- To view, visit https://review.coreboot.org/22419 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610 Gerrit-Change-Number: 22419 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 23 Nov 2017 17:58:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Set low maximum temperature threshold for Thermal ...
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22419 ) Change subject: soc/intel/skylake: Set low maximum temperature threshold for Thermal Device ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18616/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63724/ : SUCCESS -- To view, visit https://review.coreboot.org/22419 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610 Gerrit-Change-Number: 22419 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 23 Nov 2017 17:50:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Provide API to perform any post MP initialization
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22418 ) Change subject: soc/intel/common: Provide API to perform any post MP initialization ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18615/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63723/ : SUCCESS -- To view, visit https://review.coreboot.org/22418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I140a922147af81851c30444cb4b96c53ae441d7a Gerrit-Change-Number: 22418 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 23 Nov 2017 17:36:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Disable unused i2c lines
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22576 ) Change subject: google/fizz: Disable unused i2c lines ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63721/ : SUCCESS -- To view, visit https://review.coreboot.org/22576 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b Gerrit-Change-Number: 22576 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 17:08:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Remove tpm i2c configs from Kconfig
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22577 ) Change subject: google/fizz: Remove tpm i2c configs from Kconfig ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18614/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63722/ : SUCCESS -- To view, visit https://review.coreboot.org/22577 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id88f32fa952801749544534442fc15d85fc1a892 Gerrit-Change-Number: 22577 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 17:05:14 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017