coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

1 participants
852 discussions

Patch set updated for coreboot: amdmct: Fix offset calculation in mct_ResetDataStruct_D()
by Nico Huber 03 Jan '17

03 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17992 -gerrit commit e45b48d28023b4eed345250b0c8f96958660e15f Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 29 14:03:50 2016 -0700 amdmct: Fix offset calculation in mct_ResetDataStruct_D() The code was intentionally using an offset past the end of the array to get the value of the next byte when starting to clear the structure. The calculated offset was too far off. So rewrite it using offsetof() and sizeof() which is less error-prone. Also make use of memset() and put a comment into the struct's declaration about the fragile code. A correct solution would require more extensive refactoring (e.g. moving the skipped fields out of the struct). Fixes warning for GCC 6.2 toolchain update: src/northbridge/amd/amdfam10/../amdmct/mct/mct_d.c:3628:27: In function 'mct_ResetDataStruct_D': error: index 2 denotes an offset greater than size of 'u8[2][4] {aka unsigned char[2][4]}' [-Werror=array-bounds] Change-Id: Ic81cf5e57992fc0e45f6c96b62a35742a8ef891f Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 25 ++++++++++--------------- src/northbridge/amd/amdmct/mct/mct_d.h | 5 +++++ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626..779a8a5 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3601,35 +3601,30 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { u8 Node; - u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; + size_t start, stop; u8 *p; u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; host_serv1 = pDCTstat->HostBiosSrvc1; host_serv2 = pDCTstat->HostBiosSrvc2; - p = (u8 *) pDCTstat; + /* clear everything but CH_D_DIR_B_DQS .. CH_D_BC_RCVRDLY */ + p = (u8 *)pDCTstat; start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } + stop = offsetof(struct DCTStatStruc, CH_D_DIR_B_DQS); + memset(p + start, 0x00, stop - start); - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); + start = (u32)(offsetof(struct DCTStatStruc, CH_D_BC_RCVRDLY) + + sizeof(pDCTstat->CH_D_BC_RCVRDLY)); stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } + memset(p + start, 0x00, stop - start); + pDCTstat->HostBiosSrvc1 = host_serv1; pDCTstat->HostBiosSrvc2 = host_serv2; } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4e1a909..fbfbf6f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -451,6 +451,9 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ + + /* DON'T MOVE the following declarations. They form a + region that's to be skipped in mct_ResetDataStruct_D(). */ u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ @@ -473,6 +476,8 @@ struct DCTStatStruc { /* A per Node structure*/ u8 CH_D_BC_RCVRDLY[2][4]; /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* END DON'T MOVE (see above) */ + u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/

1 0

Patch set updated for coreboot: amdmct: Fix offset calculation in mct_ResetDataStruct_D()
by Nico Huber 03 Jan '17

03 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17992 -gerrit commit b0774dbce285848f37cd87a0bb31be39b5fe5238 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 29 14:03:50 2016 -0700 amdmct: Fix offset calculation in mct_ResetDataStruct_D() The code was intentionally using an offset past the end of the array to get the value of the next byte when starting to clear the structure. The calculated offset was too far off. So rewrite it using offsetof() and sizeof() which is less error-prone. Also make use of memset() and put a comment into the struct's declaration about the fragile code. A correct solution would require more extensive refactoring (e.g. moving the skipped fields out of the struct). Fixes warning for GCC 6.2 toolchain update: src/northbridge/amd/amdfam10/../amdmct/mct/mct_d.c:3628:27: In function 'mct_ResetDataStruct_D': error: index 2 denotes an offset greater than size of 'u8[2][4] {aka unsigned char[2][4]}' [-Werror=array-bounds] Change-Id: Ic81cf5e57992fc0e45f6c96b62a35742a8ef891f Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 24 ++++++++++-------------- src/northbridge/amd/amdmct/mct/mct_d.h | 5 +++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626..2d4970e 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3603,33 +3603,29 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, u8 Node; u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; + size_t start, stop; u8 *p; u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; host_serv1 = pDCTstat->HostBiosSrvc1; host_serv2 = pDCTstat->HostBiosSrvc2; - p = (u8 *) pDCTstat; + /* clear everything but CH_D_DIR_B_DQS .. CH_D_BC_RCVRDLY */ + p = (u8 *)pDCTstat; start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } + stop = offsetof(struct DCTStatStruc, CH_D_DIR_B_DQS); + memset(p + start, 0x00, stop - start); - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); + start = (u32)(offsetof(struct DCTStatStruc, CH_D_BC_RCVRDLY) + + sizeof(pDCTstat->CH_D_BC_RCVRDLY)); stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } + memset(p + start, 0x00, stop - start); + pDCTstat->HostBiosSrvc1 = host_serv1; pDCTstat->HostBiosSrvc2 = host_serv2; } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4e1a909..fbfbf6f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -451,6 +451,9 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ + + /* DON'T MOVE the following declarations. They form a + region that's to be skipped in mct_ResetDataStruct_D(). */ u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ @@ -473,6 +476,8 @@ struct DCTStatStruc { /* A per Node structure*/ u8 CH_D_BC_RCVRDLY[2][4]; /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* END DON'T MOVE (see above) */ + u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/

1 0

Patch set updated for coreboot: payloads/seabios: Add support for Hudson UART
by Ricardo Ribalda Delgado 03 Jan '17

03 Jan '17

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18025 -gerrit commit d6d8a755035ecefe76d1a86103176b4b0635fad3 Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Jan 3 11:56:22 2017 +0100 payloads/seabios: Add support for Hudson UART Since version 9332965 "serialio: Support for mmap serial ports", SeaBIOS supports memory mapped serial ports. This patch automatically configures SeaBIOS when the Hudson UART is enabled. Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- payloads/external/Makefile.inc | 2 ++ payloads/external/SeaBIOS/Makefile | 3 +++ 2 files changed, 5 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index e4d3e12..54ef3ac 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -80,6 +80,8 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_DRIVERS_UART_8250IO=$(CONFIG_DRIVERS_UART_8250IO) \ + CONFIG_DRIVERS_UART_8250MEM=$(CONFIG_DRIVERS_UART_8250MEM) \ + CONFIG_HUDSON_UART=$(CONFIG_HUDSON_UART) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 9ec3e60..1ecd279 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -42,6 +42,9 @@ config: checkout ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config +else ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250MEM)$(CONFIG_HUDSON_UART),yyy) + echo "CONFIG_DEBUG_SERIAL_MMIO=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_MEM_ADDRESS=0xFEDC6000" >> seabios/.config else echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif

1 0

New patch to review for coreboot: payloads/seabios: Add support for Hudson UART
by Ricardo Ribalda Delgado 03 Jan '17

03 Jan '17

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18025 -gerrit commit 7e7a3750bcd36561704917b6c8b99b68478ac3c3 Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Jan 3 11:56:22 2017 +0100 payloads/seabios: Add support for Hudson UART Since version 9332965 "serialio: Support for mmap serial ports", Seabios supports memory mapped serial ports. This patch automatically configures Seabios when the Hudson UART is enabled. Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- payloads/external/Makefile.inc | 2 ++ payloads/external/SeaBIOS/Makefile | 3 +++ 2 files changed, 5 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index e4d3e12..54ef3ac 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -80,6 +80,8 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_DRIVERS_UART_8250IO=$(CONFIG_DRIVERS_UART_8250IO) \ + CONFIG_DRIVERS_UART_8250MEM=$(CONFIG_DRIVERS_UART_8250MEM) \ + CONFIG_HUDSON_UART=$(CONFIG_HUDSON_UART) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 9ec3e60..1ecd279 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -42,6 +42,9 @@ config: checkout ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config +else ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250MEM)$(CONFIG_HUDSON_UART),yyy) + echo "CONFIG_DEBUG_SERIAL_MMIO=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_MEM_ADDRESS=0xFEDC6000" >> seabios/.config else echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif

1 0

Patch set updated for coreboot: [not for merge]src/cpu/intel: Add Pentium 4 model F6x
by HAOUAS Elyes 03 Jan '17

03 Jan '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17410 -gerrit commit 082a949b21eee546ee29fe3dce5b5125ede64a5e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Jan 2 21:57:13 2017 +0100 [not for merge]src/cpu/intel: Add Pentium 4 model F6x This is a modfied copy of model_F4x. Change-Id: I9c691db73e3ec44895f623ede5a7ee04c13e1851 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/model_f6x/Kconfig | 8 +++++ src/cpu/intel/model_f6x/Makefile.inc | 3 ++ src/cpu/intel/model_f6x/model_f6x_init.c | 60 ++++++++++++++++++++++++++++++++ src/cpu/intel/socket_LGA775/Makefile.inc | 2 +- 5 files changed, 73 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 138da8c..406da56 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -19,6 +19,7 @@ source src/cpu/intel/model_f1x/Kconfig source src/cpu/intel/model_f2x/Kconfig source src/cpu/intel/model_f3x/Kconfig source src/cpu/intel/model_f4x/Kconfig +source src/cpu/intel/model_f6x/Kconfig source src/cpu/intel/ep80579/Kconfig source src/cpu/intel/haswell/Kconfig # Sockets/Slots diff --git a/src/cpu/intel/model_f6x/Kconfig b/src/cpu/intel/model_f6x/Kconfig new file mode 100644 index 0000000..ede6a4a --- /dev/null +++ b/src/cpu/intel/model_f6x/Kconfig @@ -0,0 +1,8 @@ +config CPU_INTEL_MODEL_F6X + bool + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc new file mode 100644 index 0000000..30eab55 --- /dev/null +++ b/src/cpu/intel/model_f6x/Makefile.inc @@ -0,0 +1,3 @@ +ramstage-y += model_f6x_init.c + +//cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin /* missing microcode for CPUID 0F6x */ diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c new file mode 100644 index 0000000..725e4ff --- /dev/null +++ b/src/cpu/intel/model_f6x/model_f6x_init.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/hyperthreading.h> +#include <cpu/x86/cache.h> + +static void model_f6x_init(struct device *cpu) +{ + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + if (!intel_ht_sibling()) { + /* MTRRs are shared between threads */ + x86_setup_mtrrs(); + x86_mtrr_check(); + + /* Update the microcode */ + intel_update_microcode_from_cbfs(); + } + + /* Enable the local CPU APICs */ + setup_lapic(); + + /* Start up my CPU siblings */ + intel_sibling_init(cpu); +}; + +static struct device_operations cpu_dev_ops = { + .init = model_f6x_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x0f62 }, + { X86_VENDOR_INTEL, 0x0f64 }, + { X86_VENDOR_INTEL, 0x0f65 }, + { 0, 0 }, +}; + +static const struct cpu_driver model_f6x __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ffcd1cb..8eef023 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -1,7 +1,7 @@ subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x -#subdirs-y += ../model_f6x +subdirs-y += ../model_f6x #subdirs-y += ../model_1066x subdirs-y += ../model_1067x subdirs-y += ../../x86/tsc

1 0

Patch set updated for coreboot: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by HAOUAS Elyes 03 Jan '17

03 Jan '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18019 -gerrit commit 261a5824753c9468825d40993e1ee3856ce2e149 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Jan 2 21:00:59 2017 +0100 cpu/intel/speedstep/acpi.c: Add Netburst CPUs MSR(0x2c) provides information abour FSB frequency Change-Id: I42b0dcfdd62e07422acb77462aefc2d9b62fba19 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/intel/speedstep/acpi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index d85e487..1dca1ae 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -49,7 +49,17 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { - const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; + u32 fsbcode; + const u32 eax = cpuid_ext(0x01, 0).eax; + msr_t msr; + + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(0x2c); + fsbcode = (msr.lo >> 16) & 7; + } else { + fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; + } + switch (fsbcode) { case 0: return 800; /* / 3 == 266 */ case 1: return 400; /* / 3 == 133 */

1 0

Patch set updated for coreboot: driver/intel/fsp1_1: Fix boot failure for non-verstage case
by Boon Tiong Teo 03 Jan '17

03 Jan '17

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17976 -gerrit commit c4f206f57160561c8d31d8d1907f3b931ab97ed9 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Wed Dec 28 18:56:26 2016 +0800 driver/intel/fsp1_1: Fix boot failure for non-verstage case Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage. So, use the same entry point in either case. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/drivers/intel/fsp1_1/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4088293..39a688d 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,7 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S +romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c

1 0

Patch set updated for coreboot: driver/intel/fsp1_1: Fix boot failure for non-verstage case
by Boon Tiong Teo 03 Jan '17

03 Jan '17

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17976 -gerrit commit c63224050f6a06e96cc78bec8929219c2e1be109 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Wed Dec 28 18:56:26 2016 +0800 driver/intel/fsp1_1: Fix boot failure for non-verstage case Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage. So, use the same entry point in either case. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/drivers/intel/fsp1_1/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4088293..a3261df 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,7 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S +romstage-y += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c

1 0

New patch to review for coreboot: fsp1_1: Fix boot failure for non-verstage case
by Boon Tiong Teo 03 Jan '17

03 Jan '17

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17976 -gerrit commit a61b46f185e2b90e3f424dbee5173c5df96cb74c Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Wed Dec 28 18:56:26 2016 +0800 fsp1_1: Fix boot failure for non-verstage case Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage. So, use the same entry point in either case. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/drivers/intel/fsp1_1/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4088293..a3261df 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,7 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S +romstage-y += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c

1 0

New patch to review for coreboot: 3rdparty/arm-trusted-firmware: Update to Dec 23, 2016 master
by Martin Roth 03 Jan '17

03 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18024 -gerrit commit 4640b12db36a604dbb339932ce4a6f145468f1ab Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 2 19:55:11 2017 -0700 3rdparty/arm-trusted-firmware: Update to Dec 23, 2016 master 177 commits between Sep 20, 2016 and Dec 23, 2016 Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/arm-trusted-firmware | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index bfd9251..cef7b3c 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit bfd925139fdbc2e87979849907b34843aa326994 +Subproject commit cef7b3ce8b26cd94e7e71ddeefc039451525b780

1 0

← Newer
1
...
78
79
80
81
82
83
84
85
86
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2017