coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/quark: Add monotonic timer support
by Lee Leahy 03 Jan '17

03 Jan '17

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18002 -gerrit commit 70a20a93f1565f8882a0b0d997ff3b20fc241949 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Dec 31 08:21:56 2016 -0800 soc/intel/quark: Add monotonic timer support Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/tsc_freq.c | 16 +++++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index c5efd4a..8182caa 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP select C_ENVIRONMENT_BOOTBLOCK select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER select NO_MMCONF_SUPPORT select REG_SCRIPT select RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index eb8c46e..e6d0369 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -17,20 +17,18 @@ #include <stdint.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <timer.h> -static unsigned long bus_freq_khz(void) +unsigned long tsc_freq_mhz(void) { /* CPU freq = 400 MHz */ - return 400 * 1000; + return 400; } -unsigned long tsc_freq_mhz(void) +void timer_monotonic_get(struct mono_time *mt) { - /* assume ratio=1 */ - unsigned bclk_khz = bus_freq_khz(); - - if (!bclk_khz) - return 0; + uint64_t tsc_value; - return (bclk_khz * 1) / 1000; + tsc_value = rdtscll(); + mt->microseconds = tsc_value / tsc_freq_mhz(); }

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Patch merged into coreboot/master: soc/intel/quark: Add early debugging code
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit a765090f0d2f77cb099a60c23da8acaff62cb171 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Dec 28 11:43:10 2016 -0800 soc/intel/quark: Add early debugging code Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/17985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17985 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/quark: Fix serial port configuration
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 73f6a282a191c39d8f5e72e6cd2ce172821cdef4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Dec 28 12:53:37 2016 -0800 soc/intel/quark: Fix serial port configuration Fix serial port configuration broken by how PCI configuration space was referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default to enabled). TEST=Build and run on Galileo Gen2 Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/17984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17984 for details. -gerrit

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Patch set updated for coreboot: mainboard/lenovo/t430: Add Thinkpad T430 support
by Philipp Deppenwiese 03 Jan '17

03 Jan '17

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18011 -gerrit commit 53867a2791769770f26e2cfa0b9d6a68c20277e0 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Mon Jan 2 17:58:09 2017 +0100 mainboard/lenovo/t430: Add Thinkpad T430 support Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/t430/Kconfig | 70 +++++ src/mainboard/lenovo/t430/Kconfig.name | 2 + src/mainboard/lenovo/t430/Makefile.inc | 5 + src/mainboard/lenovo/t430/acpi/ec.asl | 1 + src/mainboard/lenovo/t430/acpi/platform.asl | 12 + src/mainboard/lenovo/t430/acpi/superio.asl | 1 + src/mainboard/lenovo/t430/acpi_tables.c | 1 + src/mainboard/lenovo/t430/board_info.txt | 2 + src/mainboard/lenovo/t430/cmos.default | 17 + src/mainboard/lenovo/t430/cmos.layout | 141 +++++++++ src/mainboard/lenovo/t430/devicetree.cb | 164 ++++++++++ src/mainboard/lenovo/t430/dock.c | 6 + src/mainboard/lenovo/t430/dsdt.asl | 32 ++ src/mainboard/lenovo/t430/early_southbridge.c | 69 ++++ src/mainboard/lenovo/t430/gnvs.c | 19 ++ src/mainboard/lenovo/t430/gpio.c | 433 ++++++++++++++++++++++++++ src/mainboard/lenovo/t430/hda_verb.c | 59 ++++ src/mainboard/lenovo/t430/mainboard.c | 22 ++ src/mainboard/lenovo/t430/romstage.c | 1 + src/mainboard/lenovo/t430/smihandler.c | 103 ++++++ 20 files changed, 1160 insertions(+) diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig new file mode 100644 index 0000000..0abe1fe --- /dev/null +++ b/src/mainboard/lenovo/t430/Kconfig @@ -0,0 +1,70 @@ +if BOARD_LENOVO_THINKPAD_T430 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_12288 + select CPU_INTEL_SOCKET_RPGA989 + select DRIVERS_RICOH_RCE822 + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/t430 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T430" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21f3 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/lenovo/t430/Kconfig.name b/src/mainboard/lenovo/t430/Kconfig.name new file mode 100644 index 0000000..7ae32b8 --- /dev/null +++ b/src/mainboard/lenovo/t430/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T430 + bool "ThinkPad T430" diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc new file mode 100644 index 0000000..7886c13 --- /dev/null +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += dock.c +ramstage-y += gnvs.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl new file mode 100644 index 0000000..c3569e8 --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl new file mode 100644 index 0000000..dfced7a --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -0,0 +1,12 @@ +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/lenovo/t430/board_info.txt b/src/mainboard/lenovo/t430/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/lenovo/t430/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default new file mode 100644 index 0000000..00e8863 --- /dev/null +++ b/src/mainboard/lenovo/t430/cmos.default @@ -0,0 +1,17 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout new file mode 100644 index 0000000..73bbe3a --- /dev/null +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -0,0 +1,141 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 5 r 0 unused +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb new file mode 100644 index 0000000..a5c90ad --- /dev/null +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -0,0 +1,164 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x17" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x04000201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x17aa 0x21f3 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x21f3 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21f3 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x21f3 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x21f3 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x21f3 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "disable_mask" = "0x87" + register "sdwppol" = "1" + device pci 00.0 on # Ricoh SD card reader + subsystemid 0x17aa 0x21f3 + end + end + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x21f3 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x17aa 0x21f3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x21f3 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x21f3 + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x00" + register "config0" = "0x00" + register "config1" = "0x00" + register "config2" = "0x00" + register "config3" = "0x00" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x21f3 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x21f3 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x21f3 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f3 + end + end +end diff --git a/src/mainboard/lenovo/t430/dock.c b/src/mainboard/lenovo/t430/dock.c new file mode 100644 index 0000000..9c9fa83 --- /dev/null +++ b/src/mainboard/lenovo/t430/dock.c @@ -0,0 +1,6 @@ +#include <ec/lenovo/h8/h8.h> + +void h8_mainboard_init_dock (void) +{ +/* FIXME: fill this if needed. */ +} diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl new file mode 100644 index 0000000..08bf3b0 --- /dev/null +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -0,0 +1,32 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/lenovo/t430/early_southbridge.c b/src/mainboard/lenovo/t430/early_southbridge.c new file mode 100644 index 0000000..1e4d165 --- /dev/null +++ b/src/mainboard/lenovo/t430/early_southbridge.c @@ -0,0 +1,69 @@ +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1601); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c15e1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80010000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x00000000; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/t430/gnvs.c b/src/mainboard/lenovo/t430/gnvs.c new file mode 100644 index 0000000..37cd5c9 --- /dev/null +++ b/src/mainboard/lenovo/t430/gnvs.c @@ -0,0 +1,19 @@ +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c new file mode 100644 index 0000000..0a1ff7d --- /dev/null +++ b/src/mainboard/lenovo/t430/gpio.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c new file mode 100644 index 0000000..f363eb1 --- /dev/null +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -0,0 +1,59 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21f3, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa21f3), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c new file mode 100644 index 0000000..5410d23 --- /dev/null +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -0,0 +1,22 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00000000; + RCBA32(0x38c4) = 0x00000000; + RCBA32(0x38c0) = 0x00000000; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/lenovo/t430/romstage.c @@ -0,0 +1 @@ +/* dummy file */ diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c new file mode 100644 index 0000000..88460be --- /dev/null +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +}

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Patch set updated for coreboot: vboot: Clear battery cutoff flags when vbnv_cmos loads backup VBNV.
by Martin Roth 03 Jan '17

03 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18008 -gerrit commit 468e977404f63dc117f2e5f46d2eb77c8d377c38 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Dec 29 20:59:37 2016 +0800 vboot: Clear battery cutoff flags when vbnv_cmos loads backup VBNV. When CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH is set, vbnv_cmos will try to load VBNV from flash if the VBNV in CMOS is invalid. This is usually correct, except the case of battery cut-off. CMOS will always be invalid after battery cut-off if there is no RTC battery (or if that is dead). However, in current implementation the backup in flash is only updated in coreboot, while the real battery cutoff (and the clearing of cutoff flags in VBNV) is done in payload (Depthcharge) stage. This will create an endless reboot loop that: 1. crossystem sets battery cutoff flag in VBNV_CMOS then reboot. 2. coreboot backs-up VBNV_CMOS to VBNV_flash. 3. Depthcharge sees cutoff flag in VBNV_CMOS. 4. Depthcharge clears cutoff flag in VBNV_CMOS. 5. Depthcharge performs battery cutoff (CMOS data is lost). 6. (Plug AC adapter) Reboot. 7. Coreboot sees invalid VBNV_CMOS, load backup from VBNV_flash. 8. Jump to 3. As a result, we should always clear battery cutoff flags when loading backups from VBNV_flash. BRANCH=glados,reef BUG=chrome-os-partner:61365,chrome-os-partner:59615 TEST=emerge-reef coreboot bootimage; Change-Id: I3250a3a179a7b0de9c6e401e4a94dcd23920e473 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/423460 Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/vboot/vbnv.c | 6 ++++++ src/vboot/vbnv.h | 1 + src/vboot/vbnv_cmos.c | 17 +++++++++++++++++ src/vboot/vbnv_layout.h | 3 +++ 4 files changed, 27 insertions(+) diff --git a/src/vboot/vbnv.c b/src/vboot/vbnv.c index ce64928..6537bf0 100644 --- a/src/vboot/vbnv.c +++ b/src/vboot/vbnv.c @@ -79,6 +79,12 @@ int verify_vbnv(uint8_t *vbnv_copy) (crc8_vbnv(vbnv_copy, CRC_OFFSET) == vbnv_copy[CRC_OFFSET]); } +/* Re-generate VBNV checksum. */ +void regen_vbnv_crc(uint8_t *vbnv_copy) +{ + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); +} + /* * Read VBNV data from configured storage backend. * If VBNV verification fails, reset the vbnv copy. diff --git a/src/vboot/vbnv.h b/src/vboot/vbnv.h index 78ca8f6..30da6a5 100644 --- a/src/vboot/vbnv.h +++ b/src/vboot/vbnv.h @@ -22,6 +22,7 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); +void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); int vboot_wants_oprom(void); diff --git a/src/vboot/vbnv_cmos.c b/src/vboot/vbnv_cmos.c index 5eda8e6..b7ef3e7 100644 --- a/src/vboot/vbnv_cmos.c +++ b/src/vboot/vbnv_cmos.c @@ -20,6 +20,22 @@ #include <vboot/vbnv.h> #include <vboot/vbnv_layout.h> +static void clear_vbnv_battery_cutoff_flag(uint8_t *vbnv_copy) +{ + /* + * Currently battery cutoff is done in payload stage, which does not + * update backup VBNV. And doing battery cutoff will invalidate CMOS. + * This means for every reboot after cutoff, read_vbnv_cmos will reload + * backup VBNV and try to cutoff again, causing endless reboot loop. + * So we should always clear battery cutoff flag from loaded backup. + */ + if (vbnv_copy[MISC_FLAGS_OFFSET] & MISC_FLAGS_BATTERY_CUTOFF_MASK) { + printk(BIOS_INFO, "VBNV: Remove battery cut-off request.\n"); + vbnv_copy[MISC_FLAGS_OFFSET] &= ~MISC_FLAGS_BATTERY_CUTOFF_MASK; + regen_vbnv_crc(vbnv_copy); + } +} + void read_vbnv_cmos(uint8_t *vbnv_copy) { int i; @@ -35,6 +51,7 @@ void read_vbnv_cmos(uint8_t *vbnv_copy) read_vbnv_flash(vbnv_copy); if (verify_vbnv(vbnv_copy)) { + clear_vbnv_battery_cutoff_flag(vbnv_copy); save_vbnv_cmos(vbnv_copy); printk(BIOS_INFO, "VBNV: Flash backup restored\n"); } else { diff --git a/src/vboot/vbnv_layout.h b/src/vboot/vbnv_layout.h index 59acd0c..1dc01c9 100644 --- a/src/vboot/vbnv_layout.h +++ b/src/vboot/vbnv_layout.h @@ -41,6 +41,9 @@ #define DEV_BOOT_USB_MASK 0x01 #define DEV_BOOT_SIGNED_ONLY_MASK 0x02 +#define MISC_FLAGS_OFFSET 8 +#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 + #define KERNEL_FIELD_OFFSET 11 #define CRC_OFFSET 15

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Patch set updated for coreboot: util/abuild: List boolean Kconfig options only tested at one setting
by Martin Roth 03 Jan '17

03 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17891 -gerrit commit 68b6114683699cb090239e79a2f5564475bf6cd9 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 14 10:20:53 2016 -0700 util/abuild: List boolean Kconfig options only tested at one setting To get a better idea of what Kconfig options aren't being tested, this will generate a list of which boolean symbols are always getting tested in either the enabled or disabled state. Save all Kconfig options, then build lists of all boolean options tested in the enabled and disabled states. Finally, compare the lists and generates a file containing all options that were tested only in one of the states. Change-Id: Id408785516e47d4c32ddedb268b8ad1601fcaa03 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/abuild/abuild | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/util/abuild/abuild b/util/abuild/abuild index 93ceac5..c21b54f 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -271,6 +271,7 @@ function update_config yes "" 2>/dev/null | $MAKE oldconfig $silent "DOTCONFIG=${config_file}" "obj=${build_dir}" "objutil=$TARGET/sharedutils" &> "${build_dir}/config.log" ; \ CONFIG_OK=$? if [ $CONFIG_OK -eq 0 ]; then + cat "$build_dir/auto.conf" >> "$ALLCONFIGS" $MAKE savedefconfig $silent DEFCONFIG="${defconfig_file}" DOTCONFIG="${config_file}" obj="${build_dir}" objutil="$TARGET/sharedutils" &>> "${build_dir}/config.log" return $? else @@ -701,6 +702,7 @@ if [ "$customizing" = "" ]; then customizing="default configuration" fi +ALLCONFIGS="$TARGET/all_configs.txt" FAILED_BOARDS="$TOP/$TARGET/failed_boards" if [ "$recursive" = "false" ]; then @@ -827,6 +829,12 @@ fi junit '</testsuite>' if [ "$recursive" = "false" ]; then + # Generate a file to show what configs have been tested. + grep '^CONFIG_.*=y$' "$ALLCONFIGS" | sed 's/=.*//' | sort | uniq > "$TARGET/enabled_opts.txt" + grep '^# CONFIG_.* is not set$' "$ALLCONFIGS" | sed 's/# //' | sed 's/ .*//' | sort | uniq > "$TARGET/disabled_opts.txt" + + # Untabbed options are only tested enabled, tabbed options are only tested disabled. + comm "$TARGET/enabled_opts.txt" "$TARGET/disabled_opts.txt" -3 > "$TARGET/untested_opts.txt" # Print the list of failed boards if [ -f "$FAILED_BOARDS" ]; then

1 0

Patch set updated for coreboot: util/abuild: Print list of failed boards at the end of the abuild
by Martin Roth 03 Jan '17

03 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17890 -gerrit commit 579b13006c88133f8268dccb6ddc2c5897efffe3 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 14 10:16:26 2016 -0700 util/abuild: Print list of failed boards at the end of the abuild When running abuild outside of jenkins, because all of the builds are printed intermixed, it's easy to miss when a board has failed the build by looking at the output. This saves a list of failed builds and prints the list at the end of the run. - Add a command line option to mark when abuild is being called recursively. - Add all failed builds to a list. - Print the list when a non-recursive abuild run exits. Change-Id: Icb40ed8083a57bbcde49297d2b0814f98dcbb6c8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/abuild/abuild | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 7c4e29f..93ceac5 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -79,6 +79,9 @@ quiet=false # clang mode enabled by -sb option. scanbuild=false +# Mark whether abuild was called recursively +recursive=false + trap interrupt INT function interrupt @@ -359,6 +362,7 @@ function compile_target printf "failed\n" > compile.status printf "%s build FAILED after %ss!\nLog excerpt:\n" "$BUILD_NAME" "${duration}" tail -n $CONTEXT make.log 2> /dev/null || tail -$CONTEXT make.log + echo "$BUILD_NAME" >> "$FAILED_BOARDS" failed=1 fi cd "$CURR" || return $? @@ -424,6 +428,7 @@ function build_config tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log" junit "</testcase>" + echo "$BUILD_NAME" >> "$FAILED_BOARDS" return fi @@ -585,12 +590,12 @@ getoptbrand="$(getopt -V)" # shellcheck disable=SC2086 if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,verbose,quiet,help,all,target:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,clean,outdir:,chromeos,xmlfile:,kconfig:,dir:,root: -o Vvqhat:p:c:sJCl:rP:uyBLzo:xX:K:d:R: -- "$@") || exit 1 + args=$(getopt -l version,verbose,quiet,help,all,target:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,clean,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive -o Vvqhat:p:c:sJCl:rP:uyBLzo:xX:K:d:R:I -- "$@") || exit 1 eval set -- $args retval=$? else # Detected non-GNU getopt - args=$(getopt Vvqhat:p:c:sJCl:rP:uyBLzo:xX:K:d:R: "$@") + args=$(getopt Vvqhat:p:c:sJCl:rP:uyBLzo:xX:K:d:R:I "$@") set -- $args retval=$? fi @@ -671,6 +676,7 @@ while true ; do configoptions="${configoptions}CONFIG_CHROMEOS=y\n" ;; -X|--xmlfile) shift; XMLFILE=$1; REAL_XMLFILE=$1; shift;; + -I|--recursive) shift; recursive=true;; -K|--kconfig) shift testclass="$(basename "$1" | tr '.' '_' )" customizing="${customizing}, $1 config" @@ -695,6 +701,12 @@ if [ "$customizing" = "" ]; then customizing="default configuration" fi +FAILED_BOARDS="$TOP/$TARGET/failed_boards" + +if [ "$recursive" = "false" ]; then + rm -f "$FAILED_BOARDS" +fi + USE_XARGS=0 if [ "$cpus" != "1" ]; then # Limit to 32 parallel builds for now. @@ -770,7 +782,7 @@ build_targets() fi rm -rf "$TARGET/temp" "$TMPCFG" # shellcheck disable=SC2086 - echo $targets | xargs -P ${cpus:-0} -n 1 "$0" $cmdline -t + echo $targets | xargs -P ${cpus:-0} -n 1 "$0" $cmdline -I -t } fi @@ -814,4 +826,15 @@ else fi junit '</testsuite>' +if [ "$recursive" = "false" ]; then + + # Print the list of failed boards + if [ -f "$FAILED_BOARDS" ]; then + printf "%s build(s) failed:\n" "$( wc -l < "$FAILED_BOARDS" )" + cat "$FAILED_BOARDS" + else + echo "All tested boards passed." + fi +fi + exit $failed

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Patch merged into coreboot/master: util/abuild: Don't set XGCCPATH if it's in the environment
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 14b9b9380a4649a1ec4440f625e34cb25c87df6f Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 30 16:38:25 2016 -0700 util/abuild: Don't set XGCCPATH if it's in the environment Change-Id: I0fa231ca3d33300a671810e994c5be54ac10a18b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/17723 for details. -gerrit

1 0

Patch merged into coreboot/master: mb/asus/p5gc-mx: Remove extra BSEL strap check
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 87fff20356466887d5e879ded540862087e09580 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 18:52:53 2016 +0100 mb/asus/p5gc-mx: Remove extra BSEL strap check This extra check is based on comparing CPU BSEL pins and reports in MCH configuration. This gives false positives in the case of 1333MHz CPUs which automatically get downgraded to 1067MHz by the northbridge (max supported frequency by 945gc). TESTED with Intel Xeon 5460 (does not boot but completes raminit) Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17997 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17997 for details. -gerrit

1 0

Patch merged into coreboot/master: mb/intel/d945gclf: Fix resume from S3 suspend
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit de47fc3317ce34abd91cc2be11827c96ae9bc1f8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 17:52:36 2016 +0100 mb/intel/d945gclf: Fix resume from S3 suspend Checking for dram self refresh in MCHBAR8(SLFRCS) generates false positives. Change-Id: I25afd565cae0269616e38ecbcdf385281bae5d1f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17996 for details. -gerrit

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coreboot-gerrit January 2017