coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: util/inteltool: Add ICH6-10 to BIOS_CNTL list
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 7ff4fe12372ab613ebb1fb2957396910a67200e5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Dec 28 14:00:57 2016 +0100 util/inteltool: Add ICH6-10 to BIOS_CNTL list Without this change inteltool cannot read BIOS_CNTL values nor can it read the SPIBAR values. Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17979 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17979 for details. -gerrit

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Patch merged into coreboot/master: util/inteltool: Fix ICH SPIBAR registers
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit a5798a9b8f0f2b5b026f4935bc8e2c3425e821a8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Dec 28 13:55:23 2016 +0100 util/inteltool: Fix ICH SPIBAR registers The ICH7 SPIBAR offset and registers are different from later generation. ICH8 has a different offset from later generation. ICH6 has no SPI controller. Change-Id: I7691bce619089b15805114047bcb1fd121a5722b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17978 for details. -gerrit

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Patch merged into coreboot/master: sb/nvidia/mcp55: Fix P_state generation
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 1eef32d92b1c091eebe267fbd814be59e381700e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Dec 28 12:35:06 2016 +0100 sb/nvidia/mcp55: Fix P_state generation amd_generate_powernow is never called by in lpc_slave_ops. Move it to lpc_ops like on all other AMD southbridges. TESTED on Gigabyte ga-m57sli-s4 Change-Id: I7db036e681d591a19e15dd3eaafb88b72a41bea1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17977 for details. -gerrit

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Patch merged into coreboot/master: mb/ga-m57sli: Add cmos.default
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit c258bc1ac6de973246121a6f58e76d03c4b0a208 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Dec 26 23:15:24 2016 +0100 mb/ga-m57sli: Add cmos.default If the cmos checksum is incorrect it should fall back to sane defaults. Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17968 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17968 for details. -gerrit

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Patch merged into coreboot/master: superiotool: Add support for HWM registers on W83627EHG
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 072a69e82e0c1322245eadde10f626d332f84f86 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 17 08:56:09 2016 +0100 superiotool: Add support for HWM registers on W83627EHG Based on datasheet: "W83627EHF/EF W83627EHG/EG WINBOND LPC I/O, Revision : 1.0" Change-Id: Ia2e5ab8bc454a34a89fe2cf06bfba55261109785 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17457 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17457 for details. -gerrit

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Patch merged into coreboot/master: superiotool: Add support for HWM registers on W83627DHG
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 4cd95ec1550be0525e333d050fc80d2c88c4b4d8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 15:26:44 2016 +0100 superiotool: Add support for HWM registers on W83627DHG Based on datasheet: "W83627DHG WINBOND LPC I/O, Version: 1.4" Change-Id: Id20dff7539d926ef6f68265efbfc7420539d9bca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17964 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17964 for details. -gerrit

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Patch merged into coreboot/master: google/snappy: Update DPTF settings
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 83560cf004ac25d3386599b9b446eb0794989a83 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Fri Dec 23 04:43:18 2016 -0500 google/snappy: Update DPTF settings 1. Update DPTF TSR1/TSR2 passive/critial trigger points. TSR1 passive point:53, critial point:80 TSR2 passive point:90, critial point:100 2. Update PL1 Min to 4W and PL1 Max to 12W 3. Update thermal relationship table (TRT) setting. BUG=none BRANCH=master TEST=build, boot on snappy dut and verified by thermal team member. Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/17955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17955 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: Update DPTF parameters EVT1_v0.3
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit 0984d1da43dae419695041d9792fa96da91b42aa Author: Tim Chen <Tim-Chen(a)quantatw.com> Date: Wed Dec 28 14:44:52 2016 +0800 mainboard/google/reef: Update DPTF parameters EVT1_v0.3 Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT1_v0.3_20161227.xlsx) 1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU critical point:103 TSR1 passive point:45 TSR2 passive point:55, critical point:90 2. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 3secs Change Charger Effect on Temp Sensor 2 sample rate to 60secs Change CPU Effect on Temp Sensor 1 sample rate to 8secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c Signed-off-by: Tim Chen <Tim-Chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/17975 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17975 for details. -gerrit

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Patch set updated for coreboot: amdmct: Fix offset calculation in mct_ResetDataStruct_D()
by Nico Huber 03 Jan '17

03 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17992 -gerrit commit 13e577d4c98fa19dfe66800476b2e4d1bf7f6e84 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 29 14:03:50 2016 -0700 amdmct: Fix offset calculation in mct_ResetDataStruct_D() The code was intentionally using an offset past the end of the array to get the value of the next byte when starting to clear the structure. The calculated offset was too far off. So rewrite it using offsetof() and sizeof() which is less error-prone. Also make use of memset() and put a comment into the struct's declaration about the fragile code. A correct solution would require more extensive refactoring (e.g. moving the skipped fields out of the struct). Fixes warning for GCC 6.2 toolchain update: src/northbridge/amd/amdfam10/../amdmct/mct/mct_d.c:3628:27: In function 'mct_ResetDataStruct_D': error: index 2 denotes an offset greater than size of 'u8[2][4] {aka unsigned char[2][4]}' [-Werror=array-bounds] Change-Id: Ic81cf5e57992fc0e45f6c96b62a35742a8ef891f Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 25 ++++++++++--------------- src/northbridge/amd/amdmct/mct/mct_d.h | 5 +++++ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626..86cc2e0 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3601,35 +3601,30 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { u8 Node; - u32 i; struct DCTStatStruc *pDCTstat; - u32 start, stop; + size_t start, stop; u8 *p; u16 host_serv1, host_serv2; /* Initialize Data structures by clearing all entries to 0 */ - p = (u8 *) pMCTstat; - for (i = 0; i < sizeof(struct MCTStatStruc); i++) { - p[i] = 0; - } + memset(pMCTstat, 0x00, sizeof(*pMCTstat)); for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; host_serv1 = pDCTstat->HostBiosSrvc1; host_serv2 = pDCTstat->HostBiosSrvc2; - p = (u8 *) pDCTstat; + /* clear everything but CH_D_DIR_B_DQS .. CH_D_BC_RCVRDLY */ + p = (u8 *)pDCTstat; start = 0; - stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop; i++) { - p[i] = 0; - } + stop = offsetof(struct DCTStatStruc, CH_D_DIR_B_DQS); + memset(p + start, 0x00, stop - start); - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); + start = offsetof(struct DCTStatStruc, CH_D_BC_RCVRDLY) + + sizeof(pDCTstat->CH_D_BC_RCVRDLY); stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { - p[i] = 0; - } + memset(p + start, 0x00, stop - start); + pDCTstat->HostBiosSrvc1 = host_serv1; pDCTstat->HostBiosSrvc2 = host_serv2; } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4e1a909..fbfbf6f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -451,6 +451,9 @@ struct DCTStatStruc { /* A per Node structure*/ u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ /* Max Read Latency (ns) for DCT 1*/ + + /* DON'T MOVE the following declarations. They form a + region that's to be skipped in mct_ResetDataStruct_D(). */ u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ @@ -473,6 +476,8 @@ struct DCTStatStruc { /* A per Node structure*/ u8 CH_D_BC_RCVRDLY[2][4]; /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ + /* END DON'T MOVE (see above) */ + u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ /* DIMM# in DCT1*/ u8 MaxDCTs; /* Max number of DCTs in system*/

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Patch merged into coreboot/master: sb/intel/common/gpio: Support ICH9M and prior
by gerrit＠coreboot.org 03 Jan '17

03 Jan '17

the following patch was just integrated into master: commit df369af79e98960afde403d4375ed03f1a648e2a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jan 2 18:41:37 2017 +0100 sb/intel/common/gpio: Support ICH9M and prior Write gpio level twice to make sure the level is set after pins have been configred as GPIO and to minimize glitches on newer hardware. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/18012 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18012 for details. -gerrit

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coreboot-gerrit January 2017