coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: util/romcc: Ensure that bit shift is valid
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18020 -gerrit commit 8524b01ee26cad80295bc0c1b433626bdcd12a75 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 2 21:24:50 2017 +0100 util/romcc: Ensure that bit shift is valid Change-Id: Idbe147c1217f793b0360a752383203c658b0bdce Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1287090 --- util/romcc/romcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 3cc72a7..517ad2a 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -14250,7 +14250,7 @@ static void compute_closure_variables(struct compile_state *state, } /* Find the lowest unused index value */ for(index = 0; index < MAX_INDICIES; index++) { - if (!(used_indicies & (1 << index))) { + if (!(used_indicies & ((uint64_t)1 << index))) { break; } }

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New patch to review for coreboot: cpu/intel/speedstep/acpi.c: Add Netburst and Pentium 4 CPUs
by HAOUAS Elyes 02 Jan '17

02 Jan '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18019 -gerrit commit 8e259c92247e7de72054e9feb4aaaeb783f35136 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Jan 2 21:00:59 2017 +0100 cpu/intel/speedstep/acpi.c: Add Netburst and Pentium 4 CPUs MSR(0x2c) provides information abour FSB frequency Change-Id: I42b0dcfdd62e07422acb77462aefc2d9b62fba19 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/intel/speedstep/acpi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index d85e487..fb06cb6 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -49,7 +49,17 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { - const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; + const u32 fsbcode; + const u32 eax; + msr_t msr; + + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(0x2c); + fsbcode = (msr.lo >> 16) & 7; + } else { + fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; + } + switch (fsbcode) { case 0: return 800; /* / 3 == 266 */ case 1: return 400; /* / 3 == 133 */

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Patch set updated for coreboot: util/crossgcc: update jenkins-build-toolchain
by Nico Huber 02 Jan '17

02 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17766 -gerrit commit bb78b829a80f7540f033de6eda0b3400a0bfe612 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 7 10:45:55 2016 -0700 util/crossgcc: update jenkins-build-toolchain This allows the make jenkins-build-toolchain to use the BUILDGCC_OPTIONS variable. Previously, the options were hardcoded. Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index cf900ba..f7da7de 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -72,8 +72,9 @@ else endif # ifeq ($(COMPILER_OUT_OF_DATE),1) # This target controls what the jenkins builder tests +jenkins-build-toolchain: BUILDGCC_OPTIONS ?= -y --nocolor jenkins-build-toolchain: - $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' rm -f .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does -cat .xcompile

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New patch to review for coreboot: buildgcc: Remove quotes around a $CC call
by Nico Huber 02 Jan '17

02 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18018 -gerrit commit 8ec36be38b735c7b1e76010bec62d8a344c4dd86 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Jan 2 20:51:28 2017 +0100 buildgcc: Remove quotes around a $CC call If we use ccache we have to interpret spaces in $CC as separation characters. The downside is that we can't support spaces in the compiler's path. But, well... Change-Id: I4e6e6324389354669a755f570083a40ff00b1bbf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 273f921..0dfca26 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -517,7 +517,7 @@ set_hostcflags_from_gmp() { build_GMP() { # Check if GCC enables `-pie` by default (possible since GCC 6). # We need PIC in all static libraries then. - if "${CC}" -dumpspecs 2>/dev/null | grep -q '[{;][[:space:]]*:-pie\>' + if $CC -dumpspecs 2>/dev/null | grep -q '[{;][[:space:]]*:-pie\>' then OPTIONS="$OPTIONS --with-pic" fi

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Patch set updated for coreboot: util/crossgcc: update jenkins-build-toolchain
by Nico Huber 02 Jan '17

02 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17766 -gerrit commit 3fc8df21b2e196591cbbf916519014e167a73dc1 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 7 10:45:55 2016 -0700 util/crossgcc: update jenkins-build-toolchain This allows the make jenkins-build-toolchain to use the BUILDGCC_OPTIONS variable. Previously, the options were hardcoded. Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index cf900ba..f7da7de 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -72,8 +72,9 @@ else endif # ifeq ($(COMPILER_OUT_OF_DATE),1) # This target controls what the jenkins builder tests +jenkins-build-toolchain: BUILDGCC_OPTIONS ?= -y --nocolor jenkins-build-toolchain: - $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' rm -f .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does -cat .xcompile

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Patch set updated for coreboot: sb/intel/common/gpio: Support ICH9M and prior
by Patrick Rudolph 02 Jan '17

02 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18012 -gerrit commit bcbfa71014eea7014f943ae7083c4d9c301352a8 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jan 2 18:41:37 2017 +0100 sb/intel/common/gpio: Support ICH9M and prior Write gpio level twice to make sure the level is set after pins have been configred as GPIO and to minimize glitches on newer hardware. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/southbridge/intel/common/gpio.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index aadd519..d861383 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -37,6 +37,13 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) { u16 gpiobase = get_gpio_base(); + /* The order of these calls does matter on ICH9M and prior. + * The level has to be set on pins configured as gpio, + * but on newer platforms we want to change the level first + * to make sure there are no glitches on the lines ! + * Write the gpio level twice to satisfy both requirements. + */ + /* GPIO Set 1 */ if (gpio->set1.level) outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); @@ -44,6 +51,8 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); if (gpio->set1.direction) outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); if (gpio->set1.reset) outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); if (gpio->set1.invert) @@ -58,6 +67,8 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); if (gpio->set2.direction) outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); if (gpio->set2.reset) outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); @@ -68,6 +79,8 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); if (gpio->set3.direction) outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); if (gpio->set3.reset) outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); }

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Patch set updated for coreboot: sb/intel/common/gpio: Support ICH9M and prior
by Patrick Rudolph 02 Jan '17

02 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18012 -gerrit commit 1a942f182fa2e6c5eb6e04979ab4b3b45fd2268c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jan 2 18:41:37 2017 +0100 sb/intel/common/gpio: Support ICH9M and prior Reorder the commands executed to support ICH9M and prior where GPIO level and direction are only set on pins configured as GPIO. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/southbridge/intel/common/gpio.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index aadd519..d861383 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -37,6 +37,13 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) { u16 gpiobase = get_gpio_base(); + /* The order of these calls does matter on ICH9M and prior. + * The level has to be set on pins configured as gpio, + * but on newer platforms we want to change the level first + * to make sure there are no glitches on the lines ! + * Write the gpio level twice to satisfy both requirements. + */ + /* GPIO Set 1 */ if (gpio->set1.level) outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); @@ -44,6 +51,8 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); if (gpio->set1.direction) outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); if (gpio->set1.reset) outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); if (gpio->set1.invert) @@ -58,6 +67,8 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); if (gpio->set2.direction) outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); if (gpio->set2.reset) outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); @@ -68,6 +79,8 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); if (gpio->set3.direction) outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); if (gpio->set3.reset) outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); }

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Patch set updated for coreboot: util/crossgcc: update jenkins-build-toolchain
by Martin Roth 02 Jan '17

02 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17766 -gerrit commit 8613d3514faa17b09b12c60d4bc9564d7f3c3d46 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 7 10:45:55 2016 -0700 util/crossgcc: update jenkins-build-toolchain This allows the make jenkins-build-toolchain to use the BUILDGCC_OPTIONS variable. Previously, the options were hardcoded. Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index cf900ba..f7da7de 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -72,8 +72,9 @@ else endif # ifeq ($(COMPILER_OUT_OF_DATE),1) # This target controls what the jenkins builder tests +jenkins-build-toolchain: BUILDGCC_OPTIONS ?= -y --nocolor jenkins-build-toolchain: - $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' rm -f .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does -cat .xcompile

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New patch to review for coreboot: util/romcc: avoid leaking a type
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18017 -gerrit commit d564d7fd7869ffd53ccc6d07377c825c956922e9 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 2 19:24:48 2017 +0100 util/romcc: avoid leaking a type Only allocate ptr_type when it's actually used. Change-Id: Iea5f93601a42f02a1866bdff099f63935fdd5b8d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129117 --- util/romcc/romcc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 3574ca0..3cc72a7 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -7266,22 +7266,25 @@ static struct triple *do_mk_addr_expr(struct compile_state *state, struct triple *expr, struct type *type, ulong_t offset) { struct triple *result; - struct type *ptr_type; clvalue(state, expr); - ptr_type = new_type(TYPE_POINTER | (type->type & QUAL_MASK), type, 0); - result = 0; if (expr->op == OP_ADECL) { error(state, expr, "address of auto variables not supported"); } else if (expr->op == OP_SDECL) { + struct type *ptr_type; + ptr_type = new_type(TYPE_POINTER | (type->type & QUAL_MASK), type, 0); + result = triple(state, OP_ADDRCONST, ptr_type, 0, 0); MISC(result, 0) = expr; result->u.cval = offset; } else if (expr->op == OP_DEREF) { + struct type *ptr_type; + ptr_type = new_type(TYPE_POINTER | (type->type & QUAL_MASK), type, 0); + result = triple(state, OP_ADD, ptr_type, RHS(expr, 0), int_const(state, &ulong_type, offset));

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New patch to review for coreboot: util/romcc: avoid dereferencing NULL pointer
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18016 -gerrit commit 997e1da9466b98d917d4afadb7621c27a8935329 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 2 19:15:44 2017 +0100 util/romcc: avoid dereferencing NULL pointer argv is only filled for macro->argc > 0. Change-Id: I5ff21098384afc823efa14be3d5565507fb2b3b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1287089 --- util/romcc/romcc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 7217c8c..3574ca0 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -4580,6 +4580,9 @@ static void expand_macro(struct compile_state *state, flen = fmacro.pos - fstart; switch(tk->tok) { case TOK_IDENT: + if (macro->argc < 0) { + break; + } for(i = 0; i < macro->argc; i++) { if (argv[i].ident == tk->ident) { break;

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coreboot-gerrit January 2017