coreboot-gerrit January 2017

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Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 02 Jan '17

02 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit 3f3dd6e1a30a34343aaebfb48c0d69d6c16be4f5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It stores the results of receive enable in 256 bits in the unused upper 1024 bits sized region of nvram. Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 ++++-- src/northbridge/intel/x4x/pcie.c | 15 ++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 33 ++++++++++++++++---------- src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 41 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index da51ea0..672b502 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -138,6 +138,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -157,16 +158,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(0xf14) & (1 << 8)) boot_path = BOOT_PATH_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9026a33..dd10e3f 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1560,7 +1560,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_RESET) { + if ((s->boot_path == BOOT_PATH_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2047,7 +2048,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path == BOOT_PATH_NORMAL) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2094,16 +2096,23 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; // Dummy writes / reads - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + if (s->boot_path == BOOT_PATH_NORMAL) { + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); + } } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index f86d1cc..ce4463e 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

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Patch set updated for coreboot: nb/intel/x4x: Fix raminit on reset path
by Arthur Heymans 02 Jan '17

02 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18009 -gerrit commit a1db9fb8ceb3f302f80e3c3e0ca9da4f10b92b2a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/intel/x4x: Fix raminit on reset path If the system undergoes a hot reset some steps in raminit must not be done. Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +- src/northbridge/intel/x4x/raminit_ddr2.c | 134 ++++++++++++++++++++---- src/northbridge/intel/x4x/x4x.h | 3 + 4 files changed, 122 insertions(+), 23 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 3138479..946d1a1 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -68,6 +68,7 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum +1024 256 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 2503db9..da51ea0 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -29,6 +29,7 @@ #include <lib.h> #include <arch/stages.h> #include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) @@ -136,6 +137,7 @@ void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -155,8 +157,11 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + if (MCHBAR32(0xf14) & (1 << 8)) + boot_path = BOOT_PATH_RESET; + printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..9026a33 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -20,6 +20,9 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <pc80/mc146818rtc.h> +/* only Needed for RCBA32 so it's ok to only include ICH7 function */ +#include <southbridge/intel/i82801gx/i82801gx.h> #include "iomap.h" #include "x4x.h" @@ -258,10 +261,13 @@ static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; u8 reset = 0; + u32 pmir; + pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac); pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1; @@ -273,10 +279,16 @@ static void checkreset_ddr2(struct sysinfo *s) } if (reset) { printk(BIOS_DEBUG, "Reset...\n"); + /* Do a global reset. only useful on ICH10 */ + pmir |= (1 << 20); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); outb(0xe, 0xcf9); asm ("hlt"); } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); + pmir &= ~(1 << 20); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); } static void setioclk_ddr2(struct sysinfo *s) @@ -1486,6 +1498,76 @@ static void rcven_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "End rcven\n"); } +static void sdram_save_receive_enable(void) +{ + int i = 0, j; + u32 reg32; + u16 reg16; + u8 values[32]; + u8 lane, ch; + + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) + values[i++] = MCHBAR8(0x400*ch + 0x560 + (lane*4)); + reg32 = MCHBAR32(0x400*ch + 0x248); + for (j = 0; j < 4; j++) + values[i++] = (reg32 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x5fa); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x58c); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(values); i++) + cmos_write(values[i], 128 + i); +} + +static void sdram_recover_receive_enable(void) +{ + u8 i, j; + u32 reg32 = 0; + u16 reg16 = 0; + u8 values[32]; + u8 ch, lane; + + for (i = 0; i < ARRAY_SIZE(values); i++) + values[i] = cmos_read(128 + i); + + i = 0; + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = values[i++]; + for (j = 0; j < 4; j++) + reg32 |= (values[i++] << (j * 8)); + MCHBAR32(0x400*ch + 0x248) = reg32; + reg32 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x5fa) = reg16; + reg16 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x58c) = reg16; + reg16 = 0; + } +} + +static void sdram_program_receive_enable(struct sysinfo *s) +{ + /* enable upper CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Program Receive Enable Timings */ + if (s->boot_path == BOOT_PATH_RESET) { + sdram_recover_receive_enable(); + } else { + rcven_ddr2(s); + sdram_save_receive_enable(); + } +} + static void dradrb_ddr2(struct sysinfo *s) { u8 map, i, ch, r, rankpop0, rankpop1; @@ -1860,22 +1942,23 @@ void raminit_ddr2(struct sysinfo *s) checkreset_ddr2(s); // Clear self refresh - MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + if (s->boot_path != BOOT_PATH_RESET) { + MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; - // Clear host clk gate reg - MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; - // Select DDR2 - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; - // Set freq - MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | - (s->selected_timings.mem_clk << 4) | (1 << 10); + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clk << 4) | (1 << 10); - // Overwrite freq if chipset rejects it - s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; - if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { - die("Error: DDR is faster than FSB, halt\n"); + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clk > (s->max_fsb + 3)) + die("Error: DDR is faster than FSB, halt\n"); } udelay(250000); @@ -1885,8 +1968,10 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done clk crossing\n"); // DDR2 IO - setioclk_ddr2(s); - printk(BIOS_DEBUG, "Done I/O clk\n"); + if (s->boot_path != BOOT_PATH_RESET) { + setioclk_ddr2(s); + printk(BIOS_DEBUG, "Done I/O clk\n"); + } // Grant to launch launch_ddr2(s); @@ -1900,16 +1985,21 @@ void raminit_ddr2(struct sysinfo *s) dll_ddr2(s); // RCOMP - rcomp_ddr2(s); - printk(BIOS_DEBUG, "RCOMP\n"); + if (s->boot_path != BOOT_PATH_RESET) { + rcomp_ddr2(s); + printk(BIOS_DEBUG, "RCOMP\n"); + } // ODT odt_ddr2(s); printk(BIOS_DEBUG, "Done ODT\n"); // RCOMP update - while ((MCHBAR8(0x130) & 1) != 0 ); - printk(BIOS_DEBUG, "Done RCOMP update\n"); + if (s->boot_path != BOOT_PATH_RESET) { + while ((MCHBAR8(0x130) & 1) != 0) + ; + printk(BIOS_DEBUG, "Done RCOMP update\n"); + } // Set defaults MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; @@ -1989,7 +2079,7 @@ void raminit_ddr2(struct sysinfo *s) } // Receive enable - rcven_ddr2(s); + sdram_program_receive_enable(s); printk(BIOS_DEBUG, "Done rcven\n"); // Finish rcven diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f..f86d1cc 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0,

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Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 02 Jan '17

02 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit 3e848ec69095d37098b0f1dbef4e40f929552bc2 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It stores the results of receive enable in 256 bits in the unused upper 1024 bits sized region of nvram. Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 ++++-- src/northbridge/intel/x4x/pcie.c | 15 ++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 33 ++++++++++++++++---------- src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 41 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index da51ea0..672b502 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -138,6 +138,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -157,16 +158,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(0xf14) & (1 << 8)) boot_path = BOOT_PATH_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9026a33..dd10e3f 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1560,7 +1560,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_RESET) { + if ((s->boot_path == BOOT_PATH_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2047,7 +2048,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path == BOOT_PATH_NORMAL) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2094,16 +2096,23 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; // Dummy writes / reads - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + if (s->boot_path == BOOT_PATH_NORMAL) { + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); + } } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index f86d1cc..ce4463e 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

1 0

New patch to review for coreboot: nb/intel/x4x: Fix raminit on reset path
by Arthur Heymans 02 Jan '17

02 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18009 -gerrit commit 0ac270af783d0d113848b18f6be86e577039f039 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/intel/x4x: Fix raminit on reset path If the system undergoes a hot reset some steps in raminit must not be done. Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +- src/northbridge/intel/x4x/raminit_ddr2.c | 134 ++++++++++++++++++++---- src/northbridge/intel/x4x/x4x.h | 3 + 4 files changed, 122 insertions(+), 23 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 3138479..cee6fe9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -68,6 +68,7 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum +1024 256 h 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 2503db9..da51ea0 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -29,6 +29,7 @@ #include <lib.h> #include <arch/stages.h> #include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) @@ -136,6 +137,7 @@ void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -155,8 +157,11 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + if (MCHBAR32(0xf14) & (1 << 8)) + boot_path = BOOT_PATH_RESET; + printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..9026a33 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -20,6 +20,9 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <pc80/mc146818rtc.h> +/* only Needed for RCBA32 so it's ok to only include ICH7 function */ +#include <southbridge/intel/i82801gx/i82801gx.h> #include "iomap.h" #include "x4x.h" @@ -258,10 +261,13 @@ static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; u8 reset = 0; + u32 pmir; + pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac); pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1; @@ -273,10 +279,16 @@ static void checkreset_ddr2(struct sysinfo *s) } if (reset) { printk(BIOS_DEBUG, "Reset...\n"); + /* Do a global reset. only useful on ICH10 */ + pmir |= (1 << 20); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); outb(0xe, 0xcf9); asm ("hlt"); } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); + pmir &= ~(1 << 20); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); } static void setioclk_ddr2(struct sysinfo *s) @@ -1486,6 +1498,76 @@ static void rcven_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "End rcven\n"); } +static void sdram_save_receive_enable(void) +{ + int i = 0, j; + u32 reg32; + u16 reg16; + u8 values[32]; + u8 lane, ch; + + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) + values[i++] = MCHBAR8(0x400*ch + 0x560 + (lane*4)); + reg32 = MCHBAR32(0x400*ch + 0x248); + for (j = 0; j < 4; j++) + values[i++] = (reg32 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x5fa); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x58c); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(values); i++) + cmos_write(values[i], 128 + i); +} + +static void sdram_recover_receive_enable(void) +{ + u8 i, j; + u32 reg32 = 0; + u16 reg16 = 0; + u8 values[32]; + u8 ch, lane; + + for (i = 0; i < ARRAY_SIZE(values); i++) + values[i] = cmos_read(128 + i); + + i = 0; + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = values[i++]; + for (j = 0; j < 4; j++) + reg32 |= (values[i++] << (j * 8)); + MCHBAR32(0x400*ch + 0x248) = reg32; + reg32 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x5fa) = reg16; + reg16 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x58c) = reg16; + reg16 = 0; + } +} + +static void sdram_program_receive_enable(struct sysinfo *s) +{ + /* enable upper CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Program Receive Enable Timings */ + if (s->boot_path == BOOT_PATH_RESET) { + sdram_recover_receive_enable(); + } else { + rcven_ddr2(s); + sdram_save_receive_enable(); + } +} + static void dradrb_ddr2(struct sysinfo *s) { u8 map, i, ch, r, rankpop0, rankpop1; @@ -1860,22 +1942,23 @@ void raminit_ddr2(struct sysinfo *s) checkreset_ddr2(s); // Clear self refresh - MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + if (s->boot_path != BOOT_PATH_RESET) { + MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; - // Clear host clk gate reg - MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; - // Select DDR2 - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; - // Set freq - MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | - (s->selected_timings.mem_clk << 4) | (1 << 10); + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clk << 4) | (1 << 10); - // Overwrite freq if chipset rejects it - s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; - if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { - die("Error: DDR is faster than FSB, halt\n"); + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clk > (s->max_fsb + 3)) + die("Error: DDR is faster than FSB, halt\n"); } udelay(250000); @@ -1885,8 +1968,10 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done clk crossing\n"); // DDR2 IO - setioclk_ddr2(s); - printk(BIOS_DEBUG, "Done I/O clk\n"); + if (s->boot_path != BOOT_PATH_RESET) { + setioclk_ddr2(s); + printk(BIOS_DEBUG, "Done I/O clk\n"); + } // Grant to launch launch_ddr2(s); @@ -1900,16 +1985,21 @@ void raminit_ddr2(struct sysinfo *s) dll_ddr2(s); // RCOMP - rcomp_ddr2(s); - printk(BIOS_DEBUG, "RCOMP\n"); + if (s->boot_path != BOOT_PATH_RESET) { + rcomp_ddr2(s); + printk(BIOS_DEBUG, "RCOMP\n"); + } // ODT odt_ddr2(s); printk(BIOS_DEBUG, "Done ODT\n"); // RCOMP update - while ((MCHBAR8(0x130) & 1) != 0 ); - printk(BIOS_DEBUG, "Done RCOMP update\n"); + if (s->boot_path != BOOT_PATH_RESET) { + while ((MCHBAR8(0x130) & 1) != 0) + ; + printk(BIOS_DEBUG, "Done RCOMP update\n"); + } // Set defaults MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; @@ -1989,7 +2079,7 @@ void raminit_ddr2(struct sysinfo *s) } // Receive enable - rcven_ddr2(s); + sdram_program_receive_enable(s); printk(BIOS_DEBUG, "Done rcven\n"); // Finish rcven diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f..f86d1cc 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0,

1 0

Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 02 Jan '17

02 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit be5faf6cff9539f1e8ec9507b02f034b28d79595 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It stores the results of receive enable in 256 bits in the unused upper 1024 bits sized region of nvram. Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 ++++-- src/northbridge/intel/x4x/pcie.c | 15 +++++++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 31 ++++++++++++++++---------- src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 39 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index da51ea0..672b502 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -138,6 +138,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -157,16 +158,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(0xf14) & (1 << 8)) boot_path = BOOT_PATH_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9026a33..ee0a213 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1560,7 +1560,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_RESET) { + if ((s->boot_path == BOOT_PATH_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2047,7 +2048,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path == BOOT_PATH_NORMAL) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2094,16 +2096,21 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; // Dummy writes / reads - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + if (s->boot_path == BOOT_PATH_NORMAL) { + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones, + Read: [0x%08x]=0x%08x\n", reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros, + Read: [0x%08x]=0x%08x\n", reg32, data); + } } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index f86d1cc..ce4463e 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

1 0

New patch to review for coreboot: vboot: Clear battery cutoff flags when vbnv_cmos loads backup VBNV.
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18008 -gerrit commit 62bdfb6c28803475eaa456d63201de813341eea1 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Dec 29 20:59:37 2016 +0800 vboot: Clear battery cutoff flags when vbnv_cmos loads backup VBNV. When CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH is set, vbnv_cmos will try to load VBNV from flash if the VBNV in CMOS is invalid. This is usually correct, except the case of battery cut-off. CMOS will always be invalid after battery cut-off if there is no RTC battery (or if that is dead). However, in current implementation the backup in flash is only updated in Coreboot, while the real battery cutoff (and the clearing of cutoff flags in VBNV) is done in payload (Depthcharge) stage. This will create an endless reboot loop that: 1. crossystem sets battery cutoff flag in VBNV_CMOS then reboot. 2. Coreboot backups VBNV_CMOS to VBNV_flash. 3. Depthcharge sees cutoff flag in VBNV_CMOS. 4. Depthcharge clears cutoff flag in VBNV_CMOS. 5. Depthcharge performs battery cutoff (CMOS data is lost). 6. (Plug AC adapter) Reboot. 7. Coreboot sees invalid VBNV_CMOS, load backup from VBNV_flash. 8. Jump to 3. As a result, we should always clear battery cutoff flags when loading backups from VBNV_flash. BRANCH=glados,reef BUG=chrome-os-partner:61365,chrome-os-partner:59615 TEST=emerge-reef coreboot bootimage; Change-Id: I3250a3a179a7b0de9c6e401e4a94dcd23920e473 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/423460 Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/vboot/vbnv.c | 6 ++++++ src/vboot/vbnv.h | 1 + src/vboot/vbnv_cmos.c | 17 +++++++++++++++++ src/vboot/vbnv_layout.h | 3 +++ 4 files changed, 27 insertions(+) diff --git a/src/vboot/vbnv.c b/src/vboot/vbnv.c index ce64928..6537bf0 100644 --- a/src/vboot/vbnv.c +++ b/src/vboot/vbnv.c @@ -79,6 +79,12 @@ int verify_vbnv(uint8_t *vbnv_copy) (crc8_vbnv(vbnv_copy, CRC_OFFSET) == vbnv_copy[CRC_OFFSET]); } +/* Re-generate VBNV checksum. */ +void regen_vbnv_crc(uint8_t *vbnv_copy) +{ + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); +} + /* * Read VBNV data from configured storage backend. * If VBNV verification fails, reset the vbnv copy. diff --git a/src/vboot/vbnv.h b/src/vboot/vbnv.h index 78ca8f6..30da6a5 100644 --- a/src/vboot/vbnv.h +++ b/src/vboot/vbnv.h @@ -22,6 +22,7 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); +void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); int vboot_wants_oprom(void); diff --git a/src/vboot/vbnv_cmos.c b/src/vboot/vbnv_cmos.c index 5eda8e6..b7ef3e7 100644 --- a/src/vboot/vbnv_cmos.c +++ b/src/vboot/vbnv_cmos.c @@ -20,6 +20,22 @@ #include <vboot/vbnv.h> #include <vboot/vbnv_layout.h> +static void clear_vbnv_battery_cutoff_flag(uint8_t *vbnv_copy) +{ + /* + * Currently battery cutoff is done in payload stage, which does not + * update backup VBNV. And doing battery cutoff will invalidate CMOS. + * This means for every reboot after cutoff, read_vbnv_cmos will reload + * backup VBNV and try to cutoff again, causing endless reboot loop. + * So we should always clear battery cutoff flag from loaded backup. + */ + if (vbnv_copy[MISC_FLAGS_OFFSET] & MISC_FLAGS_BATTERY_CUTOFF_MASK) { + printk(BIOS_INFO, "VBNV: Remove battery cut-off request.\n"); + vbnv_copy[MISC_FLAGS_OFFSET] &= ~MISC_FLAGS_BATTERY_CUTOFF_MASK; + regen_vbnv_crc(vbnv_copy); + } +} + void read_vbnv_cmos(uint8_t *vbnv_copy) { int i; @@ -35,6 +51,7 @@ void read_vbnv_cmos(uint8_t *vbnv_copy) read_vbnv_flash(vbnv_copy); if (verify_vbnv(vbnv_copy)) { + clear_vbnv_battery_cutoff_flag(vbnv_copy); save_vbnv_cmos(vbnv_copy); printk(BIOS_INFO, "VBNV: Flash backup restored\n"); } else { diff --git a/src/vboot/vbnv_layout.h b/src/vboot/vbnv_layout.h index 59acd0c..1dc01c9 100644 --- a/src/vboot/vbnv_layout.h +++ b/src/vboot/vbnv_layout.h @@ -41,6 +41,9 @@ #define DEV_BOOT_USB_MASK 0x01 #define DEV_BOOT_SIGNED_ONLY_MASK 0x02 +#define MISC_FLAGS_OFFSET 8 +#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 + #define KERNEL_FIELD_OFFSET 11 #define CRC_OFFSET 15

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New patch to review for coreboot: rockchip/common: Loosen I2C frequency target requirements
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18007 -gerrit commit 02e37466ed490610d43dab529c1d9c7182ba6437 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Dec 16 16:03:57 2016 -0800 rockchip/common: Loosen I2C frequency target requirements I've recently added an assertion to ensure that the effective I2C frequency on Rockchip SoCs is not too far off the 400KHz target due to divisor rounding errors. A 10KHz margin worked fine for RK3399, but it turns out that RK3288 actually only ever hit 387KHz since its I2C clocks are based off the already pretty low 75MHz PCLKs. While we could probably change the PCLKs to make this closer, that seems like a too intrusive change for something that has already worked just fine for years, so just loosen the restriction a little more instead. BRANCH=None BUG=chromium:675043 TEST=None Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421095 Reviewed-by: Randall Spangler <rspangler(a)chromium.org> --- src/soc/rockchip/common/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index a00d538..032efda 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -286,6 +286,6 @@ void i2c_init(unsigned int bus, unsigned int hz) i2c_clk = i2c_src_clk / (8 * (divl + 1 + divh + 1)); printk(BIOS_DEBUG, "I2C bus %u: %uHz (divh = %u, divl = %u)\n", bus, i2c_clk, divh, divl); - assert((divh < 65536) && (divl < 65536) && hz - i2c_clk < 10*KHz); + assert((divh < 65536) && (divl < 65536) && hz - i2c_clk < 15*KHz); write32(&regs->i2c_clkdiv, (divh << 16) | (divl << 0)); }

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New patch to review for coreboot: i2c/tpm: Ignore 0xFF bytes for status and burstCount
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18006 -gerrit commit 113317eafa9d8a42292b46623ef9285707503fe8 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Nov 30 17:46:17 2016 -0800 i2c/tpm: Ignore 0xFF bytes for status and burstCount We've found that the SLB9645 TPM sometimes seems to randomly start returning 0xFF bytes for all requests. The exact cause is yet unknown, but we should try to write our TIS code such that it avoids bad interactions with this kind of response (e.g. any wait_for_status() immediately succeeds because all "status bits" are set in the response). At least for status and burstCount readings we can say for sure that the value is nonsensical and we're already reading those in a loop until we get valid results anyway, so let's add code to explicitly discount 0xFF bytes. BRANCH=oak BUG=chrome-os-partner:55764 TEST=None Change-Id: I934d42c36d6847a22a185795cea49d282fa113d9 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420470 Reviewed-by: Nicolas Boichat <drinkcat(a)chromium.org> --- src/drivers/i2c/tpm/tpm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 55c25fe..972b17d 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -291,6 +291,8 @@ static uint8_t tpm_tis_i2c_status(struct tpm_chip *chip) uint8_t buf; if (iic_tpm_read(TPM_STS(chip->vendor.locality), &buf, 1) < 0) return 0; + else if (buf == 0xff) /* Some TPMs sometimes randomly return 0xff. */ + return 0; else return buf; } @@ -316,7 +318,7 @@ static ssize_t get_burstcount(struct tpm_chip *chip) else burstcnt = (buf[2] << 16) + (buf[1] << 8) + buf[0]; - if (burstcnt) + if (burstcnt && burstcnt != 0xffffff) return burstcnt; mdelay(TPM_TIMEOUT); timeout--;

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New patch to review for coreboot: Revert "google/oak: increase the driving strength for 4GB DRAMs"
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18005 -gerrit commit 43cbf6cc16d0eeee579a98a13ec4a40d97ccc3b4 Author: Nicolas Boichat <drinkcat(a)google.com> Date: Wed Dec 14 17:26:12 2016 +0800 Revert "google/oak: increase the driving strength for 4GB DRAMs" This reverts commit 34a6537512d412363bf56428b7ae284e6dd80fb3, which appears to cause random stability issues on some elm units. BRANCH=oak BUG=chrome-os-partner:60869 BUG=chromium:673349 TEST=None Change-Id: I5ce9e2673db1bc7a1f487a3c3bcce4651a5e3567 Reviewed-on: https://chromium-review.googlesource.com/419862 Commit-Ready: Nicolas Boichat <drinkcat(a)chromium.org> Tested-by: Nicolas Boichat <drinkcat(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- .../google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBLTBLAR-4GB.inc | 4 ++-- src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc | 4 ++-- src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBLTBLAR-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBLTBLAR-4GB.inc index 6e3b203..099a07c 100644 --- a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBLTBLAR-4GB.inc +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBLTBLAR-4GB.inc @@ -1,7 +1,7 @@ { /* 2GB (8Gb + 8Gb) for single rank dram setting */ { - .impedance_drvp = 0xc, - .impedance_drvn = 0xd, + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, .datlat_ucfirst = 19, .ca_train = { diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc index f03f858..0fe16a6 100644 --- a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc @@ -1,7 +1,7 @@ { /* 4GB (16Gb + 16Gb) for dual rank dram setting */ { - .impedance_drvp = 0xc, - .impedance_drvn = 0xd, + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, .datlat_ucfirst = 19, .ca_train = { diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc index a9fbcf1..e6c3a83 100644 --- a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc @@ -1,7 +1,7 @@ { /* 4GB (16Gb + 16Gb) for dual rank dram setting */ { - .impedance_drvp = 0xc, - .impedance_drvn = 0xd, + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, .datlat_ucfirst = 18, .ca_train = {

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Patch set updated for coreboot: util/cbfstool: Fix to build with latest llvm
by Patrick Georgi 02 Jan '17

02 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17568 -gerrit commit 41744be2aea19532016b59b21c9298cf512154a8 Author: Manoj Gupta <manojgupta(a)google.com> Date: Mon Nov 14 11:19:30 2016 -0800 util/cbfstool: Fix to build with latest llvm cbfs-payload-linux.c:255:43: note: add parentheses around left hand side expression to silence this warning if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { BUG=chromium:665657 TEST=coreboot-utils builds Change-Id: I025c784330885cce8ae43c44f9d938394af30ed5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 35c4935f2a89c3d3b45213372bcf0474a60eda43 Original-Change-Id: I8758e7d158ca32e87107797f2a33b9d9a0e4676f Original-Reviewed-on: https://chromium-review.googlesource.com/411335 Original-Commit-Ready: Manoj Gupta <manojgupta(a)chromium.org> Original-Tested-by: Manoj Gupta <manojgupta(a)chromium.org> Original-Reviewed-by: Mike Frysinger <vapier(a)chromium.org> --- util/cbfstool/cbfs-payload-linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index afb0f3a..ac7e729 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -252,7 +252,7 @@ int parse_bzImage_to_payload(const struct buffer *input, } unsigned long kernel_base = 0x100000; - if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { + if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags)) { kernel_base = 0x1000; /* zImage kernel */ } /* kernel prefers an address, so listen */

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coreboot-gerrit January 2017