the following patch was just integrated into master:
commit 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Mon Nov 28 00:29:10 2016 +1100
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson(a)raptorengineering.com>
See https://review.coreboot.org/17625 for details.
-gerrit
Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18031
-gerrit
commit ea9d9fa7163be92936d9eea93b65412856863d1b
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Wed Jan 4 08:51:52 2017 -0800
vboot: Remove rmu.bin from FW_MAIN_A and FW_MAIN_B
Add rmu.bin to the list of files that exist only in the read-only
section (COREBOOT) of the SPI flash.
TEST=Build and run on Galileo Gen2.
Change-Id: I30cbd3fb2ef1848807e4de4c479dc7a561c1faba
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/vboot/Makefile.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc
index 33109de..c03d639 100644
--- a/src/vboot/Makefile.inc
+++ b/src/vboot/Makefile.inc
@@ -152,6 +152,7 @@ regions-for-file = $(subst $(spc),$(comma),$(sort \
locale_%.bin \
font.bin \
vbgfx.bin \
+ rmu.bin \
,$(1)),COREBOOT,COREBOOT FW_MAIN_A FW_MAIN_B)))
endif # CONFIG_VBOOT
Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18030
-gerrit
commit 691d07bf912b9c6ab288b6ba2acf1341ec620c47
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Wed Jan 4 08:24:23 2017 -0800
soc/intel/quark: Properly place rmu.bin for vboot
Properly locate the rmu.bin file when using vboot. Without this patch
the build fails because the offset is outside the CBFS range. With
this patch, the file is placed properly in the COREBOOT section of the
SPI flash and is also placed in the FW_MAIN_A and FW_MAIN_B areas as
well.
CBFS rmu.bin
E: Could not add [3rdparty/blobs/soc/intel/quark/rmu.bin, 8192 bytes (8 KB)@0x4f0000]; too big?
E: Failed to add '3rdparty/blobs/soc/intel/quark/rmu.bin' into ROM image.
E: Failed while operating on 'FW_MAIN_A' region!
E: The image will be left unmodified.
make: *** [build/coreboot.pre] Error 1
TEST=Build and run on Galileo Gen2
Change-Id: I4a9bf1814651edde08c5d23c36580929bb6af7df
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Makefile.inc | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index bd297ed..fd7a7a7 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -74,7 +74,11 @@ fsp.bin-type := raw
# Add the chipset microcode file to the CBFS image
cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
-rmu.bin-position := $(CONFIG_RMU_LOC)
rmu.bin-type := raw
+ifeq ($(CONFIG_VBOOT),y)
+rmu.bin-COREBOOT-position := $(CONFIG_RMU_LOC)
+else
+rmu.bin-position := $(CONFIG_RMU_LOC)
+endif # CONFIG_VBOOT
endif # CONFIG_SOC_INTEL_QUARK
the following patch was just integrated into master:
commit 6c20b65849aeda664cc40ebc0f0bab2e99768423
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Dec 29 22:54:02 2016 +0100
intel/i945 boards: Add romstage time stamps
Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.
Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.
Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See https://review.coreboot.org/17993 for details.
-gerrit
the following patch was just integrated into master:
commit 68fdb785b2183cfa3312266b4a800174ba2d64e5
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sat Dec 31 08:21:56 2016 -0800
soc/intel/quark: Add monotonic timer support
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the
TSC for the monotonic timer. Simplify the routine to get the TSC
frequency.
TEST=Build and run on Galileo Gen2
Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/18002
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/18002 for details.
-gerrit