coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: cpu/intel/model_6fx: Add Conroe-L to cpu_device_id list
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 3f2d6c0cf303228d577a19baae9ecea15c78f45e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Jan 8 21:14:46 2017 +0100 cpu/intel/model_6fx: Add Conroe-L to cpu_device_id list Tested with Intel® Celeron® Processor 420. Change-Id: I63d308477a22a9e55ceed1b6b36e63a3044c2354 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18057 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18057 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/945gc: Hardcode the integrated graphic frequencies
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 18537817484580fef1f154cb3fcb2574d3f5a858 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Dec 28 21:20:45 2016 +0100 nb/intel/945gc: Hardcode the integrated graphic frequencies The code to set the igd frequencies is written with the mobile version of the 945 chipset in mind and seems to cause cause strange igd related problems on the desktop versions. Some possible problems are: * on 800MHz fsb CPUs the igd sometimes has artifacts on the screen; * on 800MHz fsb CPU memtest results vary a lot; * since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using variant board scheme" that does not affect this northbridge, the display shows garbage as soon as Linux (4.8) modesets the display. A fix is to hardcode the core display and render clocks to their maximum, potentially also improving graphical performance. Vendor bios on all boards in coreboot with this northbridge have the same value in this PCI config address. TESTED on P5GC-MX (display works fine again in Linux) and user reports of it making GA-945GCM-S2L run more stable. Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17981 for details. -gerrit

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Patch set updated for coreboot: chromeos: fix build issues within sar.c
by Robbie Zhang 10 Jan '17

10 Jan '17

Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18076 -gerrit commit 2a7fcad441815754fced6a07f6c2eaa09b1cb492 Author: Robbie Zhang <robbie.zhang(a)intel.com> Date: Mon Jan 9 15:28:24 2017 -0800 chromeos: fix build issues within sar.c Build issues were somehow overlooked in commit ed840023a84915ece4bc63edffef979926107d55: 1. hexstrtobin is not defined (needs the lib.h); 2. coreboot default compiler doesn't like variable initialization within for loop. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0 Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/vendorcode/google/chromeos/sar.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 2b61e22..954492b 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ #include <console/console.h> +#include <lib.h> #include <types.h> #include <string.h> #include <sar.h> @@ -31,6 +32,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) sizeof(uint8_t)) * 2 + 1; char wifi_sar_limit_str[buffer_size]; uint8_t bin_buffer[sizeof(struct wifi_sar_limits)]; + int i; /* Try to read the SAR limit entry from VPD */ if (!cros_vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, @@ -52,7 +54,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) } /* Fill the sar_limits structure with the decoded data */ - for (int i = 0; i < NUM_SAR_LIMITS; i++) + for (i = 0; i < NUM_SAR_LIMITS; i++) memcpy(sar_limits->sar_limit[i], &bin_buffer[BYTES_PER_SAR_LIMIT * i], BYTES_PER_SAR_LIMIT);

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Patch set updated for coreboot: drivers/net/rt8168: Add a macaddress cbfsfile using Kconfig
by Arthur Heymans 10 Jan '17

10 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18088 -gerrit commit 751e4b565c2c4d247700964cd923a2052b003de7 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Jan 10 15:44:47 2017 +0100 drivers/net/rt8168: Add a macaddress cbfsfile using Kconfig The default macaddress in rt8168.c can be changed with a cbfsfile called macaddress. This patch makes it possible to add such a file using Kconfig at build time. Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/net/Kconfig | 18 ++++++++++++++++++ src/drivers/net/Makefile.inc | 8 ++++++++ 2 files changed, 26 insertions(+) diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index e9c6e71..ec573f8 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -3,3 +3,21 @@ config REALTEK_8168_RESET help This forces a realtek 10ec:8168 card to reset to ensure power state is correct at boot. + +config REALTEK_8168_SET_MACADDRESS + bool "Set the Realtek rt8168 mac address" + default n + depends on REALTEK_8168_RESET + help + Select this is you want to override the default mac address of + "00:e0:4c:00:c0:b0" on a Realtek rt8168 ethernet card. + +config REALTEK_8168_MACADDRESS + string "Macaddress" + depends on REALTEK_8168_SET_MACADDRESS + default "00:e0:4c:00:c0:b0" + help + This is a string for the mac address on a Realtek rt8168 card. + It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a + hexadecimal number for it to be valid. Failing to do so will + result in the default macaddress being used. diff --git a/src/drivers/net/Makefile.inc b/src/drivers/net/Makefile.inc index e435d48..d2294ee 100644 --- a/src/drivers/net/Makefile.inc +++ b/src/drivers/net/Makefile.inc @@ -1,3 +1,11 @@ romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c ramstage-$(CONFIG_REALTEK_8168_RESET) += r8168.c + +$(obj)/macaddress: + echo " Creating a file holding the rt8168 macaddress" + printf %s $(CONFIG_REALTEK_8168_MACADDRESS) > $@ + +cbfs-files-$(CONFIG_REALTEK_8168_SET_MACADDRESS) += macaddress +macaddress-file := $(obj)/macaddress +macaddress-type := raw

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Patch set updated for coreboot: chromeos: fix build issues within sar.c
by Robbie Zhang 10 Jan '17

10 Jan '17

Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18076 -gerrit commit 23fad61dce9a708e9ed05a3e2884b026a1892e1c Author: Robbie Zhang <robbie.zhang(a)intel.com> Date: Mon Jan 9 15:28:24 2017 -0800 chromeos: fix build issues within sar.c Build issues were somehow overlooked in commit ed840023a84915ece4bc63edffef979926107d55: 1. hexstrtobin is not defined (needs the lib.h); 2. coreboot default compiler doesn't lile variable initialization within for loop. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0 Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/vendorcode/google/chromeos/sar.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 2b61e22..954492b 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ #include <console/console.h> +#include <lib.h> #include <types.h> #include <string.h> #include <sar.h> @@ -31,6 +32,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) sizeof(uint8_t)) * 2 + 1; char wifi_sar_limit_str[buffer_size]; uint8_t bin_buffer[sizeof(struct wifi_sar_limits)]; + int i; /* Try to read the SAR limit entry from VPD */ if (!cros_vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, @@ -52,7 +54,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) } /* Fill the sar_limits structure with the decoded data */ - for (int i = 0; i < NUM_SAR_LIMITS; i++) + for (i = 0; i < NUM_SAR_LIMITS; i++) memcpy(sar_limits->sar_limit[i], &bin_buffer[BYTES_PER_SAR_LIMIT * i], BYTES_PER_SAR_LIMIT);

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Patch set updated for coreboot: nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c'
by Arthur Heymans 10 Jan '17

10 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18087 -gerrit commit 5d980e1d0b76e159d54644c576d880824bc09d0d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Jan 10 14:26:23 2017 +0100 nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c' Change-Id: Ib86600b687c7002646ca82d5fa52121b6eafcd60 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/Makefile.inc | 1 + src/northbridge/intel/i945/raminit.c | 3 --- src/northbridge/intel/i945/rcven.c | 3 +++ 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 6b176c2..0e4fcfc 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c romstage-y += debug.c +romstage-y += rcven.c smm-y += udelay.c diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a4a1eaf..a361ee7 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -22,7 +22,6 @@ #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> -#include <arch/io.h> #include <halt.h> #include <lib.h> #include "raminit.h" @@ -2743,8 +2742,6 @@ static void sdram_recover_receive_enable(void) MCHBAR32(C1DRT1) = reg32; } -#include "rcven.c" - static void sdram_program_receive_enable(struct sys_info *sysinfo) { MCHBAR32(REPC) |= (1 << 0); diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index f4d9315..a6aaefa 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -13,7 +13,10 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <arch/io.h> #include "raminit.h" +#include "i945.h" /** * sample the strobes signal

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Patch merged into coreboot/master: amd/mct/ddr3: Fix incorrect DQ mask calculation
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 21b01b80d6a11a24d69a3e7ccd7c113681b6dcee Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 12:13:52 2017 -0600 amd/mct/ddr3: Fix incorrect DQ mask calculation On AMD DDR3 platforms, the upper DQMask was incorrectly calculated, leading to undefined behaviour and possible DRAM training faults. Use the correct calculation for the upper DQMask. Found-by: Coverity Scan #1347394 #1347393 Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/18068 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18068 for details. -gerrit

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New patch to review for coreboot: fsp 1.0 systems: Check for NULL when saving HobListPtr
by Martin Roth 10 Jan '17

10 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18092 -gerrit commit b53c052da631547a586daa3c83e5ef8f2e430f87 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 10 11:15:13 2017 -0700 fsp 1.0 systems: Check for NULL when saving HobListPtr Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 4 +++- src/soc/intel/fsp_baytrail/romstage/romstage.c | 5 ++++- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 8 +++----- src/southbridge/intel/fsp_i89xx/romstage.c | 4 +++- src/southbridge/intel/fsp_rangeley/romstage.c | 4 +++- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 998528d..bf5b738 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -298,7 +298,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { } /* Save the HOB pointer in CBMEM to be used in ramstage. */ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*HobListPtr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*HobListPtr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 9d204d1..7f624fc 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -252,7 +252,10 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); + *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 49d9a94..5754ec0 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -106,11 +106,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) cbmem_was_initted = !cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); - if (cbmem_hob_ptr == NULL) { - printk(BIOS_DEBUG, "Failed to save HOB pointer in CBMEM.\n"); - return; - } + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; /* Load the ramstage. */ diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index 09cce59..c2b5221 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -208,7 +208,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { } /* Save the HOB pointer in CBMEM to be used in ramstage. */ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(HobListPtr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(HobListPtr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(uint32_t*)cbmem_hob_ptr = (uint32_t)HobListPtr; post_code(0x4f); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 042aaf9..74df691 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -122,7 +122,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { cbmem_was_initted = !cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e);

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Patch merged into coreboot/master: mb/lenovo/t400: Increase MAX_CPUS to 4
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit ccc042b8216752dd6c8181ec94003921b86d9a25 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Jan 8 21:55:13 2017 +0100 mb/lenovo/t400: Increase MAX_CPUS to 4 The Lenovo T400 has a CPU socket that can fit quad cores. Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18059 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18059 for details. -gerrit

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Patch merged into coreboot/master: payloads/GRUB2: Add Kconfig options for grub.cfg
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 8fb72c9147d96c732c37bf87558963b38b78500d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Jan 8 06:43:01 2017 +0100 payloads/GRUB2: Add Kconfig options for grub.cfg Change-Id: I5480d6a5f2a6bbae4222e05bbe92eb717e1aff65 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: https://review.coreboot.org/5109 Tested-by: build bot (Jenkins) See https://review.coreboot.org/5109 for details. -gerrit

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coreboot-gerrit January 2017