coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/pyro: Add ELAN touch screen support
by Kevin Chiu 10 Jan '17

10 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18086 -gerrit commit b2177de8a9fbc6a972fbe8ae79fb5b4b60909bac Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Tue Jan 10 22:31:05 2017 +0800 google/pyro: Add ELAN touch screen support Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index bc06bbb..addfcef 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -176,6 +176,23 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "pwr_mgmt_type" = "GPIO_EXPORT" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + + chip drivers/generic/gpio_regulator + register "name" = ""vcc33"" + register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enabled_on_boot" = "1" + device generic 0 on end + end + + device i2c 10 on end + end end # - I2C 3 device pci 17.0 on chip drivers/i2c/generic

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Patch set updated for coreboot: soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree
by Kane Chen 10 Jan '17

10 Jan '17

Kane Chen (kane.chen(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18060 -gerrit commit 1151c8cab2977888104b522f666a03bc4cbb605b Author: Kane Chen <kane.chen(a)intel.com> Date: Mon Jan 9 10:45:20 2017 +0800 soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree This code allows people to override the usb2 eye pattern UPD settings for boards. BUG=chrome-os-partner:61031 BRANCH=None TEST=Usb2 function ok and make sure fsp upd is overridden Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- 3rdparty/blobs | 2 +- src/soc/intel/apollolake/chip.c | 32 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 5 +++++ src/soc/intel/apollolake/include/soc/usb.h | 33 ++++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8090bdd..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a24ca33..1de41cf 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -436,6 +436,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; + uint8_t port; /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt; @@ -491,6 +492,37 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Bios config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; + /* USB2 eye diagram settings per port */ + for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) + silconfig->PortUsb20PerPortTxPeHalf[port] = + cfg->usb2eye[port].Usb20PerPortTxPeHalf; + + if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0) + silconfig->PortUsb20PerPortPeTxiSet[port] = + cfg->usb2eye[port].Usb20PerPortPeTxiSet; + + if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0) + silconfig->PortUsb20PerPortTxiSet[port] = + cfg->usb2eye[port].Usb20PerPortTxiSet; + + if (cfg->usb2eye[port].Usb20HsSkewSel != 0) + silconfig->PortUsb20HsSkewSel[port] = + cfg->usb2eye[port].Usb20HsSkewSel; + + if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0) + silconfig->PortUsb20IUsbTxEmphasisEn[port] = + cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; + + if (cfg->usb2eye[port].Usb20PerPortRXISet != 0) + silconfig->PortUsb20PerPortRXISet[port] = + cfg->usb2eye[port].Usb20PerPortRXISet; + + if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0) + silconfig->PortUsb20HsNpreDrvSel[port] = + cfg->usb2eye[port].Usb20HsNpreDrvSel; + } + } struct chip_operations soc_intel_apollolake_ops = { diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 5f8fed9..d60ffbf 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -24,6 +24,7 @@ #include <soc/intel/common/lpss_i2c.h> #include <device/i2c.h> #include <soc/pm.h> +#include <soc/usb.h> #define CLKREQ_DISABLED 0xf #define APOLLOLAKE_I2C_DEV_MAX 8 @@ -115,6 +116,10 @@ struct soc_intel_apollolake_config { /* GPIO pin for PERST_0 */ uint16_t prt0_gpio; + + /* USB2 eye diagram settings per port */ + struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; + }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h new file mode 100644 index 0000000..7220023 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * (Written by Kane Chen <Kane.Chen(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_USB_H_ +#define _SOC_APOLLOLAKE_USB_H_ + +#define APOLLOLAKE_USB2_PORT_MAX 8 + +struct usb2_eye_per_port { + uint8_t Usb20PerPortTxPeHalf; + uint8_t Usb20PerPortPeTxiSet; + uint8_t Usb20PerPortTxiSet; + uint8_t Usb20HsSkewSel; + uint8_t Usb20IUsbTxEmphasisEn; + uint8_t Usb20PerPortRXISet; + uint8_t Usb20HsNpreDrvSel; +}; + +#endif /* _SOC_APOLLOLAKE_USB_H_ */

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New patch to review for coreboot: google/chromeos: disable platform hierarchy on resume for TPM2
by Aaron Durbin 10 Jan '17

10 Jan '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18096 -gerrit commit a78ef1599cf9ed5d351bd071da283ca8c479712b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 10 17:44:42 2017 -0600 google/chromeos: disable platform hierarchy on resume for TPM2 On Chrome OS devices that use TPM2 parts the platform hierarchy is disabled by the boot loader. In order to ensure consistent state in resume the platform hierarchy in the TPM2 needs to be disabled as well. Therefore, on systems that resume using the firmware the platform hierarchy is disabled when utilizing TPM2 devices. BUG=chrome-os-partner:61097 BRANCH=reef TEST=Suspend and resume. Confirmed 'top trunksd; tpmc getvf; start trunksd' shows that phEnable is 0. Change-Id: I060252f338c8fd68389273224ee58caa99881de8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/tpm_lite/tlcl.h | 5 ++++ src/lib/Makefile.inc | 2 ++ src/lib/tpm2_marshaling.c | 23 +++++++++++++++ src/lib/tpm2_tlcl.c | 16 ++++++++++ src/lib/tpm2_tlcl_structures.h | 26 ++++++++++------- src/vendorcode/google/chromeos/Kconfig | 14 +++++++++ src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/tpm2.c | 45 +++++++++++++++++++++++++++++ 8 files changed, 122 insertions(+), 10 deletions(-) diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h index 8ea5564..95bae77 100644 --- a/src/include/tpm_lite/tlcl.h +++ b/src/include/tpm_lite/tlcl.h @@ -151,4 +151,9 @@ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, */ uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags); +/** + * Disable platform hierarchy. Specific to TPM2. The TPM error code is returned. + */ +uint32_t tlcl_disable_platform_hierarchy(void); + #endif /* TPM_LITE_TLCL_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2d5aa57..9a9ddc8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -144,6 +144,8 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c +ramstage-$(CONFIG_TPM2) += tpm2_marshaling.c +ramstage-$(CONFIG_TPM2) += tpm2_tlcl.c romstage-y += cbmem_common.c romstage-y += imd_cbmem.c diff --git a/src/lib/tpm2_marshaling.c b/src/lib/tpm2_marshaling.c index 1edc690..38c8d2f 100644 --- a/src/lib/tpm2_marshaling.c +++ b/src/lib/tpm2_marshaling.c @@ -373,6 +373,23 @@ static void marshal_selftest(void **buffer, marshal_u8(buffer, command_body->yes_no, buffer_space); } +static void marshal_hierarchy_control(void **buffer, + struct tpm2_hierarchy_control_cmd *command_body, + size_t *buffer_space) +{ + struct tpm2_session_header session_header; + + car_set_var(tpm_tag, TPM_ST_SESSIONS); + + marshal_TPM_HANDLE(buffer, TPM_RH_PLATFORM, buffer_space); + memset(&session_header, 0, sizeof(session_header)); + session_header.session_handle = TPM_RS_PW; + marshal_session_header(buffer, &session_header, buffer_space); + + marshal_TPM_HANDLE(buffer, command_body->enable, buffer_space); + marshal_u8(buffer, command_body->state, buffer_space); +} + int tpm_marshal_command(TPM_CC command, void *tpm_command_body, void *buffer, size_t buffer_size) { @@ -414,6 +431,11 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, marshal_selftest(&cmd_body, tpm_command_body, &body_size); break; + case TPM2_Hierarchy_Control: + marshal_hierarchy_control(&cmd_body, tpm_command_body, + &body_size); + break; + case TPM2_Clear: marshal_clear(&cmd_body, &body_size); break; @@ -583,6 +605,7 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, &tpm2_resp->nvr); break; + case TPM2_Hierarchy_Control: case TPM2_Clear: case TPM2_NV_DefineSpace: case TPM2_NV_Write: diff --git a/src/lib/tpm2_tlcl.c b/src/lib/tpm2_tlcl.c index 6f5243e..6c0cd6e 100644 --- a/src/lib/tpm2_tlcl.c +++ b/src/lib/tpm2_tlcl.c @@ -369,3 +369,19 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size) return TPM_E_INTERNAL_INCONSISTENCY; } } + +uint32_t tlcl_disable_platform_hierarchy(void) +{ + struct tpm2_response *response; + struct tpm2_hierarchy_control_cmd hc = { + .enable = TPM_RH_PLATFORM, + .state = 0, + }; + + response = tpm_process_command(TPM2_Hierarchy_Control, &hc); + + if (!response || response->hdr.tpm_code) + return TPM_E_INTERNAL_INCONSISTENCY; + + return TPM_SUCCESS; +} diff --git a/src/lib/tpm2_tlcl_structures.h b/src/lib/tpm2_tlcl_structures.h index 36a3e8b..c5c6d87 100644 --- a/src/lib/tpm2_tlcl_structures.h +++ b/src/lib/tpm2_tlcl_structures.h @@ -28,7 +28,7 @@ typedef uint8_t TPMI_YES_NO; typedef TPM_ALG_ID TPMI_ALG_HASH; typedef TPM_HANDLE TPMI_DH_PCR; typedef TPM_HANDLE TPMI_RH_NV_INDEX; -typedef TPM_HANDLE TPMI_RH_PROVISION; +typedef TPM_HANDLE TPMI_RH_ENABLES; typedef TPM_HANDLE TPMI_SH_AUTH_SESSION; typedef TPM_HANDLE TPM_RH; @@ -59,15 +59,16 @@ struct tpm_header { } __attribute__((packed)); /* TPM command codes. */ -#define TPM2_Clear ((TPM_CC)0x00000126) -#define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) -#define TPM2_NV_Write ((TPM_CC)0x00000137) -#define TPM2_NV_WriteLock ((TPM_CC)0x00000138) -#define TPM2_SelfTest ((TPM_CC)0x00000143) -#define TPM2_Startup ((TPM_CC)0x00000144) -#define TPM2_NV_Read ((TPM_CC)0x0000014E) -#define TPM2_GetCapability ((TPM_CC)0x0000017A) -#define TPM2_PCR_Extend ((TPM_CC)0x00000182) +#define TPM2_Hierarchy_Control ((TPM_CC)0x00000121) +#define TPM2_Clear ((TPM_CC)0x00000126) +#define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) +#define TPM2_NV_Write ((TPM_CC)0x00000137) +#define TPM2_NV_WriteLock ((TPM_CC)0x00000138) +#define TPM2_SelfTest ((TPM_CC)0x00000143) +#define TPM2_Startup ((TPM_CC)0x00000144) +#define TPM2_NV_Read ((TPM_CC)0x0000014E) +#define TPM2_GetCapability ((TPM_CC)0x0000017A) +#define TPM2_PCR_Extend ((TPM_CC)0x00000182) /* Startup values. */ #define TPM_SU_CLEAR 0 @@ -334,4 +335,9 @@ struct tpm2_pcr_extend_cmd { TPML_DIGEST_VALUES digests; }; +struct tpm2_hierarchy_control_cmd { + TPMI_RH_ENABLES enable; + TPMI_YES_NO state; +}; + #endif // __SRC_LIB_TPM2_TLCL_STRUCTURES_H diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 238b4e5..ef79501 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -127,6 +127,20 @@ config CHROMEOS_FWID_VERSION This is the second part of the FWID written to various regions of a Chrome OS firmware image to identify its version. +config CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME + bool + default y + depends on TPM2 && RESUME_PATH_SAME_AS_BOOT + help + Disable the platform heirarchy on resume path if the firmware + is involved in resume. The hierarchy is disabled prior to jumping + to the OS. Note that this option is sepcific to TPM2 boards. + This option is auto selected if CHROMEOS because it matches with + vboot_reference model which disbales the platform hierarchy in + the boot loader. However, those operations need to be symmetric + on normal boot as well as resume and coreboot is only involved + in the resume piece w.r.t. the platform hierarchy. + menu "GBB configuration" config GBB_HWID diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 878b068..f0762bc 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -24,6 +24,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c +ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c ifeq ($(CONFIG_ARCH_MIPS),) diff --git a/src/vendorcode/google/chromeos/tpm2.c b/src/vendorcode/google/chromeos/tpm2.c new file mode 100644 index 0000000..fd1dac9 --- /dev/null +++ b/src/vendorcode/google/chromeos/tpm2.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <tpm_lite/tlcl.h> +#include <vb2_api.h> + +static void disable_platform_hierarchy(void *unused) +{ + int ret; + + if (!IS_ENABLED(CONFIG_TPM2)) + return; + + if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) + return; + + ret = tlcl_lib_init(); + + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: %x\n", ret); + return; + } + + ret = tlcl_disable_platform_hierarchy(); + if (ret != TPM_SUCCESS) + printk(BIOS_ERR, "Platform hierarchy disablement failed: %x\n", + ret); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, disable_platform_hierarchy, + NULL);

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New patch to review for coreboot: sb/intel/fsp_rangeley: Fix NULL check in gpio.c
by Martin Roth 10 Jan '17

10 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18095 -gerrit commit 6518dd7fc8b2f9ea1a089d60321212ccfadb7e42 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 10 16:40:45 2017 -0700 sb/intel/fsp_rangeley: Fix NULL check in gpio.c This should always have been an and, not an or. The only way this would happen is if no GPIOs were getting configured, so we shouldn't ever have a NULL here, but if we did, GPIOs would be randomly configured, which would have 'interesting' results. Found-by: Coverity Scan #1229633 & 1229632 Change-Id: If123372658383f84279738e1186425beba3208ca Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/southbridge/intel/fsp_rangeley/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index 2a2061c..0a287c4 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -62,7 +62,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* GPIO PAD Settings */ /* CFIO Core Well Set 1 */ - if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) { + if ((gpio->core.cfio_init != NULL) && (gpio->core.cfio_entrynum != 0)) { write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) @@ -76,7 +76,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) } /* CFIO SUS Well Set 1 */ - if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) { + if ((gpio->sus.cfio_init != NULL) && (gpio->sus.cfio_entrynum != 0)) { write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))

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Patch set updated for coreboot: soc/intel/skylake: Rename car_stage.S for fsp2_0
by Boon Tiong Teo 10 Jan '17

10 Jan '17

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18083 -gerrit commit a28e1226ec48afb10c23e06ff7534bc1297570b0 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Tue Jan 10 21:10:40 2017 +0800 soc/intel/skylake: Rename car_stage.S for fsp2_0 Cosmetic changes to rename car_stage.S to car_stage_fsp20.S, so that it is associate with fsp driver version that being used. Tested on Kabylake Rvp11. Change-Id: I869df6eb746e3982e5912c272255eab6cb008838 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/soc/intel/skylake/romstage/Makefile.inc | 2 +- src/soc/intel/skylake/romstage/car_stage.S | 131 ----------------------- src/soc/intel/skylake/romstage/car_stage_fsp20.S | 131 +++++++++++++++++++++++ 3 files changed, 132 insertions(+), 132 deletions(-) diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 877712f..c19301f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,6 +1,6 @@ verstage-y += power_state.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S romstage-y += pmc.c romstage-y += power_state.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S deleted file mode 100644 index c6401fa..0000000 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <rules.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -.section ".text" -.global car_stage_entry - -car_stage_entry: - - /* Enter the C code */ - call car_stage_c_entry - -/* - * Car teardown - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - - #include <soc/car_teardown.S> - - /* Display the MTRRs */ - call soc_display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - call copy_and_run diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S new file mode 100644 index 0000000..c6401fa --- /dev/null +++ b/src/soc/intel/skylake/romstage/car_stage_fsp20.S @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <rules.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.section ".text" +.global car_stage_entry + +car_stage_entry: + + /* Enter the C code */ + call car_stage_c_entry + +/* + * Car teardown + */ + /* + * eax: New stack address + */ + + /* Switch to the stack in RAM */ + movl %eax, %esp + + #include <soc/car_teardown.S> + + /* Display the MTRRs */ + call soc_display_mtrrs + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Clear all of the variable MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx + clr %eax + clr %edx + +1: + testl %ebx, %ebx + jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ + wrmsr + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ + wrmsr + inc %ecx + + dec %ebx + jmp 2b +2: + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + call copy_and_run

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Patch set updated for coreboot: amd/mct/ddr3: Fix unintended sign extension warning
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18077 -gerrit commit cd28926900e56a6e830a68e9eaa8ccb632b8a6ae Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:40:21 2017 -0600 amd/mct/ddr3: Fix unintended sign extension warning An unintended sign extension warning was thrown by Coverity. Explicitly state the length of the constant multiplier. Found-by: Coverity Scan #1347342 Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f726345..b64ad54 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2474,10 +2474,10 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, if (interleaved) /* Move upper limit down by 16M * the number of nodes */ - max_range_limit -= (0x1000000 * num_nodes); + max_range_limit -= (0x1000000ULL * num_nodes); else /* Move upper limit down by 16M */ - max_range_limit -= 0x1000000; + max_range_limit -= 0x1000000ULL; printk(BIOS_INFO, "%s:\tnew max_range_limit: %16llx\n", __func__, max_range_limit);

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Patch set updated for coreboot: amd/mct/ddr2: Remove orphaned Tab_TrefT_k variable
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18094 -gerrit commit 683c22a4aab6144f30c494e673f02eaf4508b8f7 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue Jan 10 16:24:56 2017 -0600 amd/mct/ddr2: Remove orphaned Tab_TrefT_k variable The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 909037f..8bee434 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -159,7 +159,6 @@ static const u8 Table_T_k[] = {0x00,0x50,0x3D,0x30,0x25, 0x18 }; static const u8 Table_CL2_j[] = {0x04,0x08,0x10,0x20,0x40, 0x80 }; static const u8 Tab_defTrc_k[] = {0x0,0x41,0x3C,0x3C,0x3A, 0x3A }; static const u16 Tab_40T_k[] = {00,200,150,120,100,75 }; -static const u8 Tab_TrefT_k[] = {00,0,1,1,2,2,3,4,5,6,0,0}; static const u8 Tab_BankAddr[] = {0x0,0x08,0x09,0x10,0x0C,0x0D,0x11,0x0E,0x15,0x16,0x0F,0x17}; static const u8 Tab_tCL_j[] = {0,2,3,4,5}; static const u8 Tab_1KTfawT_k[] = {00,8,10,13,14,20};

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Patch set updated for coreboot: amd/mct: Add default values to highest_rank_count for DDR2
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18078 -gerrit commit db2342033a0921c18cc93adb6236599325928390 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:47:37 2017 -0600 amd/mct: Add default values to highest_rank_count for DDR2 The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 06e4a06..0b08c20 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -344,6 +344,7 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) uint8_t ch1_voltage = 0; uint8_t ch2_voltage = 0; uint8_t highest_rank_count[2]; + uint8_t dimm; int i; for (i = 0; i < 15; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) @@ -363,14 +364,13 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) } #if IS_ENABLED(CONFIG_DIMM_DDR3) - uint8_t dimm; - for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; if (pDCTstat->DIMMValid & (1 << (i + 1))) ch2_voltage |= pDCTstat->DimmConfiguredVoltage[i + 1]; } +#endif for (i = 0; i < 2; i++) { highest_rank_count[i] = 0x0; @@ -379,7 +379,6 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) highest_rank_count[i] = pDCTstat->DimmRanks[dimm]; } } -#endif /* Set limits if needed */ pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq);

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Patch set updated for coreboot: amd/mct/ddr3: Avoid using uninitialized register address in ECC setup
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18079 -gerrit commit db086cd3c65ce4630cbbb91e9168dd32d43598fd Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:54:35 2017 -0600 amd/mct/ddr3: Avoid using uninitialized register address in ECC setup Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as a register address under certain conditions. Refactor mct_EnableDimmEccEn_D to use the explicit address of the register in all cases. Found-by: Coverity Scan #1347337 Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 9783f38..10d4206 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2242,23 +2242,20 @@ void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC) { u32 val; - u32 reg; u32 dev; /* Enable ECC correction if it was previously disabled */ - dev = pDCTstat->dev_dct; if ((_DisableDramECC & 0x01) == 0x01) { - reg = 0x90; - val = Get_NB32_DCT(dev, 0, reg); + val = Get_NB32_DCT(dev, 0, 0x90); val |= (1<<DimmEcEn); - Set_NB32_DCT(dev, 0, reg, val); + Set_NB32_DCT(dev, 0, 0x90, val); } if ((_DisableDramECC & 0x02) == 0x02) { - val = Get_NB32_DCT(dev, 1, reg); + val = Get_NB32_DCT(dev, 1, 0x90); val |= (1<<DimmEcEn); - Set_NB32_DCT(dev, 1, reg, val); + Set_NB32_DCT(dev, 1, 0x90, val); } }

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Patch merged into coreboot/master: amd/mct/ddr3: Free malloced resources in failure branches
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit a20d0e0f79cdff543a584ed6187ba6e86e76ddac Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:54:24 2017 -0600 amd/mct/ddr3: Free malloced resources in failure branches Malloced resources were not freed in failure branches during S3 parameter save. Clean up Coverity warnings by freeing resources in failure branches. Found-by: Coverity Scan #1347344 Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/18074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18074 for details. -gerrit

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coreboot-gerrit January 2017