coreboot-gerrit January 2017

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Patch merged into coreboot/master: amd/mct/ddr3: Rework memory speed to clock value conversion logic
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 6f9468f019239af70c20de9fca411fc76a00db1b Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:27:09 2017 -0600 amd/mct/ddr3: Rework memory speed to clock value conversion logic The existing DRAM clock speed to configuration value logic contained an error resulting in a theoretical out of bounds read. While this would not be hit on real hardware, it was prudent to clean up the logic to avoid the associated Coverity warning. Found-by: Coverity Scan #1347353 Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/18073 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18073 for details. -gerrit

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Patch merged into coreboot/master: amd/mct/ddr3: Correctly program maximum read latency
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 8fa624784e3d78e67cf7b4e0e72cb2208c399f0f Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:19:37 2017 -0600 amd/mct/ddr3: Correctly program maximum read latency The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. Found-by: Coverity Scan #1347354 Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/18072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See https://review.coreboot.org/18072 for details. -gerrit

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Patch set updated for coreboot: apollolake: Update UPD header files for FSP 1.3.0
by Brandon Breitenstein 10 Jan '17

10 Jan '17

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18046 -gerrit commit 99a9a982eba27f65d9dcdf8f9e1c6349e4ab15a6 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Thu Jan 5 12:47:27 2017 -0800 apollolake: Update UPD header files for FSP 1.3.0 These updated header files contain USB tuning parameters as well as some general cleanup of unused parameters in the UPD Headers. This patch along with the upcoming FSP 1.3.0 release will allow for USB tuning on apollolake platforms. CQ-DEPEND=CL:*315403 BUG=chrome-os-partner:61031 Change-Id: Id7cce1ea83057630d508523ada18c5425804535e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- .../intel/fsp/fsp2_0/apollolake/FspmUpd.h | 36 +------------ .../intel/fsp/fsp2_0/apollolake/FspsUpd.h | 59 ++++++++++++---------- 2 files changed, 33 insertions(+), 62 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h index d0620f5..3cfbd71 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h @@ -820,32 +820,6 @@ typedef struct { UINT8 ReservedFspmUpd[12]; } FSP_M_CONFIG; -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0160 -**/ - UINT32 Signature; - -/** Offset 0x0164 -**/ - UINT8 ReservedFspmTestUpd[12]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0170 -**/ - UINT32 Signature; - -/** Offset 0x0174 -**/ - UINT8 ReservedFspmRestrictedUpd[124]; -} FSP_M_RESTRICTED_CONFIG; - /** Fsp M UPD Configuration **/ typedef struct { @@ -864,15 +838,7 @@ typedef struct { /** Offset 0x0160 **/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0170 -**/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x01F0 -**/ - UINT8 UnusedUpdSpace2[14]; + UINT8 UnusedUpdSpace2[158]; /** Offset 0x01FE **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h index 8a4fe1a..82a224d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -1521,34 +1521,47 @@ typedef struct { /** Offset 0x0334 **/ - UINT8 ReservedFspsUpd[12]; -} FSP_S_CONFIG; + UINT8 UnusedUpdSpace7[4]; -/** Fsp S Test Configuration +/** Offset 0x0338 - PerPort Half Bit Pre-emphasis + PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14] **/ -typedef struct { + UINT8 PortUsb20PerPortTxPeHalf[8]; -/** Offset 0x0340 +/** Offset 0x0340 - PerPort HS Pre-emphasis Bias + PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11] **/ - UINT32 Signature; + UINT8 PortUsb20PerPortPeTxiSet[8]; -/** Offset 0x0344 +/** Offset 0x0348 - PerPort HS Transmitter Bias + PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8] **/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; + UINT8 PortUsb20PerPortTxiSet[8]; -/** Fsp S Restricted Configuration +/** Offset 0x0350 - Select the skew direction for HS transition + Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25] **/ -typedef struct { + UINT8 PortUsb20HsSkewSel[8]; + +/** Offset 0x0358 - Per Port HS Transmitter Emphasis + Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23] +**/ + UINT8 PortUsb20IUsbTxEmphasisEn[8]; + +/** Offset 0x0360 - PerPort HS Receiver Bias + PerPort HS Receiver Bias. Value of register USB2_PER_PORT_2_PPX [19:17] +**/ + UINT8 PortUsb20PerPortRXISet[8]; -/** Offset 0x0350 +/** Offset 0x0368 - Delay/skew's strength control for HS driver + Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0] **/ - UINT32 Signature; + UINT8 PortUsb20HsNpreDrvSel[8]; -/** Offset 0x0354 +/** Offset 0x0370 **/ - UINT8 ReservedFspsRestrictedUpd[12]; -} FSP_S_RESTRICTED_CONFIG; + UINT8 ReservedFspsUpd[16]; +} FSP_S_CONFIG; /** Fsp S UPD Configuration **/ @@ -1562,19 +1575,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0340 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0350 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x0360 +/** Offset 0x0380 **/ - UINT8 UnusedUpdSpace7[14]; + UINT8 UnusedUpdSpace8[46]; -/** Offset 0x036E +/** Offset 0x03AE **/ UINT16 UpdTerminator; } FSPS_UPD;

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Patch set updated for coreboot: mainboard/asus: Add F2A85-M PRO variant to F2A85-M.
by Denis 'GNUtoo' Carikli 10 Jan '17

10 Jan '17

Denis 'GNUtoo' Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16931 -gerrit commit b5b7c7ecf4e0e8dc9374f40056a62ff4d3943b15 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Jul 26 19:57:51 2015 +0200 mainboard/asus: Add F2A85-M PRO variant to F2A85-M. Status: - The primary PCIe 16x slot works: It was tested with a GPU compatible with nouveau - USB and audio are not very reliable - The ethernet card is not seen with lspci - The secondary pcie16x slot isn't working: When plugging a GPU inside, it's not seen with lspci - SATA works: The board fully boots GNU/Linux - Serial doesn't work - Populating the RAM slots might have to follow the recommended memory configuration that is described in the mainboard manual in order to be able to boot. Note that when running the shutdown command, the default boot firmware will rewrite part of the boot flash before powering off the machine. Flashing coreboot internally from the default boot fimrware can still work, if the power plug is removed after running flashrom. Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/f2a85-m/Kconfig | 15 +- src/mainboard/asus/f2a85-m/Kconfig.name | 3 + src/mainboard/asus/f2a85-m/OemCustomize.c | 20 +++ src/mainboard/asus/f2a85-m/acpi/routing.asl | 7 + src/mainboard/asus/f2a85-m/devicetree.cb | 133 ---------------- src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb | 133 ++++++++++++++++ .../asus/f2a85-m/devicetree_f2a85-m_pro.cb | 172 +++++++++++++++++++++ src/mainboard/asus/f2a85-m/romstage.c | 14 ++ 8 files changed, 360 insertions(+), 137 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 04eb936..03c9c28 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -14,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_ASUS_F2A85_M +if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -25,7 +25,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES - select SUPERIO_ITE_IT8728F + select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M + select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO select BOARD_ROMSIZE_KB_8192 select GFXUMA select HUDSON_DISABLE_IMC @@ -60,7 +61,8 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "F2A85-M" + default "F2A85-M" if BOARD_ASUS_F2A85_M + default "F2A85-M_PRO" if BOARD_ASUS_F2A85_M_PRO config HW_MEM_HOLE_SIZEK hex @@ -102,4 +104,9 @@ config POST_IO bool default n -endif # BOARD_ASUS_F2A85_M +config DEVICETREE + string + default "devicetree_f2a85-m_pro.cb" if BOARD_ASUS_F2A85_M_PRO + default "devicetree_f2a85-m.cb" if BOARD_ASUS_F2A85_M + +endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name index af6f628..a8aa273 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig.name +++ b/src/mainboard/asus/f2a85-m/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASUS_F2A85_M bool "F2A85-M" + +config BOARD_ASUS_F2A85_M_PRO + bool "F2A85-M PRO" diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 6348d5a..d545207 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -225,6 +225,26 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ PSO_END }; +#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO) +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), +/* + TODO: is this OK for DDR3 socket FM2? + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + */ + PSO_END +}; #endif /* CONFIG_BOARD_ASUS_F2A85_M */ const struct OEM_HOOK OemCustomize = { diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 0af6b42..cc36dcd 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -46,6 +46,13 @@ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ +#if CONFIG_BOARD_ASUS_F2A85_M_PRO + Package(){0x000FFFFF, 0, INTA, 0 }, + Package(){0x000FFFFF, 1, INTB, 0 }, + Package(){0x000FFFFF, 2, INTC, 0 }, + Package(){0x000FFFFF, 3, INTD, 0 }, +#endif /* CONFIG_BOARD_ASUS_F2A85_M_PRO */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb deleted file mode 100644 index d942445..0000000 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ /dev/null @@ -1,133 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 blue - device pci 3.0 off end # unused? - device pci 4.0 on end # PCIE 4x black - device pci 5.0 off end # unused? - device pci 6.0 off end # unused? - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 on end # PCIe 0 - onboard PCIe 1x - device pci 15.1 on end # PCIe 1 onboard gigabit - device pci 15.2 off end # unused - device pci 15.3 off end # unused - - end #chip southbridge/amd/agesa/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb new file mode 100644 index 0000000..d942445 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -0,0 +1,133 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register hwm_ctl_register = "0xc0" + register hwm_main_ctl_register = "0x33" + register hwm_adc_temp_chan_en_reg = "0x38" + register hwm_fan1_ctl_pwm = "0x00" + register hwm_fan2_ctl_pwm = "0x00" + register hwm_fan3_ctl_pwm = "0x00" + + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused + + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb new file mode 100644 index 0000000..238ab51 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -0,0 +1,172 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 2.0 on end # Internal Graphics P2P bridge 0x99XX + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 52 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 2 + device i2c 51 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 3 + device i2c 53 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # unused + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x780e + chip superio/nuvoton/nct5572d + device pnp 2e.0 off end # FDC + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2/IR + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 + io 0xe0 = 0x7f + io 0xe1 = 0x10 + io 0xe2 = 0x00 + io 0xe3 = 0x00 + io 0xe4 = 0xff + io 0xe5 = 0xff + io 0xe6 = 0xff + io 0xe7 = 0xff + io 0xec = 0x00 + io 0xed = 0xff + io 0xf4 = 0xff + io 0xf5 = 0xff + io 0xf6 = 0x00 + io 0xf7 = 0x00 + io 0xf8 = 0x00 + end + device pnp 2e.8 on # WDT1, GPIO0, GPIO1 + io 0x30 = 0x00 + io 0x60 = 0x00 + io 0x61 = 0x00 + io 0xe0 = 0xff + io 0xe1 = 0xff + io 0xe2 = 0xff + io 0xe3 = 0xff + io 0xe4 = 0xff + io 0xf0 = 0xff + io 0xf1 = 0x28 + io 0xf2 = 0x00 + io 0xf3 = 0x00 + io 0xf4 = 0x08 + io 0xf5 = 0xff + io 0xf6 = 0x00 + io 0xf7 = 0xff + end + device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 + io 0x30 = 0xfe + io 0xe0 = 0xff + io 0xe1 = 0x90 + io 0xe2 = 0x00 + io 0xe3 = 0x00 + io 0xe4 = 0x7f + io 0xe5 = 0x76 + io 0xe6 = 0x00 + io 0xe7 = 0x00 + io 0xe8 = 0x00 + io 0xe9 = 0x00 + io 0xea = 0x00 + io 0xeb = 0x00 + io 0xee = 0x00 + io 0xf0 = 0xff + io 0xf1 = 0x7b + io 0xf2 = 0x00 + io 0xf4 = 0xff + io 0xf5 = 0xef + io 0xf6 = 0x00 + io 0xf7 = 0x00 + io 0xfe = 0x00 + end + device pnp 2e.a on # ACPI + io 0xe6 = 0x4c + io 0xe7 = 0x11 + io 0xf2 = 0x5d + end + device pnp 2e.b on # Hardware Monitor, Front Panel LED + io 0x30 = 0x01 + io 0x60 = 0x02 + io 0x61 = 0x90 + io 0xe2 = 0x7f + io 0xe4 = 0xf1 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off # GPIO Push-pull/Open-drain selection + io 0xe6 = 7f + end + device pnp 2e.14 off # PORT80 UART + io 0xe0 = 0x00 + end + device pnp 2e.16 off end # Deep Sleep + end + end #device pci 14.3 # LPC + + device pci 14.4 on end # PCI bridge + device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806]) + device pci 15.0 on end # PCI bridge + device pci 15.1 on end # PCI bridge + device pci 15.2 on end # PCI bridge # Only present with the original boot firmware + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index b5aff9f..e02638e 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -33,16 +33,26 @@ #include <southbridge/amd/agesa/hudson/smbus.h> #include <stdint.h> #include <string.h> +#if CONFIG_BOARD_ASUS_F2A85_M #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> +#elif CONFIG_BOARD_ASUS_F2A85_M_PRO +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> +#endif /* CONFIG_BOARD_ASUS_F2A85_M */ + #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) +#if CONFIG_BOARD_ASUS_F2A85_M #define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#elif CONFIG_BOARD_ASUS_F2A85_M_PRO +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#endif /* CONFIG_BOARD_ASUS_F2A85_M */ static void sbxxx_enable_48mhzout(void) { @@ -95,9 +105,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* enable SIO clock */ sbxxx_enable_48mhzout(); +#if CONFIG_BOARD_ASUS_F2A85_M ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_3vsbsw(GPIO_DEV); +#elif CONFIG_BOARD_ASUS_F2A85_M_PRO + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +#endif console_init(); /* turn on secondary smbus at b20 */

1 0

New patch to review for coreboot: amd/mct/ddr2: Remove orphaned Tab_TrefT_k variable
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18094 -gerrit commit 3b2e9aec50225e4258ce30894f4e0557c6247758 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue Jan 10 16:24:56 2017 -0600 amd/mct/ddr2: Remove orphaned Tab_TrefT_k variable The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 909037f..8bee434 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -159,7 +159,6 @@ static const u8 Table_T_k[] = {0x00,0x50,0x3D,0x30,0x25, 0x18 }; static const u8 Table_CL2_j[] = {0x04,0x08,0x10,0x20,0x40, 0x80 }; static const u8 Tab_defTrc_k[] = {0x0,0x41,0x3C,0x3C,0x3A, 0x3A }; static const u16 Tab_40T_k[] = {00,200,150,120,100,75 }; -static const u8 Tab_TrefT_k[] = {00,0,1,1,2,2,3,4,5,6,0,0}; static const u8 Tab_BankAddr[] = {0x0,0x08,0x09,0x10,0x0C,0x0D,0x11,0x0E,0x15,0x16,0x0F,0x17}; static const u8 Tab_tCL_j[] = {0,2,3,4,5}; static const u8 Tab_1KTfawT_k[] = {00,8,10,13,14,20};

1 0

Patch set updated for coreboot: fsp 1.0 systems: Check for NULL when saving HobListPtr
by Martin Roth 10 Jan '17

10 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18092 -gerrit commit e0c998886b725c913aa5c9ce5b79ffe3009e3e51 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 10 11:15:13 2017 -0700 fsp 1.0 systems: Check for NULL when saving HobListPtr Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 4 +++- src/soc/intel/fsp_baytrail/romstage/romstage.c | 4 +++- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 8 +++----- src/southbridge/intel/fsp_i89xx/romstage.c | 4 +++- src/southbridge/intel/fsp_rangeley/romstage.c | 4 +++- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 998528d..bf5b738 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -298,7 +298,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { } /* Save the HOB pointer in CBMEM to be used in ramstage. */ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*HobListPtr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*HobListPtr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 9d204d1..f8d985e 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -252,7 +252,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 49d9a94..5754ec0 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -106,11 +106,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) cbmem_was_initted = !cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); - if (cbmem_hob_ptr == NULL) { - printk(BIOS_DEBUG, "Failed to save HOB pointer in CBMEM.\n"); - return; - } + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; /* Load the ramstage. */ diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index 09cce59..c2b5221 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -208,7 +208,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { } /* Save the HOB pointer in CBMEM to be used in ramstage. */ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(HobListPtr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(HobListPtr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(uint32_t*)cbmem_hob_ptr = (uint32_t)HobListPtr; post_code(0x4f); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 042aaf9..74df691 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -122,7 +122,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { cbmem_was_initted = !cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); + if (cbmem_hob_ptr == NULL) + die("Could not allocate cbmem for HOB pointer"); *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e);

1 0

Patch merged into coreboot/master: SPD_CACHE: Drop debug statement
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit bc44178f0240fe2e6165f300674e3e74a021a0b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 27 04:58:02 2016 +0200 SPD_CACHE: Drop debug statement Output from CBFS functions is enough. Change-Id: I94d4a20a24f88eeacbe4aeb2e03a15974d18b16c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17923 for details. -gerrit

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Patch set updated for coreboot: amd/mct: Add default values to highest_rank_count for DDR2
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18078 -gerrit commit f8d111d2e889d545b09a2ef1179404bec7a33638 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:47:37 2017 -0600 amd/mct: Add default values to highest_rank_count for DDR2 The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 06e4a06..0b08c20 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -344,6 +344,7 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) uint8_t ch1_voltage = 0; uint8_t ch2_voltage = 0; uint8_t highest_rank_count[2]; + uint8_t dimm; int i; for (i = 0; i < 15; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) @@ -363,14 +364,13 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) } #if IS_ENABLED(CONFIG_DIMM_DDR3) - uint8_t dimm; - for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; if (pDCTstat->DIMMValid & (1 << (i + 1))) ch2_voltage |= pDCTstat->DimmConfiguredVoltage[i + 1]; } +#endif for (i = 0; i < 2; i++) { highest_rank_count[i] = 0x0; @@ -379,7 +379,6 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) highest_rank_count[i] = pDCTstat->DimmRanks[dimm]; } } -#endif /* Set limits if needed */ pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq);

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Patch set updated for coreboot: amd/mct/ddr3: Avoid using uninitialized register address in ECC setup
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18079 -gerrit commit 3a56c2bdbe1e94fff7355f5cf23624858d3bd1d7 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:54:35 2017 -0600 amd/mct/ddr3: Avoid using uninitialized register address in ECC setup Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as a register address under certain conditions. Refactor mct_EnableDimmEccEn_D to use the explicit address of the register in all cases. Found-by: Coverity Scan #1347337 Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 9783f38..10d4206 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2242,23 +2242,20 @@ void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC) { u32 val; - u32 reg; u32 dev; /* Enable ECC correction if it was previously disabled */ - dev = pDCTstat->dev_dct; if ((_DisableDramECC & 0x01) == 0x01) { - reg = 0x90; - val = Get_NB32_DCT(dev, 0, reg); + val = Get_NB32_DCT(dev, 0, 0x90); val |= (1<<DimmEcEn); - Set_NB32_DCT(dev, 0, reg, val); + Set_NB32_DCT(dev, 0, 0x90, val); } if ((_DisableDramECC & 0x02) == 0x02) { - val = Get_NB32_DCT(dev, 1, reg); + val = Get_NB32_DCT(dev, 1, 0x90); val |= (1<<DimmEcEn); - Set_NB32_DCT(dev, 1, reg, val); + Set_NB32_DCT(dev, 1, 0x90, val); } }

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Patch set updated for coreboot: amd/mct/ddr3: Fix unintended sign extension warning
by Timothy Pearson 10 Jan '17

10 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18077 -gerrit commit 6700c9fd63053e49c4089aa96d7825b2867dc672 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:40:21 2017 -0600 amd/mct/ddr3: Fix unintended sign extension warning An unintended sign extension warning was thrown by Coverity. Explicitly state the unsigned nature of num_nodes. Found-by: Coverity Scan #1347342 Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f726345..8769a7d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2474,7 +2474,7 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, if (interleaved) /* Move upper limit down by 16M * the number of nodes */ - max_range_limit -= (0x1000000 * num_nodes); + max_range_limit -= (0x1000000 * (uint8_t)num_nodes); else /* Move upper limit down by 16M */ max_range_limit -= 0x1000000;

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coreboot-gerrit January 2017