Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18101
-gerrit
commit daed7709b9cfafb55733ffcb9c0395a9a0ab5801
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Jan 11 10:10:17 2017 -0700
sb/intel/ibexpeak: Update debug code do match other chips
Other chips dump tco_status here if it wasn't handled, which makes
sense.
tco_sts can't be zero here, because the call would have already returned
if it were. Also, dump_tco_status wouldn't print anything if tco_sts
were zero.
This will still only print the debug information if DEBUG_SMI is
enabled in Kconfig, so in general, this change won't have much of an
effect on anything.
Found-by: Coverity Scan #1229598
Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/southbridge/intel/ibexpeak/smihandler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index ec91bdf..a0b963e 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -709,7 +709,7 @@ static void southbridge_smi_tco(void)
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
printk(BIOS_DEBUG, "TCO Timeout.\n");
- } else if (!tco_sts) {
+ } else {
dump_tco_status(tco_sts);
}
}
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18024
-gerrit
commit 863d8c37992aad6bc8903ef7216c53b7d668d35d
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Jan 2 19:55:11 2017 -0700
3rdparty: update arm-trusted-firmware submodule
Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017
Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
3rdparty/arm-trusted-firmware | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index bfd9251..236c27d 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit bfd925139fdbc2e87979849907b34843aa326994
+Subproject commit 236c27d21f52ad8f0a998e54774e3d8a4b59129d
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18100
-gerrit
commit c8210ec73f0381ea17e6bc25f5619dcf20983917
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Jan 11 09:43:52 2017 -0700
sb/nvidia/mcp55: Fix typo in nic.c
The comparison value was obviously wrong here. One too many 'f'
characters.
Found-by: Coverity Scan #1229588 & 1229604
Change-Id: Iedd4f956d846f1c8661390b346c7397346def86b
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/southbridge/nvidia/mcp55/nic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 2474ef3..be9daf7 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -72,7 +72,7 @@ static void phy_detect(u8 *base)
val = phy_read(base, phyaddr, 1);
if (val < 0)
continue;
- if ((val & 0xffff) == 0xfffff)
+ if ((val & 0xffff) == 0xffff)
continue;
if ((val & 0xffff) == 0)
continue;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18098
-gerrit
commit 6ce406eddc42f0c99c25b84f1e1246a496f2a5e7
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Jan 11 17:17:18 2017 +0100
util/cbfstool: compile with -O2 by default
This speeds up the lzma encoder approximately four-fold.
Change-Id: Ibf896098799693ddd0f8a6c74bda2e518ecea869
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/cbfstool/Makefile.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index d666f6a..6882cba 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -65,6 +65,7 @@ ifwiobj += common.o
TOOLCFLAGS ?= -Werror -Wall -Wextra
TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
+TOOLCFLAGS += -O2
TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
the following patch was just integrated into master:
commit feb4ef6d92bdbcd12b2cd97b6446fb64b76cfef4
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Jan 9 15:28:24 2017 -0800
chromeos: fix build issues within sar.c
Build issues were somehow overlooked in commit
ed840023a84915ece4bc63edffef979926107d55:
1. hexstrtobin is not defined (needs the lib.h);
2. coreboot default compiler doesn't like variable initialization
within for loop.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Reviewed-on: https://review.coreboot.org/18076
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18076 for details.
-gerrit
the following patch was just integrated into master:
commit 88a2e3b3bf7b622cd3bef941a3e3f71337644a39
Author: Timothy Pearson <tpearson(a)raptorengineering.com>
Date: Mon Jan 9 17:40:21 2017 -0600
amd/mct/ddr3: Fix unintended sign extension warning
An unintended sign extension warning was thrown by Coverity.
Explicitly state the length of the constant multiplier.
Found-by: Coverity Scan #1347342
Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18077
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See https://review.coreboot.org/18077 for details.
-gerrit
the following patch was just integrated into master:
commit 590a3e1f6ccce873bb8f2129dc3680cab12e5a42
Author: Timothy Pearson <tpearson(a)raptorengineering.com>
Date: Mon Jan 9 17:54:35 2017 -0600
amd/mct/ddr3: Avoid using uninitialized register address in ECC setup
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions. Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.
Found-by: Coverity Scan #1347337
Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18079
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/18079 for details.
-gerrit
the following patch was just integrated into master:
commit 7d484106319a0f4261eb17326dd9fe31e2d4e401
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Jan 9 22:23:39 2017 -0800
skylake: Do not pass VBT to FSP if display init not required
The FSP 2.0 change broke the logic for determining whether or not
to execute the GOP binary. Modify the FSP 2.0 code to do the right
thing and check for display_init_required() before passing VBT into
FSP and the GOP binary.
BUG=chrome-os-partner:61726
TEST=disable developer mode and ensure FSP does not run GOP
Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18084
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/18084 for details.
-gerrit