coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mc_tcu3: Remove FSP_BAYTRAIL_GFX_INIT in Kconfig
by Werner Zeh 12 Jan '17

12 Jan '17

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18110 -gerrit commit 97244532c46c4ae313d55a5e8eba1b3dc7136c67 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:52:58 2017 +0100 mc_tcu3: Remove FSP_BAYTRAIL_GFX_INIT in Kconfig As the config switch FSP_BAYTRAIL_GFX_INIT is now set per default in fsp_baitrail, there is no need to set it here again. Just remove it from this Kconfig file. Change-Id: I9052b36668103d6c4481be13709e5bd157027c4b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 5ff233d..6a3b3c4 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES - select FSP_BAYTRAIL_GFX_INIT select USE_SIEMENS_HWILIB config MAINBOARD_DIR

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Patch set updated for coreboot: fsp_baytrail: Enable graphic init per default
by Werner Zeh 12 Jan '17

12 Jan '17

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18109 -gerrit commit 1fa82cb643955434d4edfc3ec1a7f9dd694b961c Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:29:04 2017 +0100 fsp_baytrail: Enable graphic init per default Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni(a)kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 689e625..2a6a01c 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -96,7 +96,7 @@ config VGA_BIOS_FILE default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS config FSP_BAYTRAIL_GFX_INIT - default n + default y bool help Enabling this option will activate graphics init code. With this init,

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New patch to review for coreboot: mc_tcu3: Remove FSP_BAYTRAIL_GFX_INIT in Kconfig
by Werner Zeh 12 Jan '17

12 Jan '17

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18110 -gerrit commit ae7308e8f82b6e3cba98376e79d2ca596681350d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:52:58 2017 +0100 mc_tcu3: Remove FSP_BAYTRAIL_GFX_INIT in Kconfig As the config switch FSP_BAYTRAIL_GFX_INIT is now set per default in fsp_baitrail, there is no need to set it here again. Just remove it from this Kconfig file. Change-Id: I9052b36668103d6c4481be13709e5bd157027c4b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 5ff233d..6a3b3c4 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES - select FSP_BAYTRAIL_GFX_INIT select USE_SIEMENS_HWILIB config MAINBOARD_DIR

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New patch to review for coreboot: fsp_baytrail: Enable graphic init per default
by Werner Zeh 12 Jan '17

12 Jan '17

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18109 -gerrit commit 929d3795d427e02378f7267a413319d663dcc611 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:29:04 2017 +0100 fsp_baytrail: Enable graphic init per default Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa2dbdd66b0470224715dc6da254ce62 - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni(a)kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 689e625..2a6a01c 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -96,7 +96,7 @@ config VGA_BIOS_FILE default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS config FSP_BAYTRAIL_GFX_INIT - default n + default y bool help Enabling this option will activate graphics init code. With this init,

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Patch set updated for coreboot: riscv: get SBI calls to work
by Ronald G. Minnich 11 Jan '17

11 Jan '17

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18097 -gerrit commit c5cf9b9edb8fa46df03f2cc569a5a306e721b671 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 10 18:06:48 2017 -0800 riscv: get SBI calls to work SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/bootblock.S | 10 +++++----- src/arch/riscv/include/mcall.h | 28 +++++++++++++++------------- src/arch/riscv/mcall.c | 25 +++++++++++++++++++++++-- src/arch/riscv/trap_handler.c | 12 +++++------- src/arch/riscv/trap_util.S | 12 ++++++++---- 5 files changed, 56 insertions(+), 31 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index c54c0e2..83063d6 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -30,6 +30,11 @@ _start: # and the stack must be page-aligned. la sp, _estack + # poison the stack + la t1, _stack + li t0, 0xdeadbeef + sd t0, 0(t1) + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE // Once again, the docs and toolchain disagree. @@ -39,11 +44,6 @@ _start: csrr a0, 0xf14 call hls_init - # poison the stack - la t1, _stack - li t0, 0xdeadbeef - sd t0, 0(t1) - la t0, trap_entry csrw mtvec, t0 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index a43b9cf..d3dda32 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -24,27 +24,29 @@ #define MENTRY_FRAME_SIZE HLS_SIZE typedef struct { - unsigned long base; - unsigned long size; - unsigned long node_id; + unsigned long base; + unsigned long size; + unsigned long node_id; } memory_block_info; typedef struct { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; + unsigned long dev; + unsigned long cmd; + unsigned long data; + unsigned long sbi_private_data; } sbi_device_message; typedef struct { - sbi_device_message* device_request_queue_head; - unsigned long device_request_queue_size; - sbi_device_message* device_response_queue_head; - sbi_device_message* device_response_queue_tail; + sbi_device_message *device_request_queue_head; + unsigned long device_request_queue_size; + sbi_device_message *device_response_queue_head; + sbi_device_message *device_response_queue_tail; - int hart_id; - int ipi_pending; + int hart_id; + int ipi_pending; + uint64_t *timecmp; + uint64_t *time; } hls_t; #define MACHINE_STACK_TOP() ({ \ diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index aa61ae4..37a9366 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -34,6 +34,8 @@ #include <string.h> #include <vm.h> +int mcalldebug; // set this interactively for copious debug. + uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) { if (id == 0) { @@ -74,9 +76,17 @@ uintptr_t mcall_shutdown(void) return 0; } -uintptr_t mcall_set_timer(unsigned long long when) +uintptr_t mcall_set_timer(uint64_t when) { - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + uint64_t *timecmp = HLS()->timecmp; + + if (mcalldebug) + printk(BIOS_SPEW, + "hart %d: HLS %p: mcall timecmp@%p to 0x%llx\n", + HLS()->hart_id, HLS(), timecmp, when); + *timecmp = when; + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); return 0; } @@ -94,8 +104,19 @@ uintptr_t mcall_dev_resp(void) void hls_init(uint32_t hart_id) { + query_result res; + + printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS()); memset(HLS(), 0, sizeof(*HLS())); HLS()->hart_id = hart_id; + + res = query_config_string(configstring(), "rtc{addr"); + HLS()->time = (void *)get_uint(res); + res = query_config_string(configstring(), "core{0{0{timecmp"); + HLS()->timecmp = (void *)get_uint(res); + + printk(BIOS_SPEW, "Time is %p and timecmp is %p\n", + HLS()->time, HLS()->timecmp); } uintptr_t mcall_console_putchar(uint8_t ch) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 5681209..9a8947c 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -64,9 +64,6 @@ void handle_supervisor_call(trapframe *tf) { returnValue = mcall_shutdown(); break; case SBI_ECALL_SET_TIMER: - printk(BIOS_DEBUG, - "Setting timer to %p (current time is %p)...\n", - (void *)arg0, (void *)rdtime()); returnValue = mcall_set_timer(arg0); break; case SBI_ECALL_QUERY_MEMORY: @@ -152,7 +149,7 @@ static void gettimer(void) static void interrupt_handler(trapframe *tf) { uint64_t cause = tf->cause & ~0x8000000000000000ULL; - uint32_t ssip, ssie; + uint32_t msip, ssie; switch (cause) { case IRQ_M_TIMER: @@ -183,10 +180,11 @@ static void interrupt_handler(trapframe *tf) if (!timecmp) gettimer(); + //printk(BIOS_SPEW, "timer interrupt\n"); *timecmp = (uint64_t) -1; - ssip = read_csr(sip); - ssip |= SIP_STIP; - write_csr(sip, ssip); + msip = read_csr(mip); + msip |= SIP_STIP; + write_csr(mip, msip); break; default: printk(BIOS_EMERG, "======================================\n"); diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 3357959..f2660c0 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -100,16 +100,18 @@ # get faulting insn, if it wasn't a fetch-related trap li x5,-1 STORE x5,36*REGBYTES(x2) -1: + .endm +.globl estack .text .global supervisor_trap_entry supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - li sp, 0x80FFF0 - 64 - 1:addi sp,sp,-320 + la sp, _estack + addi sp,sp,-64 + addi sp,sp,-304 save_tf move a0,sp jal trap_handler @@ -127,7 +129,9 @@ trap_entry: # TODO: Use the old stack pointer (plus an offset) for exceptions in machine # mode, to avoid overwriting stack data. - li sp, 0x8000fff0 + la sp, _estack + addi sp,sp,-64 + addi sp,sp,-304 save_tf move a0,sp

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Patch set updated for coreboot: intel/wifi: Create ACPI objects for wifi SAR configuration
by Robbie Zhang 11 Jan '17

11 Jan '17

Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17959 -gerrit commit 8b1e5114204287d0a605b5a3ac2b5d448f883b10 Author: Robbie Zhang <robbie.zhang(a)intel.com> Date: Fri Dec 23 12:20:47 2016 -0800 intel/wifi: Create ACPI objects for wifi SAR configuration To support intel wifi SAR configuration, it is required coreboot to publish two ACPI objects (WRDS and EWRD) to supply SAR limit data sets. VPD entry "wifi_sar" is required to supply the raw SAR limit data. BUG=chrome-os-partner:60821 TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot, check the SSDT dump and verify WRDS and EWRD structures. Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8 Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/drivers/intel/wifi/Kconfig | 24 ++++++++++++++ src/drivers/intel/wifi/chip.h | 32 +++++++++++++++++++ src/drivers/intel/wifi/wifi.c | 71 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 330de6c..1e6be6d 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -5,3 +5,27 @@ config DRIVERS_INTEL_WIFI help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. + +config USE_SAR + bool + default n + help + Enable it when wifi driver uses SAR configuration feature. + VPD entry "wifi_sar" is required to support it. + +config SAR_ENABLE + bool + default n + depends on USE_SAR + +config DSAR_ENABLE + bool + default n + depends on USE_SAR + +config DSAR_SET_NUM + hex "Number of SAR sets when D-SAR is enabled" + default 0x3 + depends on USE_SAR + help + There can be up to 3 optional SAR table sets. diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h index 117d39c..0871874 100644 --- a/src/drivers/intel/wifi/chip.h +++ b/src/drivers/intel/wifi/chip.h @@ -1,3 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _WIFI_CHIP_H_ +#define _WIFI_CHIP_H_ + +/* WRDS Spec Revision */ +#define WRDS_REVISION 0x0 + +/* EWRD Spec Revision */ +#define EWRD_REVISION 0x0 + +/* WRDS Domain type */ +#define WRDS_DOMAIN_TYPE_WIFI 0x7 + +/* EWRD Domain type */ +#define EWRD_DOMAIN_TYPE_WIFI 0x7 + struct drivers_intel_wifi_config { unsigned wake; /* Wake pin for ACPI _PRW */ }; + +#endif /* _WIFI_CHIP_H_ */ diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 789d0d5..06bc54c 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <sar.h> #include <smbios.h> #include <string.h> #include <wrdd.h> @@ -59,6 +60,72 @@ static int smbios_write_wifi(struct device *dev, int *handle, #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void emit_sar_acpi_structures(void) +{ + int i, j, package_size; + struct wifi_sar_limits sar_limits; + + /* Retrieve the sar limits data */ + if (get_wifi_sar_limits(&sar_limits) < 0) { + printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + return; + } + + /* + * Name ("WRDS", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * WiFi SAR BIOS, // BIOS SAR Enable/disable + * SAR Table Set // Set#1 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("WRDS"); + acpigen_write_package(2); + acpigen_write_dword(WRDS_REVISION); + /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ + package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG_SAR_ENABLE); + for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) + acpigen_write_byte(sar_limits.sar_limit[0][i]); + acpigen_pop_len(); + acpigen_pop_len(); + + /* + * Name ("EWRD", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * Dynamic SAR Enable, // Dynamic SAR Enable/disable + * Extended SAR sets, // Number of optional SAR table sets + * SAR Table Set, // Set#2 of SAR Table (10 bytes) + * SAR Table Set, // Set#3 of SAR Table (10 bytes) + * SAR Table Set // Set#4 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("EWRD"); + acpigen_write_package(2); + acpigen_write_dword(EWRD_REVISION); + /* + * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' + * + number of bytes for Set#2 & 3 & 4 + */ + package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG_DSAR_ENABLE); + acpigen_write_dword(CONFIG_DSAR_SET_NUM); + for (i = 1; i < NUM_SAR_LIMITS; i++) + for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) + acpigen_write_byte(sar_limits.sar_limit[i][j]); + acpigen_pop_len(); + acpigen_pop_len(); +} + static void intel_wifi_fill_ssdt(struct device *dev) { struct drivers_intel_wifi_config *config = dev->chip_info; @@ -105,6 +172,10 @@ static void intel_wifi_fill_ssdt(struct device *dev) acpigen_pop_len(); } + /* Fill Wifi sar related ACPI structures */ + if (IS_ENABLED(CONFIG_USE_SAR)) + emit_sar_acpi_structures(); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: google/pyro: Add ELAN touch screen support
by Keith Tzeng 11 Jan '17

11 Jan '17

Keith Tzeng (keith.tzeng(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18086 -gerrit commit 36f9774e7cbb1b76aa10cec909585f58cb318506 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Tue Jan 10 22:31:05 2017 +0800 google/pyro: Add ELAN touch screen support Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=chrome-os-partner:61803 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index bc06bbb..f7551d6 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -176,6 +176,21 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + + chip drivers/generic/gpio_regulator + register "name" = ""vcc33"" + register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enabled_on_boot" = "1" + device generic 0 on end + end + + device i2c 10 on end + end end # - I2C 3 device pci 17.0 on chip drivers/i2c/generic

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New patch to review for coreboot: Run sdhci init on an AP in parallel
by Bora Guvendik 11 Jan '17

11 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18108 -gerrit commit 9b1285b66320e238f099f43824178961d3360c54 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed Jan 4 17:12:55 2017 -0800 Run sdhci init on an AP in parallel Initialize sdhci and setup mmc on AP. Put the sdhci in transfer mode and set a flag to let payload know that it can just resume operations. Let BSP run in parallel and do work until it is time to write coreboot tables. At that point, make BSP wait for AP to finish up. If AP fails to setup sdhci or mmc, let payload re-initialize everything. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I86a8b3857685d8638c4cdcd865b16b9454496cb2 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/drivers/storage/sdhci.c | 6 ++++++ src/drivers/storage/sdhci.h | 2 ++ src/lib/coreboot_table.c | 3 +++ src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/mainboard.c | 38 +++++++++++++++++++++++++++++++++++ 5 files changed, 50 insertions(+) diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c index 54cc54d..88d7180 100644 --- a/src/drivers/storage/sdhci.c +++ b/src/drivers/storage/sdhci.c @@ -29,6 +29,8 @@ #include <timer.h> #include <string.h> +atomic_t sdhci_barrier = ATOMIC_INIT(0); + static void sdhci_reset(SdhciHost *host, u8 mask) { unsigned long timeout; @@ -718,4 +720,8 @@ void add_sdhci(SdhciHost *host) host->mmc_ctrlr.b_max = 65535; } +atomic_t* get_sdhci_barrier( void ) +{ + return &sdhci_barrier; +} diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h index c44edad..6ee7a8f 100644 --- a/src/drivers/storage/sdhci.h +++ b/src/drivers/storage/sdhci.h @@ -23,6 +23,7 @@ #include "mmc.h" #include <device/pci_ops.h> +#include <smp/atomic.h> /* * Controller registers @@ -346,6 +347,7 @@ static inline u8 sdhci_readb(SdhciHost *host, int reg) void add_sdhci(SdhciHost *host); int sdhci_init(SdhciHost *host); SdhciHost* sdhci_get_host_ptr( void ); +atomic_t* get_sdhci_barrier(void); /* Add SDHCI controller from PCI */ SdhciHost *new_pci_sdhci_host(struct device *dev, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 989f8d1..13d0dc9 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -16,6 +16,7 @@ */ #include <arch/cbconfig.h> +#include <cpu/x86/mp.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -157,6 +158,8 @@ static void lb_sdhci_host( struct lb_header *header ) struct lb_sdhci_host_info *lb_host; SdhciHost* host_ptr = sdhci_get_host_ptr(); + barrier_wait_timeout(get_sdhci_barrier(),500); + lb_host = (struct lb_sdhci_host_info *)lb_new_record(header); lb_host->tag = LB_TAG_SDHCI_HOST; diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 0766577a..38af4be 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -19,6 +19,7 @@ if BOARD_GOOGLE_BASEBOARD_REEF config BASEBOARD_REEF_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP + select DRIVERS_STORAGE config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 702269c..e7a80cc 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -28,6 +28,41 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> +#include <drivers/storage/sdhci.h> +#include <cpu/cpu.h> +#include <cpu/x86/mp.h> +#include <soc/pci_devs.h> + +#define EMMC_SD_CLOCK_MIN 400000 +#define EMMC_CLOCK_MAX 200000000 +#define SD_CLOCK_MAX 52000000 + +static void platform_emmc_init(void) +{ + SdhciHost *host; + + host = new_pci_sdhci_host(EMMC_DEV, + SDHCI_PLATFORM_NO_EMMC_HS200, + EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX); + sdhci_init(host); + mmc_setup_media(&host->mmc_ctrlr,0); + host->initialized = 1; + + // Let BSP continue + release_barrier(get_sdhci_barrier()); +} + +static void run_on_single_ap(void) +{ + struct cpu_info *info; + + info = cpu_info(); + + if( info->index != 1 ) + return; + + platform_emmc_init(); +} static void mainboard_init(void *chip_info) { @@ -35,6 +70,9 @@ static void mainboard_init(void *chip_info) const struct pad_config *pads; size_t num; + if (mp_run_on_aps(&run_on_single_ap, 1000) < 0) + printk(BIOS_ERR, "failed to run sdhci init\n"); + boardid = board_id(); printk(BIOS_INFO, "Board ID: %d\n", boardid);

1 0

New patch to review for coreboot: Add a lock with timeout
by Bora Guvendik 11 Jan '17

11 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18107 -gerrit commit fa28608c185eeb6f6ef98811683ee0cc39724a5a Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed Jan 4 16:51:31 2017 -0800 Add a lock with timeout In case something goes wrong on one of the cpus, add the ability to use a lock with timeout so that other cpus don't wait forever. Turn lock and release into apis BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/cpu/x86/mp_init.c | 21 +++++++++++++++++++-- src/include/cpu/x86/mp.h | 6 ++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c989963..f137ede 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -138,7 +138,7 @@ struct cpu_map { /* Keep track of APIC and device structure for each CPU. */ static struct cpu_map cpus[CONFIG_MAX_CPUS]; -static inline void barrier_wait(atomic_t *b) +inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) { asm ("pause"); @@ -146,7 +146,24 @@ static inline void barrier_wait(atomic_t *b) mfence(); } -static inline void release_barrier(atomic_t *b) +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms) +{ + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout_ms); + + while (atomic_read(b) == 0) { + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) + break; + asm ("pause"); + } + mfence(); +} + +inline void release_barrier(atomic_t *b) { mfence(); atomic_set(b, 1); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b9b4d57..113ed84 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -151,4 +151,10 @@ void smm_initiate_relocation_parallel(void); /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +inline void barrier_wait(atomic_t *b); + +inline void release_barrier(atomic_t *b); + +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms); + #endif /* _X86_MP_H_ */

1 0

New patch to review for coreboot: Pass the firmware sdhci data to deptcharge
by Bora Guvendik 11 Jan '17

11 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18106 -gerrit commit ebf9cf33b631a49fb609c5cdb731caab9c7ad085 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Fri Dec 9 11:14:43 2016 -0800 Pass the firmware sdhci data to deptcharge Write sdhci and mmc driver data to coreboot tables so that payload can use the data and start talking to emmc without reinitializing the storage driver. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I496c103e4a4889b665bc4bcfe0dc8138c5741f87 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 53 +++++++++++++++ payloads/libpayload/include/sysinfo.h | 3 + payloads/libpayload/libc/coreboot.c | 24 +++++++ src/commonlib/include/commonlib/coreboot_tables.h | 53 +++++++++++++++ src/lib/coreboot_table.c | 81 +++++++++++++++++++++++ 5 files changed, 214 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index d77242a..fbe83b4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -291,6 +291,59 @@ struct cb_tsc_info { uint32_t freq_khz; }; +#define CB_TAG_SDHCI_HOST 0x0033 +struct cb_sdhci_host_info { + uint32_t tag; + uint32_t size; + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; + int removable; + unsigned voltages; + unsigned dma64; +}; + +#define CB_TAG_MMC_MEDIA 0x0034 +struct cb_mmc_media_info { + uint32_t tag; + uint32_t size; + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + uint32_t erase_size; + uint32_t trim_mult; + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t op_cond_response; +}; + +#define CB_TAG_MMC_CTRLR 0x0035 +struct cb_mmc_ctrlr_info { + uint32_t tag; + uint32_t size; + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + uint32_t hardcoded_voltage; +}; + #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 2110d88..baf9446 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -124,6 +124,9 @@ struct sysinfo_t { uint64_t boot_media_size; uint64_t mtc_start; uint32_t mtc_size; + struct cb_sdhci_host_info *sdhci_host; + struct cb_mmc_media_info *mmc_media; + struct cb_mmc_ctrlr_info *mmc_ctrlr; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 9fc6a69..6d9c04d 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -151,6 +151,21 @@ static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) info->board_id = cbbid->board_id; } +static void cb_parse_sdhci_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->sdhci_host = (struct cb_sdhci_host_info*)ptr; +} + +static void cb_mmc_media_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->mmc_media = (struct cb_mmc_media_info*)ptr; +} + +static void cb_mmc_ctrlr_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->mmc_ctrlr = (struct cb_mmc_ctrlr_info*)ptr; +} + static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info) { struct cb_ram_code *const ram_code = (struct cb_ram_code *)ptr; @@ -375,6 +390,15 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_BOARD_ID: cb_parse_board_id(ptr, info); break; + case CB_TAG_SDHCI_HOST: + cb_parse_sdhci_info(ptr, info); + break; + case CB_TAG_MMC_MEDIA: + cb_mmc_media_info(ptr, info); + break; + case CB_TAG_MMC_CTRLR: + cb_mmc_ctrlr_info(ptr, info); + break; case CB_TAG_RAM_CODE: cb_parse_ram_code(ptr, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7d58fdd..b5d44f0 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -358,6 +358,59 @@ struct lb_tsc_info { uint32_t freq_khz; }; +#define LB_TAG_SDHCI_HOST 0x0033 +struct lb_sdhci_host_info { + uint32_t tag; + uint32_t size; + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; + int removable; + unsigned voltages; + unsigned dma64; +}; + +#define LB_TAG_MMC_MEDIA 0x0034 +struct lb_mmc_media_info { + uint32_t tag; + uint32_t size; + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + uint32_t erase_size; + uint32_t trim_mult; + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t op_cond_response; +}; + +#define LB_TAG_MMC_CTRLR 0x0035 +struct lb_mmc_ctrlr_info { + uint32_t tag; + uint32_t size; + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + uint32_t hardcoded_voltage; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f8da658..989f8d1 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -46,6 +46,7 @@ #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> #endif +#include <drivers/storage/sdhci.h> static struct lb_header *lb_table_init(unsigned long addr) { @@ -151,6 +152,77 @@ void __attribute__((weak)) lb_framebuffer(struct lb_header *header) framebuffer->size = sizeof(*framebuffer); #endif } +static void lb_sdhci_host( struct lb_header *header ) +{ + struct lb_sdhci_host_info *lb_host; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_host = (struct lb_sdhci_host_info *)lb_new_record(header); + + lb_host->tag = LB_TAG_SDHCI_HOST; + lb_host->size = sizeof(*lb_host); + + lb_host->initialized = host_ptr->initialized; + lb_host->quirks = host_ptr->quirks; + lb_host->host_caps = host_ptr->host_caps; + lb_host->version = host_ptr->version; + lb_host->clock = host_ptr->clock; + lb_host->clock_f_min = host_ptr->clock_f_min; + lb_host->clock_f_max = host_ptr->clock_f_max; + lb_host->clock_base = host_ptr->clock_base; + lb_host->removable = host_ptr->removable; + lb_host->voltages = host_ptr->voltages; + lb_host->dma64 = host_ptr->dma64; +} + +static void lb_mmc_media( struct lb_header *header ) +{ + struct lb_mmc_media_info *lb_mmc_media; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_mmc_media = (struct lb_mmc_media_info *)lb_new_record(header); + + lb_mmc_media->tag = LB_TAG_MMC_MEDIA; + lb_mmc_media->size = sizeof(*lb_mmc_media); + + lb_mmc_media->caps = host_ptr->mmc_ctrlr.media->caps; + lb_mmc_media->version = host_ptr->mmc_ctrlr.media->version; + lb_mmc_media->read_bl_len = host_ptr->mmc_ctrlr.media->read_bl_len; + lb_mmc_media->write_bl_len = host_ptr->mmc_ctrlr.media->write_bl_len; + lb_mmc_media->capacity = host_ptr->mmc_ctrlr.media->capacity; + lb_mmc_media->high_capacity = host_ptr->mmc_ctrlr.media->high_capacity; + lb_mmc_media->tran_speed = host_ptr->mmc_ctrlr.media->tran_speed; + lb_mmc_media->erase_size = host_ptr->mmc_ctrlr.media->erase_size; + lb_mmc_media->trim_mult = host_ptr->mmc_ctrlr.media->trim_mult; + lb_mmc_media->ocr = host_ptr->mmc_ctrlr.media->ocr; + lb_mmc_media->rca = host_ptr->mmc_ctrlr.media->rca; + lb_mmc_media->op_cond_response = host_ptr->mmc_ctrlr.media->op_cond_response; + + memcpy(&lb_mmc_media->scr[0],&host_ptr->mmc_ctrlr.media->scr[0],2); + memcpy(&lb_mmc_media->csd[0],&host_ptr->mmc_ctrlr.media->csd[0],4); + memcpy(&lb_mmc_media->cid[0],&host_ptr->mmc_ctrlr.media->cid[0],4); +} + +static void lb_mmc_ctrlr( struct lb_header *header ) +{ + struct lb_mmc_ctrlr_info *lb_mmc_ctrlr; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_mmc_ctrlr = (struct lb_mmc_ctrlr_info *)lb_new_record(header); + + lb_mmc_ctrlr->tag = LB_TAG_MMC_CTRLR; + lb_mmc_ctrlr->size = sizeof(*lb_mmc_ctrlr); + + lb_mmc_ctrlr->voltages = host_ptr->mmc_ctrlr.voltages; + lb_mmc_ctrlr->f_min = host_ptr->mmc_ctrlr.f_min; + lb_mmc_ctrlr->f_max = host_ptr->mmc_ctrlr.f_max; + lb_mmc_ctrlr->bus_width = host_ptr->mmc_ctrlr.bus_width; + lb_mmc_ctrlr->bus_hz = host_ptr->mmc_ctrlr.bus_hz; + lb_mmc_ctrlr->caps = host_ptr->mmc_ctrlr.caps; + lb_mmc_ctrlr->b_max = host_ptr->mmc_ctrlr.b_max; + lb_mmc_ctrlr->timing = host_ptr->mmc_ctrlr.timing; + lb_mmc_ctrlr->hardcoded_voltage = host_ptr->mmc_ctrlr.hardcoded_voltage; +} void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count) @@ -534,6 +606,15 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_vboot_handoff(head); #endif + /* Add sdhci host information */ + lb_sdhci_host(head); + + /* Add mmc media information */ + lb_mmc_media(head); + + /* Add mmc ctrlr information */ + lb_mmc_ctrlr(head); + /* Add board ID if available */ lb_board_id(head);

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coreboot-gerrit January 2017