coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Pass the firmware sdhci data to deptcharge
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18106 -gerrit commit c21f7dde830b448a2fb86d574d695d10b5c0b07f Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Fri Dec 9 11:14:43 2016 -0800 Pass the firmware sdhci data to deptcharge Write sdhci and mmc driver data to coreboot tables so that payload can use the data and start talking to emmc without reinitializing the storage driver. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I496c103e4a4889b665bc4bcfe0dc8138c5741f87 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 53 ++++++++++++++ payloads/libpayload/include/sysinfo.h | 3 + payloads/libpayload/libc/coreboot.c | 24 +++++++ src/commonlib/include/commonlib/coreboot_tables.h | 53 ++++++++++++++ src/lib/coreboot_table.c | 87 +++++++++++++++++++++++ 5 files changed, 220 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index d77242a..fbe83b4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -291,6 +291,59 @@ struct cb_tsc_info { uint32_t freq_khz; }; +#define CB_TAG_SDHCI_HOST 0x0033 +struct cb_sdhci_host_info { + uint32_t tag; + uint32_t size; + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; + int removable; + unsigned voltages; + unsigned dma64; +}; + +#define CB_TAG_MMC_MEDIA 0x0034 +struct cb_mmc_media_info { + uint32_t tag; + uint32_t size; + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + uint32_t erase_size; + uint32_t trim_mult; + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t op_cond_response; +}; + +#define CB_TAG_MMC_CTRLR 0x0035 +struct cb_mmc_ctrlr_info { + uint32_t tag; + uint32_t size; + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + uint32_t hardcoded_voltage; +}; + #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 2110d88..baf9446 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -124,6 +124,9 @@ struct sysinfo_t { uint64_t boot_media_size; uint64_t mtc_start; uint32_t mtc_size; + struct cb_sdhci_host_info *sdhci_host; + struct cb_mmc_media_info *mmc_media; + struct cb_mmc_ctrlr_info *mmc_ctrlr; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 9fc6a69..6d9c04d 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -151,6 +151,21 @@ static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) info->board_id = cbbid->board_id; } +static void cb_parse_sdhci_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->sdhci_host = (struct cb_sdhci_host_info*)ptr; +} + +static void cb_mmc_media_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->mmc_media = (struct cb_mmc_media_info*)ptr; +} + +static void cb_mmc_ctrlr_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->mmc_ctrlr = (struct cb_mmc_ctrlr_info*)ptr; +} + static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info) { struct cb_ram_code *const ram_code = (struct cb_ram_code *)ptr; @@ -375,6 +390,15 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_BOARD_ID: cb_parse_board_id(ptr, info); break; + case CB_TAG_SDHCI_HOST: + cb_parse_sdhci_info(ptr, info); + break; + case CB_TAG_MMC_MEDIA: + cb_mmc_media_info(ptr, info); + break; + case CB_TAG_MMC_CTRLR: + cb_mmc_ctrlr_info(ptr, info); + break; case CB_TAG_RAM_CODE: cb_parse_ram_code(ptr, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7d58fdd..b5d44f0 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -358,6 +358,59 @@ struct lb_tsc_info { uint32_t freq_khz; }; +#define LB_TAG_SDHCI_HOST 0x0033 +struct lb_sdhci_host_info { + uint32_t tag; + uint32_t size; + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; + int removable; + unsigned voltages; + unsigned dma64; +}; + +#define LB_TAG_MMC_MEDIA 0x0034 +struct lb_mmc_media_info { + uint32_t tag; + uint32_t size; + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + uint32_t erase_size; + uint32_t trim_mult; + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t op_cond_response; +}; + +#define LB_TAG_MMC_CTRLR 0x0035 +struct lb_mmc_ctrlr_info { + uint32_t tag; + uint32_t size; + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + uint32_t hardcoded_voltage; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f8da658..932c8fe 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -46,6 +46,9 @@ #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> #endif +#if CONFIG_DRIVERS_STORAGE +#include <drivers/storage/sdhci.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) { @@ -152,6 +155,80 @@ void __attribute__((weak)) lb_framebuffer(struct lb_header *header) #endif } +#if CONFIG_DRIVERS_STORAGE +static void lb_sdhci_host( struct lb_header *header ) +{ + struct lb_sdhci_host_info *lb_host; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_host = (struct lb_sdhci_host_info *)lb_new_record(header); + + lb_host->tag = LB_TAG_SDHCI_HOST; + lb_host->size = sizeof(*lb_host); + + lb_host->initialized = host_ptr->initialized; + lb_host->quirks = host_ptr->quirks; + lb_host->host_caps = host_ptr->host_caps; + lb_host->version = host_ptr->version; + lb_host->clock = host_ptr->clock; + lb_host->clock_f_min = host_ptr->clock_f_min; + lb_host->clock_f_max = host_ptr->clock_f_max; + lb_host->clock_base = host_ptr->clock_base; + lb_host->removable = host_ptr->removable; + lb_host->voltages = host_ptr->voltages; + lb_host->dma64 = host_ptr->dma64; +} + +static void lb_mmc_media( struct lb_header *header ) +{ + struct lb_mmc_media_info *lb_mmc_media; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_mmc_media = (struct lb_mmc_media_info *)lb_new_record(header); + + lb_mmc_media->tag = LB_TAG_MMC_MEDIA; + lb_mmc_media->size = sizeof(*lb_mmc_media); + + lb_mmc_media->caps = host_ptr->mmc_ctrlr.media->caps; + lb_mmc_media->version = host_ptr->mmc_ctrlr.media->version; + lb_mmc_media->read_bl_len = host_ptr->mmc_ctrlr.media->read_bl_len; + lb_mmc_media->write_bl_len = host_ptr->mmc_ctrlr.media->write_bl_len; + lb_mmc_media->capacity = host_ptr->mmc_ctrlr.media->capacity; + lb_mmc_media->high_capacity = host_ptr->mmc_ctrlr.media->high_capacity; + lb_mmc_media->tran_speed = host_ptr->mmc_ctrlr.media->tran_speed; + lb_mmc_media->erase_size = host_ptr->mmc_ctrlr.media->erase_size; + lb_mmc_media->trim_mult = host_ptr->mmc_ctrlr.media->trim_mult; + lb_mmc_media->ocr = host_ptr->mmc_ctrlr.media->ocr; + lb_mmc_media->rca = host_ptr->mmc_ctrlr.media->rca; + lb_mmc_media->op_cond_response = host_ptr->mmc_ctrlr.media->op_cond_response; + + memcpy(&lb_mmc_media->scr[0],&host_ptr->mmc_ctrlr.media->scr[0],2); + memcpy(&lb_mmc_media->csd[0],&host_ptr->mmc_ctrlr.media->csd[0],4); + memcpy(&lb_mmc_media->cid[0],&host_ptr->mmc_ctrlr.media->cid[0],4); +} + +static void lb_mmc_ctrlr( struct lb_header *header ) +{ + struct lb_mmc_ctrlr_info *lb_mmc_ctrlr; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_mmc_ctrlr = (struct lb_mmc_ctrlr_info *)lb_new_record(header); + + lb_mmc_ctrlr->tag = LB_TAG_MMC_CTRLR; + lb_mmc_ctrlr->size = sizeof(*lb_mmc_ctrlr); + + lb_mmc_ctrlr->voltages = host_ptr->mmc_ctrlr.voltages; + lb_mmc_ctrlr->f_min = host_ptr->mmc_ctrlr.f_min; + lb_mmc_ctrlr->f_max = host_ptr->mmc_ctrlr.f_max; + lb_mmc_ctrlr->bus_width = host_ptr->mmc_ctrlr.bus_width; + lb_mmc_ctrlr->bus_hz = host_ptr->mmc_ctrlr.bus_hz; + lb_mmc_ctrlr->caps = host_ptr->mmc_ctrlr.caps; + lb_mmc_ctrlr->b_max = host_ptr->mmc_ctrlr.b_max; + lb_mmc_ctrlr->timing = host_ptr->mmc_ctrlr.timing; + lb_mmc_ctrlr->hardcoded_voltage = host_ptr->mmc_ctrlr.hardcoded_voltage; +} +#endif /* CONFIG_DRIVERS_STORAGE */ + void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count) { @@ -534,6 +611,16 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_vboot_handoff(head); #endif +#if CONFIG_DRIVERS_STORAGE + /* Add sdhci host information */ + lb_sdhci_host(head); + + /* Add mmc media information */ + lb_mmc_media(head); + + /* Add mmc ctrlr information */ + lb_mmc_ctrlr(head); +#endif /* Add board ID if available */ lb_board_id(head);

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Patch set updated for coreboot: Run sdhci init on an AP in parallel
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18108 -gerrit commit 72e1f042e44fc5ba80e1d807e1f38b9a24a66788 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed Jan 4 17:12:55 2017 -0800 Run sdhci init on an AP in parallel Initialize sdhci and setup mmc on AP. Put the sdhci in transfer mode and set a flag to let payload know that it can just resume operations. Let BSP run in parallel and do work until it is time to write coreboot tables. At that point, make BSP wait for AP to finish up. If AP fails to setup sdhci or mmc, let payload re-initialize everything. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I86a8b3857685d8638c4cdcd865b16b9454496cb2 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/drivers/storage/sdhci.c | 6 ++++++ src/drivers/storage/sdhci.h | 2 ++ src/lib/coreboot_table.c | 3 +++ src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/mainboard.c | 38 +++++++++++++++++++++++++++++++++++ 5 files changed, 50 insertions(+) diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c index 54cc54d..88d7180 100644 --- a/src/drivers/storage/sdhci.c +++ b/src/drivers/storage/sdhci.c @@ -29,6 +29,8 @@ #include <timer.h> #include <string.h> +atomic_t sdhci_barrier = ATOMIC_INIT(0); + static void sdhci_reset(SdhciHost *host, u8 mask) { unsigned long timeout; @@ -718,4 +720,8 @@ void add_sdhci(SdhciHost *host) host->mmc_ctrlr.b_max = 65535; } +atomic_t* get_sdhci_barrier( void ) +{ + return &sdhci_barrier; +} diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h index c44edad..6ee7a8f 100644 --- a/src/drivers/storage/sdhci.h +++ b/src/drivers/storage/sdhci.h @@ -23,6 +23,7 @@ #include "mmc.h" #include <device/pci_ops.h> +#include <smp/atomic.h> /* * Controller registers @@ -346,6 +347,7 @@ static inline u8 sdhci_readb(SdhciHost *host, int reg) void add_sdhci(SdhciHost *host); int sdhci_init(SdhciHost *host); SdhciHost* sdhci_get_host_ptr( void ); +atomic_t* get_sdhci_barrier(void); /* Add SDHCI controller from PCI */ SdhciHost *new_pci_sdhci_host(struct device *dev, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 989f8d1..13d0dc9 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -16,6 +16,7 @@ */ #include <arch/cbconfig.h> +#include <cpu/x86/mp.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -157,6 +158,8 @@ static void lb_sdhci_host( struct lb_header *header ) struct lb_sdhci_host_info *lb_host; SdhciHost* host_ptr = sdhci_get_host_ptr(); + barrier_wait_timeout(get_sdhci_barrier(),500); + lb_host = (struct lb_sdhci_host_info *)lb_new_record(header); lb_host->tag = LB_TAG_SDHCI_HOST; diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 0766577..38af4be 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -19,6 +19,7 @@ if BOARD_GOOGLE_BASEBOARD_REEF config BASEBOARD_REEF_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP + select DRIVERS_STORAGE config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 702269c..e7a80cc 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -28,6 +28,41 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> +#include <drivers/storage/sdhci.h> +#include <cpu/cpu.h> +#include <cpu/x86/mp.h> +#include <soc/pci_devs.h> + +#define EMMC_SD_CLOCK_MIN 400000 +#define EMMC_CLOCK_MAX 200000000 +#define SD_CLOCK_MAX 52000000 + +static void platform_emmc_init(void) +{ + SdhciHost *host; + + host = new_pci_sdhci_host(EMMC_DEV, + SDHCI_PLATFORM_NO_EMMC_HS200, + EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX); + sdhci_init(host); + mmc_setup_media(&host->mmc_ctrlr,0); + host->initialized = 1; + + // Let BSP continue + release_barrier(get_sdhci_barrier()); +} + +static void run_on_single_ap(void) +{ + struct cpu_info *info; + + info = cpu_info(); + + if( info->index != 1 ) + return; + + platform_emmc_init(); +} static void mainboard_init(void *chip_info) { @@ -35,6 +70,9 @@ static void mainboard_init(void *chip_info) const struct pad_config *pads; size_t num; + if (mp_run_on_aps(&run_on_single_ap, 1000) < 0) + printk(BIOS_ERR, "failed to run sdhci init\n"); + boardid = board_id(); printk(BIOS_INFO, "Board ID: %d\n", boardid);

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Patch set updated for coreboot: Add a lock with timeout
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18107 -gerrit commit a36f77d0da1f8ff9f47b1d32785df7941bc86b98 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed Jan 4 16:51:31 2017 -0800 Add a lock with timeout In case something goes wrong on one of the cpus, add the ability to use a lock with timeout so that other cpus don't wait forever. Turn lock and release into apis BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/cpu/x86/mp_init.c | 21 +++++++++++++++++++-- src/include/cpu/x86/mp.h | 6 ++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c989963..f137ede 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -138,7 +138,7 @@ struct cpu_map { /* Keep track of APIC and device structure for each CPU. */ static struct cpu_map cpus[CONFIG_MAX_CPUS]; -static inline void barrier_wait(atomic_t *b) +inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) { asm ("pause"); @@ -146,7 +146,24 @@ static inline void barrier_wait(atomic_t *b) mfence(); } -static inline void release_barrier(atomic_t *b) +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms) +{ + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout_ms); + + while (atomic_read(b) == 0) { + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) + break; + asm ("pause"); + } + mfence(); +} + +inline void release_barrier(atomic_t *b) { mfence(); atomic_set(b, 1); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b9b4d57..113ed84 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -151,4 +151,10 @@ void smm_initiate_relocation_parallel(void); /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +inline void barrier_wait(atomic_t *b); + +inline void release_barrier(atomic_t *b); + +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms); + #endif /* _X86_MP_H_ */

1 0

Patch set updated for coreboot: Pass the firmware sdhci data to deptcharge
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18106 -gerrit commit 5a9956ff66ca6600acbb68d7f9e6948c0c1ff688 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Fri Dec 9 11:14:43 2016 -0800 Pass the firmware sdhci data to deptcharge Write sdhci and mmc driver data to coreboot tables so that payload can use the data and start talking to emmc without reinitializing the storage driver. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I496c103e4a4889b665bc4bcfe0dc8138c5741f87 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 53 +++++++++++++++ payloads/libpayload/include/sysinfo.h | 3 + payloads/libpayload/libc/coreboot.c | 24 +++++++ src/commonlib/include/commonlib/coreboot_tables.h | 53 +++++++++++++++ src/lib/coreboot_table.c | 81 +++++++++++++++++++++++ 5 files changed, 214 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index d77242a..fbe83b4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -291,6 +291,59 @@ struct cb_tsc_info { uint32_t freq_khz; }; +#define CB_TAG_SDHCI_HOST 0x0033 +struct cb_sdhci_host_info { + uint32_t tag; + uint32_t size; + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; + int removable; + unsigned voltages; + unsigned dma64; +}; + +#define CB_TAG_MMC_MEDIA 0x0034 +struct cb_mmc_media_info { + uint32_t tag; + uint32_t size; + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + uint32_t erase_size; + uint32_t trim_mult; + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t op_cond_response; +}; + +#define CB_TAG_MMC_CTRLR 0x0035 +struct cb_mmc_ctrlr_info { + uint32_t tag; + uint32_t size; + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + uint32_t hardcoded_voltage; +}; + #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 2110d88..baf9446 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -124,6 +124,9 @@ struct sysinfo_t { uint64_t boot_media_size; uint64_t mtc_start; uint32_t mtc_size; + struct cb_sdhci_host_info *sdhci_host; + struct cb_mmc_media_info *mmc_media; + struct cb_mmc_ctrlr_info *mmc_ctrlr; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 9fc6a69..6d9c04d 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -151,6 +151,21 @@ static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) info->board_id = cbbid->board_id; } +static void cb_parse_sdhci_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->sdhci_host = (struct cb_sdhci_host_info*)ptr; +} + +static void cb_mmc_media_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->mmc_media = (struct cb_mmc_media_info*)ptr; +} + +static void cb_mmc_ctrlr_info(unsigned char *ptr, struct sysinfo_t *info) +{ + info->mmc_ctrlr = (struct cb_mmc_ctrlr_info*)ptr; +} + static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info) { struct cb_ram_code *const ram_code = (struct cb_ram_code *)ptr; @@ -375,6 +390,15 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_BOARD_ID: cb_parse_board_id(ptr, info); break; + case CB_TAG_SDHCI_HOST: + cb_parse_sdhci_info(ptr, info); + break; + case CB_TAG_MMC_MEDIA: + cb_mmc_media_info(ptr, info); + break; + case CB_TAG_MMC_CTRLR: + cb_mmc_ctrlr_info(ptr, info); + break; case CB_TAG_RAM_CODE: cb_parse_ram_code(ptr, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7d58fdd..b5d44f0 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -358,6 +358,59 @@ struct lb_tsc_info { uint32_t freq_khz; }; +#define LB_TAG_SDHCI_HOST 0x0033 +struct lb_sdhci_host_info { + uint32_t tag; + uint32_t size; + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; + int removable; + unsigned voltages; + unsigned dma64; +}; + +#define LB_TAG_MMC_MEDIA 0x0034 +struct lb_mmc_media_info { + uint32_t tag; + uint32_t size; + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + uint32_t erase_size; + uint32_t trim_mult; + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t op_cond_response; +}; + +#define LB_TAG_MMC_CTRLR 0x0035 +struct lb_mmc_ctrlr_info { + uint32_t tag; + uint32_t size; + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + uint32_t hardcoded_voltage; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f8da658..989f8d1 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -46,6 +46,7 @@ #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> #endif +#include <drivers/storage/sdhci.h> static struct lb_header *lb_table_init(unsigned long addr) { @@ -151,6 +152,77 @@ void __attribute__((weak)) lb_framebuffer(struct lb_header *header) framebuffer->size = sizeof(*framebuffer); #endif } +static void lb_sdhci_host( struct lb_header *header ) +{ + struct lb_sdhci_host_info *lb_host; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_host = (struct lb_sdhci_host_info *)lb_new_record(header); + + lb_host->tag = LB_TAG_SDHCI_HOST; + lb_host->size = sizeof(*lb_host); + + lb_host->initialized = host_ptr->initialized; + lb_host->quirks = host_ptr->quirks; + lb_host->host_caps = host_ptr->host_caps; + lb_host->version = host_ptr->version; + lb_host->clock = host_ptr->clock; + lb_host->clock_f_min = host_ptr->clock_f_min; + lb_host->clock_f_max = host_ptr->clock_f_max; + lb_host->clock_base = host_ptr->clock_base; + lb_host->removable = host_ptr->removable; + lb_host->voltages = host_ptr->voltages; + lb_host->dma64 = host_ptr->dma64; +} + +static void lb_mmc_media( struct lb_header *header ) +{ + struct lb_mmc_media_info *lb_mmc_media; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_mmc_media = (struct lb_mmc_media_info *)lb_new_record(header); + + lb_mmc_media->tag = LB_TAG_MMC_MEDIA; + lb_mmc_media->size = sizeof(*lb_mmc_media); + + lb_mmc_media->caps = host_ptr->mmc_ctrlr.media->caps; + lb_mmc_media->version = host_ptr->mmc_ctrlr.media->version; + lb_mmc_media->read_bl_len = host_ptr->mmc_ctrlr.media->read_bl_len; + lb_mmc_media->write_bl_len = host_ptr->mmc_ctrlr.media->write_bl_len; + lb_mmc_media->capacity = host_ptr->mmc_ctrlr.media->capacity; + lb_mmc_media->high_capacity = host_ptr->mmc_ctrlr.media->high_capacity; + lb_mmc_media->tran_speed = host_ptr->mmc_ctrlr.media->tran_speed; + lb_mmc_media->erase_size = host_ptr->mmc_ctrlr.media->erase_size; + lb_mmc_media->trim_mult = host_ptr->mmc_ctrlr.media->trim_mult; + lb_mmc_media->ocr = host_ptr->mmc_ctrlr.media->ocr; + lb_mmc_media->rca = host_ptr->mmc_ctrlr.media->rca; + lb_mmc_media->op_cond_response = host_ptr->mmc_ctrlr.media->op_cond_response; + + memcpy(&lb_mmc_media->scr[0],&host_ptr->mmc_ctrlr.media->scr[0],2); + memcpy(&lb_mmc_media->csd[0],&host_ptr->mmc_ctrlr.media->csd[0],4); + memcpy(&lb_mmc_media->cid[0],&host_ptr->mmc_ctrlr.media->cid[0],4); +} + +static void lb_mmc_ctrlr( struct lb_header *header ) +{ + struct lb_mmc_ctrlr_info *lb_mmc_ctrlr; + SdhciHost* host_ptr = sdhci_get_host_ptr(); + + lb_mmc_ctrlr = (struct lb_mmc_ctrlr_info *)lb_new_record(header); + + lb_mmc_ctrlr->tag = LB_TAG_MMC_CTRLR; + lb_mmc_ctrlr->size = sizeof(*lb_mmc_ctrlr); + + lb_mmc_ctrlr->voltages = host_ptr->mmc_ctrlr.voltages; + lb_mmc_ctrlr->f_min = host_ptr->mmc_ctrlr.f_min; + lb_mmc_ctrlr->f_max = host_ptr->mmc_ctrlr.f_max; + lb_mmc_ctrlr->bus_width = host_ptr->mmc_ctrlr.bus_width; + lb_mmc_ctrlr->bus_hz = host_ptr->mmc_ctrlr.bus_hz; + lb_mmc_ctrlr->caps = host_ptr->mmc_ctrlr.caps; + lb_mmc_ctrlr->b_max = host_ptr->mmc_ctrlr.b_max; + lb_mmc_ctrlr->timing = host_ptr->mmc_ctrlr.timing; + lb_mmc_ctrlr->hardcoded_voltage = host_ptr->mmc_ctrlr.hardcoded_voltage; +} void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count) @@ -534,6 +606,15 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_vboot_handoff(head); #endif + /* Add sdhci host information */ + lb_sdhci_host(head); + + /* Add mmc media information */ + lb_mmc_media(head); + + /* Add mmc ctrlr information */ + lb_mmc_ctrlr(head); + /* Add board ID if available */ lb_board_id(head);

1 0

Patch set updated for coreboot: WIP: Add coreboot storage driver
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18105 -gerrit commit e3d038da2da6cc6cb9deebf38a9c0cf9f375d983 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Fri Dec 9 11:40:51 2016 -0800 WIP: Add coreboot storage driver Port sdhci and mmc driver from depthcharge to coreboot. The purpose is to be able to start emmc initialization earlier in the boot process. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I2b96e0fabc5277529f6621ecd228fde83e619390 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/drivers/storage/Kconfig | 3 + src/drivers/storage/Makefile.inc | 5 + src/drivers/storage/mmc.c | 1072 ++++++++++++++++++++++++++++++++++ src/drivers/storage/mmc.h | 327 +++++++++++ src/drivers/storage/pci_sdhci.c | 104 ++++ src/drivers/storage/sdhci.c | 721 +++++++++++++++++++++++ src/drivers/storage/sdhci.h | 363 ++++++++++++ src/drivers/storage/storage_common.h | 28 + 8 files changed, 2623 insertions(+) diff --git a/src/drivers/storage/Kconfig b/src/drivers/storage/Kconfig new file mode 100644 index 0000000..9f980ad --- /dev/null +++ b/src/drivers/storage/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_STORAGE + bool + default n diff --git a/src/drivers/storage/Makefile.inc b/src/drivers/storage/Makefile.inc new file mode 100644 index 0000000..97d0d1f --- /dev/null +++ b/src/drivers/storage/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_DRIVERS_STORAGE),y) + +ramstage-y += sdhci.c mmc.c pci_sdhci.c + +endif diff --git a/src/drivers/storage/mmc.c b/src/drivers/storage/mmc.c new file mode 100644 index 0000000..4bcec20 --- /dev/null +++ b/src/drivers/storage/mmc.c @@ -0,0 +1,1072 @@ +/* + * Copyright 2008, Freescale Semiconductor, Inc + * Andy Fleming + * + * Copyright 2013 Google Inc. All rights reserved. + * + * Based vaguely on the Linux code + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <endian.h> +#include <stdint.h> +#include <string.h> +#include <delay.h> +#include <timer.h> + +#include "mmc.h" + +/* Set block count limit because of 16 bit register limit on some hardware*/ +#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 +#endif + +/* Set to 1 to turn on debug messages. */ +int32_t __mmc_debug = 0; +int32_t __mmc_trace = 0; + +int32_t mmc_busy_wait_io(volatile uint32_t *address, uint32_t *output, + uint32_t io_mask, uint32_t timeout_ms) +{ + uint32_t value = (uint32_t)-1; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout_ms); + + if (!output) + output = &value; + for (; *output & io_mask; *output = readl(address)) { + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) + return -1; + } + return 0; +} + +int32_t mmc_busy_wait_io_until(volatile uint32_t *address, uint32_t *output, + uint32_t io_mask, uint32_t timeout_ms) +{ + uint32_t value = 0; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout_ms); + + if (!output) + output = &value; + for (; !(*output & io_mask); *output = readl(address)) { + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) + return -1; + } + return 0; +} + +static uint64_t extract_uint32_bits(const uint32_t *array, int32_t start, int32_t count) +{ + int32_t i; + uint64_t value = 0; + + for (i = 0; i < count; i++, start++) { + value <<= 1; + value |= (array[start / 32] >> (31 - (start % 32))) & 0x1; + } + return value; +} + +static int32_t mmc_send_cmd(MmcCtrlr *ctrlr, MmcCommand *cmd, MmcData *data) +{ + int32_t ret = -1, retries = 2; + + mmc_trace("CMD_SEND:%d %p\n", cmd->cmdidx, ctrlr); + mmc_trace("\tARG\t\t\t %#8.8x\n", cmd->cmdarg); + mmc_trace("\tFLAG\t\t\t %d\n", cmd->flags); + if (data) { + mmc_trace("\t%s %d block(s) of %d bytes (%p)\n", + data->flags == MMC_DATA_READ ? "READ" : "WRITE", + data->blocks, + data->blocksize, + data->dest); + } + + while (retries--) { + ret = ctrlr->send_cmd(ctrlr, cmd, data); + + switch (cmd->resp_type) { + case MMC_RSP_NONE: + mmc_trace("\tMMC_RSP_NONE\n"); + break; + + case MMC_RSP_R1: + mmc_trace("\tMMC_RSP_R1,5,6,7 \t %#8.8x\n", + cmd->response[0]); + break; + + case MMC_RSP_R1b: + mmc_trace("\tMMC_RSP_R1b\t\t %#8.8x\n", + cmd->response[0]); + break; + + case MMC_RSP_R2: + mmc_trace("\tMMC_RSP_R2\t\t %#8.8x\n", + cmd->response[0]); + mmc_trace("\t \t\t %#8.8x\n", + cmd->response[1]); + mmc_trace("\t \t\t %#8.8x\n", + cmd->response[2]); + mmc_trace("\t \t\t %#8.8x\n", + cmd->response[3]); + break; + + case MMC_RSP_R3: + mmc_trace("\tMMC_RSP_R3,4\t\t %#8.8x\n", + cmd->response[0]); + break; + + default: + mmc_trace("\tERROR MMC rsp not supported\n"); + break; + } + mmc_trace("\trv:\t\t\t %d\n", ret); + + /* Retry failed commands, bail out otherwise. */ + if (!ret) + break; + } + return ret; +} + +static int32_t mmc_send_status(MmcMedia *media, ssize_t tries) +{ + MmcCommand cmd; + cmd.cmdidx = MMC_CMD_SEND_STATUS; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = media->rca << 16; + cmd.flags = 0; + + while (tries--) { + int32_t err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + else if (cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) + break; + else if (cmd.response[0] & MMC_STATUS_MASK) { + mmc_error("Status Error: %#8.8x\n", cmd.response[0]); + return MMC_COMM_ERR; + } + + udelay(100); + } + + mmc_trace("CURR STATE:%d\n", + (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9); + + if (tries < 0) { + mmc_error("Timeout waiting card ready\n"); + return MMC_TIMEOUT; + } + return 0; +} + +int32_t mmc_set_blocklen(MmcCtrlr *ctrlr, int32_t len) +{ + MmcCommand cmd; + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = len; + cmd.flags = 0; + + return mmc_send_cmd(ctrlr, &cmd, NULL); +} + +uint32_t mmc_write(MmcMedia *media, uint32_t start, lba_t block_count, + const void *src) +{ + MmcCommand cmd; + cmd.resp_type = MMC_RSP_R1; + cmd.flags = 0; + + if (block_count > 1) + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; + + if (media->high_capacity) + cmd.cmdarg = start; + else + cmd.cmdarg = start * media->write_bl_len; + + MmcData data; + data.src = src; + data.blocks = block_count; + data.blocksize = media->write_bl_len; + data.flags = MMC_DATA_WRITE; + + if (mmc_send_cmd(media->ctrlr, &cmd, &data)) { + mmc_error("mmc write failed\n"); + return 0; + } + + /* SPI multiblock writes terminate using a special + * token, not a STOP_TRANSMISSION request. + */ + if ((block_count > 1) && !(media->ctrlr->caps & MMC_AUTO_CMD12)) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + cmd.flags = 0; + if (mmc_send_cmd(media->ctrlr, &cmd, NULL)) { + mmc_error("mmc fail to send stop cmd\n"); + return 0; + } + + /* Waiting for the ready status */ + mmc_send_status(media, MMC_IO_RETRIES); + } + + return block_count; +} + +int32_t mmc_read(MmcMedia *media, void *dest, uint32_t start, + lba_t block_count) +{ + + MmcCommand cmd; + cmd.resp_type = MMC_RSP_R1; + cmd.flags = 0; + + if (block_count > 1) + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; + + if (media->high_capacity) + cmd.cmdarg = start; + else + cmd.cmdarg = start * media->read_bl_len; + + MmcData data; + data.dest = dest; + data.blocks = block_count; + data.blocksize = media->read_bl_len; + data.flags = MMC_DATA_READ; + + if (mmc_send_cmd(media->ctrlr, &cmd, &data)) + return 0; + + if ((block_count > 1) && !(media->ctrlr->caps & MMC_AUTO_CMD12)) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + cmd.flags = 0; + if (mmc_send_cmd(media->ctrlr, &cmd, NULL)) { + mmc_error("mmc fail to send stop cmd\n"); + return 0; + } + + /* Waiting for the ready status */ + mmc_send_status(media, MMC_IO_RETRIES); + } + + return block_count; +} + +static int32_t mmc_go_idle(MmcMedia *media,int removable) +{ + // Some cards can't accept idle commands without delay. + if (removable) + mdelay(1); + + MmcCommand cmd; + cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_NONE; + cmd.flags = 0; + + int32_t err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + // Some cards need more than half second to respond to next command (ex, + // SEND_OP_COND). + if (removable) + mdelay(2); + + return 0; +} + +static int32_t sd_send_op_cond(MmcMedia *media) +{ + int32_t err; + MmcCommand cmd; + + int32_t tries = MMC_IO_RETRIES; + while (tries--) { + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + cmd.flags = 0; + + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + + /* + * Most cards do not answer if some reserved bits + * in the ocr are set. However, Some controller + * can set bit 7 (reserved for low voltages), but + * how to manage low voltages SD card is not yet + * specified. + */ + cmd.cmdarg = (media->ctrlr->voltages & 0xff8000); + + if (media->version == SD_VERSION_2) + cmd.cmdarg |= OCR_HCS; + + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + // OCR_BUSY means "initialization complete". + if (cmd.response[0] & OCR_BUSY) + break; + + udelay(100); + } + if (tries < 0) + return MMC_UNUSABLE_ERR; + + if (media->version != SD_VERSION_2) + media->version = SD_VERSION_1_0; + + media->ocr = cmd.response[0]; + media->high_capacity = ((media->ocr & OCR_HCS) == OCR_HCS); + media->rca = 0; + return 0; +} + +/* We pass in the cmd since otherwise the init seems to fail */ +static int32_t mmc_send_op_cond_iter(MmcMedia *media, MmcCommand *cmd, int32_t use_arg) +{ + cmd->cmdidx = MMC_CMD_SEND_OP_COND; + cmd->resp_type = MMC_RSP_R3; + + if (use_arg) { + uint32_t mask = media->op_cond_response & + (OCR_VOLTAGE_MASK | OCR_ACCESS_MODE); + cmd->cmdarg = media->ctrlr->voltages & mask; + + if (media->ctrlr->caps & MMC_MODE_HC) + cmd->cmdarg |= OCR_HCS; + } + cmd->flags = 0; + int32_t err = mmc_send_cmd(media->ctrlr, cmd, NULL); + if (err) + return err; + + media->op_cond_response = cmd->response[0]; + return 0; +} + +static int32_t mmc_send_op_cond(MmcMedia *media,int removable) +{ + MmcCommand cmd; + int32_t max_iters; + int32_t i; + + /* Some cards seem to need this */ + mmc_go_idle(media,removable); + + /* Devices with hardcoded voltage do not need second iteration. */ + cmd.cmdarg = media->ctrlr->hardcoded_voltage; + max_iters = cmd.cmdarg ? 1 : 2; + + /* Ask the card for its capabilities unless required to be hardcoded. */ + for (i = 0; i < max_iters; i++) { + int32_t err = mmc_send_op_cond_iter(media, &cmd, i != 0); + if (err) + return err; + + // OCR_BUSY is active low, this bit set means + // "initialization complete". + if (media->op_cond_response & OCR_BUSY) + return 0; + } + return MMC_IN_PROGRESS; +} + +static int32_t mmc_complete_op_cond(MmcMedia *media) +{ + MmcCommand cmd; + + int32_t timeout = MMC_INIT_TIMEOUT_US_MS; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); + + while (1) { + // CMD1 queries whether initialization is done. + int32_t err = mmc_send_op_cond_iter(media, &cmd, 1); + if (err) + return err; + + // OCR_BUSY means "initialization complete". + if (media->op_cond_response & OCR_BUSY) + break; + + // Check if init timeout has expired. + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) + return MMC_UNUSABLE_ERR; + + udelay(100); + } + + media->version = MMC_VERSION_UNKNOWN; + media->ocr = cmd.response[0]; + + media->high_capacity = ((media->ocr & OCR_HCS) == OCR_HCS); + media->rca = 0; + return 0; +} + +static int32_t mmc_send_ext_csd(MmcCtrlr *ctrlr, unsigned char *ext_csd) +{ + int32_t rv; + /* Get the Card Status Register */ + MmcCommand cmd; + cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + cmd.flags = 0; + + MmcData data; + data.dest = (char *)ext_csd; + data.blocks = 1; + data.blocksize = 512; + data.flags = MMC_DATA_READ; + + rv = mmc_send_cmd(ctrlr, &cmd, &data); + + if (!rv && __mmc_trace) { + int32_t i, size; + + size = data.blocks * data.blocksize; + mmc_trace("\t%p ext_csd:", ctrlr); + for (i = 0; i < size; i++) { + if (!(i % 32)) + printk(BIOS_DEBUG,"\n"); + printk(BIOS_DEBUG," %2.2x", ext_csd[i]); + } + printk(BIOS_DEBUG,"\n"); + } + return rv; +} + +static int32_t mmc_switch(MmcMedia *media, uint8_t set, uint8_t index, + uint8_t value) +{ + MmcCommand cmd; + cmd.cmdidx = MMC_CMD_SWITCH; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = ((MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (index << 16) | (value << 8)); + cmd.flags = 0; + + int32_t ret = mmc_send_cmd(media->ctrlr, &cmd, NULL); + + /* Waiting for the ready status */ + mmc_send_status(media, MMC_IO_RETRIES); + return ret; + +} + +static void mmc_set_bus_width(MmcCtrlr *ctrlr, uint32_t width) +{ + ctrlr->bus_width = width; + ctrlr->set_ios(ctrlr); +} + +static void mmc_set_timing(MmcCtrlr *ctrlr, uint32_t timing) +{ + ctrlr->timing = timing; + ctrlr->set_ios(ctrlr); +} + +static int mmc_change_freq(MmcMedia *media) +{ + char cardtype; + int32_t err; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, 512); + + media->caps = 0; + + /* Only version 4 supports high-speed */ + if (media->version < MMC_VERSION_4) + return 0; + + err = mmc_send_ext_csd(media->ctrlr, ext_csd); + if (err) + return err; + + if (media->ctrlr->caps & MMC_MODE_HS_200MHz) + cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x1f; + else + cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; + + if (cardtype & MMC_HS_200MHZ) { + /* Switch to 8-bit since HS200 only support 8-bit bus width */ + err = mmc_switch(media, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8); + if (err) + return err; + + /* Switch to HS200 */ + err = mmc_switch(media, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_HS_TIMING, 0x2); + if (err) + return err; + + mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS200); + + /* Adjust Host Bus Wisth to 8-bit */ + mmc_set_bus_width(media->ctrlr, 8); + media->caps |= EXT_CSD_BUS_WIDTH_8; + } else { + err = mmc_switch(media, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_HS_TIMING, 1); + + if (!err) + mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS); + } + + if (err) + return err; + + /* Now check to see that it worked */ + err = mmc_send_ext_csd(media->ctrlr, ext_csd); + if (err) + return err; + + /* No high-speed support */ + if (!ext_csd[EXT_CSD_HS_TIMING]) + return 0; + + /* High Speed is set, there are types: HS200, 52MHz, 26MHz */ + if (cardtype & MMC_HS_200MHZ) + media->caps |= (MMC_MODE_HS_200MHz + | MMC_MODE_HS_52MHz | MMC_MODE_HS); + else if (cardtype & MMC_HS_52MHZ) + media->caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + else + media->caps |= MMC_MODE_HS; + return 0; +} + +static int32_t sd_switch(MmcCtrlr *ctrlr, int32_t mode, int32_t group, uint8_t value, + uint8_t *resp) +{ + /* Switch the frequency */ + MmcCommand cmd; + cmd.cmdidx = SD_CMD_SWITCH_FUNC; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = (mode << 31) | (0xffffff & ~(0xf << (group * 4))) | + (value << (group * 4)); + cmd.flags = 0; + + MmcData data; + data.dest = (char *)resp; + data.blocksize = 64; + data.blocks = 1; + data.flags = MMC_DATA_READ; + + return mmc_send_cmd(ctrlr, &cmd, &data); +} + +static int32_t sd_change_freq(MmcMedia *media) +{ + int32_t err, timeout; + MmcCommand cmd; + MmcData data; + ALLOC_CACHE_ALIGN_BUFFER(uint32_t, scr, 2); + ALLOC_CACHE_ALIGN_BUFFER(uint32_t, switch_status, 16); + + media->caps = 0; + + /* Read the SCR to find out if this card supports higher speeds */ + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = media->rca << 16; + cmd.flags = 0; + + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + mmc_debug("%s: before SD_CMD_APP_SEND_SCR\n", __func__); + cmd.cmdidx = SD_CMD_APP_SEND_SCR; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + cmd.flags = 0; + + timeout = 3; + while (timeout--) { + data.dest = (char *)scr; + data.blocksize = 8; + data.blocks = 1; + data.flags = MMC_DATA_READ; + err = mmc_send_cmd(media->ctrlr, &cmd, &data); + if (!err) + break; + } + if (err) { + mmc_error("%s: return err (%d).\n", __func__, err); + return err; + } + mmc_debug("%s: end SD_CMD_APP_SEND_SCR\n", __func__); + + media->scr[0] = be32toh(scr[0]); + media->scr[1] = be32toh(scr[1]); + + switch ((media->scr[0] >> 24) & 0xf) { + case 0: + media->version = SD_VERSION_1_0; + break; + case 1: + media->version = SD_VERSION_1_10; + break; + case 2: + media->version = SD_VERSION_2; + break; + default: + media->version = SD_VERSION_1_0; + break; + } + + if (media->scr[0] & SD_DATA_4BIT) + media->caps |= MMC_MODE_4BIT; + + /* Version 1.0 doesn't support switching */ + if (media->version == SD_VERSION_1_0) + return 0; + + timeout = 4; + while (timeout--) { + err = sd_switch(media->ctrlr, SD_SWITCH_CHECK, 0, 1, + (uint8_t *)switch_status); + if (err) + return err; + + /* The high-speed function is busy. Try again */ + if (!(ntohl(switch_status[7]) & SD_HIGHSPEED_BUSY)) + break; + } + + /* If high-speed isn't supported, we return */ + if (!(ntohl(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) + return 0; + + /* + * If the host doesn't support SD_HIGHSPEED, do not switch card to + * HIGHSPEED mode even if the card support SD_HIGHSPPED. + * This can avoid furthur problem when the card runs in different + * mode between the host. + */ + if (!((media->ctrlr->caps & MMC_MODE_HS_52MHz) && + (media->ctrlr->caps & MMC_MODE_HS))) + return 0; + + err = sd_switch(media->ctrlr, SD_SWITCH_SWITCH, 0, 1, + (uint8_t *)switch_status); + if (err) + return err; + + if ((ntohl(switch_status[4]) & 0x0f000000) == 0x01000000) { + media->caps |= MMC_MODE_HS; + mmc_set_timing(media->ctrlr, MMC_TIMING_SD_HS); + } + return 0; +} + +static void mmc_set_clock(MmcCtrlr *ctrlr, uint32_t clock) +{ + clock = MIN(clock, ctrlr->f_max); + clock = MAX(clock, ctrlr->f_min); + + ctrlr->bus_hz = clock; + ctrlr->set_ios(ctrlr); +} + +static uint32_t mmc_calculate_transfer_speed(uint32_t csd0) +{ + uint32_t mult, freq; + + /* frequency bases, divided by 10 to be nice to platforms without + * floating point */ + static const int32_t fbase[] = { + 10000, + 100000, + 1000000, + 10000000, + }; + /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice + * to platforms without floating point. */ + static const int32_t multipliers[] = { + 0, // reserved + 10, + 12, + 13, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 70, + 80, + }; + + /* divide frequency by 10, since the mults are 10x bigger */ + freq = fbase[csd0 & 0x7]; + mult = multipliers[(csd0 >> 3) & 0xf]; + return freq * mult; +} + +static int32_t mmc_startup(MmcMedia *media) +{ + int32_t err, width; + uint64_t cmult, csize, capacity; + uint32_t clock = MMC_CLOCK_DEFAULT_MHZ; + + MmcCommand cmd; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, EXT_CSD_SIZE); + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, test_csd, EXT_CSD_SIZE); + + /* Put the Card in Identify Mode */ + cmd.cmdidx = MMC_CMD_ALL_SEND_CID; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = 0; + cmd.flags = 0; + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + memcpy(media->cid, cmd.response, sizeof(media->cid)); + + /* + * For MMC cards, set the Relative Address. + * For SD cards, get the Relatvie Address. + * This also puts the cards into Standby State + */ + cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; + cmd.cmdarg = media->rca << 16; + cmd.resp_type = MMC_RSP_R6; + cmd.flags = 0; + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + if (IS_SD(media)) + media->rca = (cmd.response[0] >> 16) & 0xffff; + + /* Get the Card-Specific Data */ + cmd.cmdidx = MMC_CMD_SEND_CSD; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = media->rca << 16; + cmd.flags = 0; + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + + /* Waiting for the ready status */ + mmc_send_status(media, MMC_IO_RETRIES); + if (err) + return err; + + memcpy(media->csd, cmd.response, sizeof(media->csd)); + if (media->version == MMC_VERSION_UNKNOWN) { + int32_t version = extract_uint32_bits(media->csd, 2, 4); + switch (version) { + case 0: + media->version = MMC_VERSION_1_2; + break; + case 1: + media->version = MMC_VERSION_1_4; + break; + case 2: + media->version = MMC_VERSION_2_2; + break; + case 3: + media->version = MMC_VERSION_3; + break; + case 4: + media->version = MMC_VERSION_4; + break; + default: + media->version = MMC_VERSION_1_2; + break; + } + } + + media->tran_speed = mmc_calculate_transfer_speed(media->csd[0]); + media->read_bl_len = 1 << extract_uint32_bits(media->csd, 44, 4); + + if (IS_SD(media)) + media->write_bl_len = media->read_bl_len; + else + media->write_bl_len = + 1 << extract_uint32_bits(media->csd, 102, 4); + + if (media->high_capacity) { + cmult = 8; + csize = extract_uint32_bits(media->csd, 58, 22); + + } else { + csize = extract_uint32_bits(media->csd, 54, 12); + cmult = extract_uint32_bits(media->csd, 78, 3); + } + + media->capacity = (csize + 1) << (cmult + 2); + media->capacity *= media->read_bl_len; + + if (media->read_bl_len > 512) + media->read_bl_len = 512; + + if (media->write_bl_len > 512) + media->write_bl_len = 512; + + mmc_debug("mmc media info: version=%#x, tran_speed=%d\n", + media->version, (int32_t)media->tran_speed); + + /* Select the card, and put it into Transfer Mode */ + cmd.cmdidx = MMC_CMD_SELECT_CARD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = media->rca << 16; + cmd.flags = 0; + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + + if (err) + return err; + + if (!IS_SD(media) && (media->version >= MMC_VERSION_4)) { + /* check ext_csd version and capacity */ + err = mmc_send_ext_csd(media->ctrlr, ext_csd); + if (!err & (ext_csd[EXT_CSD_REV] >= 2)) { + /* According to the JEDEC Standard, the value of + * ext_csd's capacity is valid if the value is more + * than 2GB */ + // TODO(hungte) Replace by letohl(). + capacity = (ext_csd[EXT_CSD_SEC_CNT + 0] << 0 | + ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | + ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | + ext_csd[EXT_CSD_SEC_CNT + 3] << 24); + capacity *= 512; + + if ((capacity >> 20) > 2 * 1024) + media->capacity = capacity; + } + } + + if (IS_SD(media)) + err = sd_change_freq(media); + else + err = mmc_change_freq(media); + if (err) + return err; + + /* Restrict card's capabilities by what the host can do */ + media->caps &= media->ctrlr->caps; + + if (IS_SD(media)) { + if (media->caps & MMC_MODE_4BIT) { + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = media->rca << 16; + cmd.flags = 0; + + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 2; + cmd.flags = 0; + err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + mmc_set_bus_width(media->ctrlr, 4); + } + + if (media->caps & MMC_MODE_HS) + clock = MMC_CLOCK_50MHZ; + else + clock = MMC_CLOCK_25MHZ; + } else { + for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width--) { + /* If HS200 is switched, Bus Width has been 8-bit */ + if (media->caps & MMC_MODE_HS_200MHz) + break; + + /* Set the card to use 4 bit*/ + err = mmc_switch(media, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, width); + if (err) + continue; + + if (!width) { + mmc_set_bus_width(media->ctrlr, 1); + break; + } else + mmc_set_bus_width(media->ctrlr, 4 * width); + + err = mmc_send_ext_csd(media->ctrlr, test_csd); + if (!err && + (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] == + test_csd[EXT_CSD_PARTITIONING_SUPPORT]) && + (ext_csd[EXT_CSD_ERASE_GROUP_DEF] == + test_csd[EXT_CSD_ERASE_GROUP_DEF]) && + (ext_csd[EXT_CSD_REV] == + test_csd[EXT_CSD_REV]) && + (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] == + test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) && + memcmp(&ext_csd[EXT_CSD_SEC_CNT], + &test_csd[EXT_CSD_SEC_CNT], 4) == 0) { + media->caps |= width; + break; + } + } + + if (media->caps & MMC_MODE_HS) { + if (media->caps & MMC_MODE_HS_200MHz) + clock = MMC_CLOCK_200MHZ; + else if (media->caps & MMC_MODE_HS_52MHz) + clock = MMC_CLOCK_52MHZ; + else + clock = MMC_CLOCK_26MHZ; + } + } + mmc_set_clock(media->ctrlr, clock); + + printk(BIOS_DEBUG,"Man %06x Snr %u ", + media->cid[0] >> 24, + (((media->cid[2] & 0xffff) << 16) | + ((media->cid[3] >> 16) & 0xffff))); + printk(BIOS_DEBUG,"Product %c%c%c%c", media->cid[0] & 0xff, + (media->cid[1] >> 24), (media->cid[1] >> 16) & 0xff, + (media->cid[1] >> 8) & 0xff); + if (!IS_SD(media)) /* eMMC product string is longer */ + printk(BIOS_DEBUG,"%c%c", media->cid[1] & 0xff, + (media->cid[2] >> 24) & 0xff); + printk(BIOS_DEBUG," Revision %d.%d\n", (media->cid[2] >> 20) & 0xf, + (media->cid[2] >> 16) & 0xf); + + /* Check whether to use HC erase group size or not. */ + if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x1) + media->erase_size = ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * + 512 * KiB; + else + media->erase_size = (extract_uint32_bits(media->csd, 81, 5) + + 1) * + (extract_uint32_bits(media->csd, 86, 5) + 1); + + media->trim_mult = ext_csd[EXT_CSD_TRIM_MULT]; + + return 0; +} + +static int32_t mmc_send_if_cond(MmcMedia *media) +{ + MmcCommand cmd; + cmd.cmdidx = SD_CMD_SEND_IF_COND; + // Set if host supports voltages between 2.7 and 3.6 V. + cmd.cmdarg = ((media->ctrlr->voltages & 0xff8000) != 0) << 8 | 0xaa; + cmd.resp_type = MMC_RSP_R7; + cmd.flags = 0; + int32_t err = mmc_send_cmd(media->ctrlr, &cmd, NULL); + if (err) + return err; + + if ((cmd.response[0] & 0xff) != 0xaa) + return MMC_UNUSABLE_ERR; + else + media->version = SD_VERSION_2; + return 0; +} + +int32_t mmc_setup_media(MmcCtrlr *ctrlr,int removable) +{ + int32_t err; + MmcMedia *media = malloc(sizeof(*media)); + memset(media,0,sizeof(*media)); + + media->ctrlr = ctrlr; + + mmc_set_bus_width(ctrlr, 1); + mmc_set_clock(ctrlr, 1); + + /* Reset the Card */ + err = mmc_go_idle(media,removable); + if (err) { + free(media); + return err; + } + + /* Test for SD version 2 */ + err = mmc_send_if_cond(media); + + /* Get SD card operating condition */ + err = sd_send_op_cond(media); + + /* If the command timed out, we check for an MMC card */ + if (err == MMC_TIMEOUT) { + err = mmc_send_op_cond(media,removable); + + if (err && err != MMC_IN_PROGRESS) { + mmc_error("Card did not respond to voltage select!\n"); + free(media); + return MMC_UNUSABLE_ERR; + } + } + + if (err && err != MMC_IN_PROGRESS) { + free(media); + return err; + } + + if (err == MMC_IN_PROGRESS) + err = mmc_complete_op_cond(media); + + if (!err) { + err = mmc_startup(media); + if (!err) { + ctrlr->media = media; + return 0; + } + } + + free(media); + return err; +} diff --git a/src/drivers/storage/mmc.h b/src/drivers/storage/mmc.h new file mode 100644 index 0000000..54c26f2 --- /dev/null +++ b/src/drivers/storage/mmc.h @@ -0,0 +1,327 @@ +/* + * Copyright 2008,2010 Freescale Semiconductor, Inc + * Andy Fleming + * + * Copyright 2013 Google Inc. All rights reserved. + * + * Based (loosely) on the Linux code + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_STORAGE_MMC_H__ +#define __DRIVERS_STORAGE_MMC_H__ + +#include "storage_common.h" + +#define SD_VERSION_SD 0x20000 +#define SD_VERSION_2 (SD_VERSION_SD | 0x20) +#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) +#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a) +#define MMC_VERSION_MMC 0x10000 +#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) +#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12) +#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14) +#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22) +#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30) +#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40) + +#define MMC_MODE_HS 0x001 +#define MMC_MODE_HS_52MHz 0x010 +#define MMC_MODE_HS_200MHz 0x020 +#define MMC_MODE_HS400 0x040 +#define MMC_MODE_HS400ES 0x080 +#define MMC_MODE_1V8_VDD 0x100 +#define MMC_MODE_4BIT 0x200 +#define MMC_MODE_8BIT 0x400 +#define MMC_MODE_SPI 0x800 +#define MMC_MODE_HC 0x1000 +#define MMC_AUTO_CMD12 0x2000 + +#define SD_DATA_4BIT 0x00040000 + +#define IS_SD(x) (x->version & SD_VERSION_SD) + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +#define MMC_SUPPORT_ERR -15 /* No support feature */ +#define MMC_NO_CARD_ERR -16 /* No SD/MMC card inserted */ +#define MMC_UNUSABLE_ERR -17 /* Unusable Card */ +#define MMC_COMM_ERR -18 /* Communications Error */ +#define MMC_TIMEOUT -19 +#define MMC_IN_PROGRESS -20 /* operation is in progress */ +#define MMC_INVALID_ERR -21 /* A catch all case. */ + +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_ERASE_GROUP_START 35 +#define MMC_CMD_ERASE_GROUP_END 36 +#define MMC_CMD_ERASE 38 +#define MMC_CMD_APP_CMD 55 +#define MMC_CMD_SPI_READ_OCR 58 +#define MMC_CMD_SPI_CRC_ON_OFF 59 + +#define MMC_TRIM_ARG 0x1 +#define MMC_SECURE_ERASE_ARG 0x80000000 + +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SEND_IF_COND 8 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +/* SCR definitions in different words */ +#define SD_HIGHSPEED_BUSY 0x00020000 +#define SD_HIGHSPEED_SUPPORTED 0x00020000 + +#define MMC_HS_TIMING 0x00000100 +#define MMC_HS_52MHZ 0x2 +#define MMC_HS_200MHZ 0x10 +#define MMC_HS400 0x40 + +#define OCR_BUSY 0x80000000 +#define OCR_HCS 0x40000000 +#define OCR_VOLTAGE_MASK 0x007FFF80 +#define OCR_ACCESS_MODE 0x60000000 + +#define SECURE_ERASE 0x80000000 + +#define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_CURR_STATE (0xf << 9) +#define MMC_STATUS_ERROR (1 << 19) + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_VDD_165_195_SHIFT 7 + +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte + addressed by index which are + 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte + addressed by index, which are + 1 in value field */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ +#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_PART_CONF 179 /* R/W */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_TRIM_MULT 232 /* RO */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_CMD_SET_NORMAL (1 << 0) +#define EXT_CSD_CMD_SET_SECURE (1 << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) + +#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */ + +#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ +#define EXT_CSD_TIMING_HS 1 /* High speed */ +#define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ + MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + +#define MMC_INIT_TIMEOUT_US_MS 1000 +#define MMC_IO_RETRIES (1000) +#define MMC_CLOCK_20MHZ (20000000) +#define MMC_CLOCK_25MHZ (25000000) +#define MMC_CLOCK_26MHZ (26000000) +#define MMC_CLOCK_50MHZ (50000000) +#define MMC_CLOCK_52MHZ (52000000) +#define MMC_CLOCK_200MHZ (200000000) +#define MMC_CLOCK_DEFAULT_MHZ (MMC_CLOCK_20MHZ) + +#define EXT_CSD_SIZE (512) + +typedef struct MmcCommand { + uint16_t cmdidx; + uint32_t resp_type; + uint32_t cmdarg; + uint32_t response[4]; + uint32_t flags; +} MmcCommand; + +typedef struct MmcData { + union { + char *dest; + const char *src; + }; + uint32_t flags; + uint32_t blocks; + uint32_t blocksize; +} MmcData; + +struct MmcMedia; +typedef struct MmcMedia MmcMedia; + +typedef struct MmcCtrlr { + MmcMedia *media; + + uint32_t voltages; + uint32_t f_min; + uint32_t f_max; + uint32_t bus_width; + uint32_t bus_hz; + uint32_t caps; + uint32_t b_max; + uint32_t timing; + +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 +#define MMC_TIMING_MMC_HS400 10 + + /* + * Some eMMC devices do not support iterative OCR setting, they need + * to be programmed with the required/expected value. This field is + * used to set the value for those devices. + */ + uint32_t hardcoded_voltage; + + int (*send_cmd)(struct MmcCtrlr *me, MmcCommand *cmd, MmcData *data); + void (*set_ios)(struct MmcCtrlr *me); +} MmcCtrlr; + +typedef struct MmcMedia { + MmcCtrlr *ctrlr; + + uint32_t caps; + uint32_t version; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint64_t capacity; + int high_capacity; + uint32_t tran_speed; + /* Erase size in terms of block length. */ + uint32_t erase_size; + /* Trim operation multiplier for determining timeout. */ + uint32_t trim_mult; + + uint32_t ocr; + uint16_t rca; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + + uint32_t op_cond_response; // The response byte from the last op_cond +} MmcMedia; + +int mmc_busy_wait_io(volatile uint32_t *address, uint32_t *output, + uint32_t io_mask, uint32_t timeout_ms); +int mmc_busy_wait_io_until(volatile uint32_t *address, uint32_t *output, + uint32_t io_mask, uint32_t timeout_ms); +uint32_t mmc_write(MmcMedia *media, uint32_t start, lba_t block_count, + const void *src); +int32_t mmc_read(MmcMedia *media, void *dest, uint32_t start, + lba_t block_count); +int32_t mmc_set_blocklen(MmcCtrlr *ctrlr, int32_t len); + +int mmc_setup_media(MmcCtrlr *ctrlr,int removable); + +// Debug functions. +extern int __mmc_debug, __mmc_trace; +#define mmc_debug(format...) \ + while (__mmc_debug) { printk(BIOS_DEBUG,"mmc: " format); break; } +#define mmc_trace(format...) \ + while (__mmc_trace) { printk(BIOS_DEBUG,format); break; } +#define mmc_error(format...) printk(BIOS_DEBUG,"mmc: ERROR: " format) + +#endif /* __DRIVERS_STORAGE_MMC_H__ */ diff --git a/src/drivers/storage/pci_sdhci.c b/src/drivers/storage/pci_sdhci.c new file mode 100644 index 0000000..baf2588 --- /dev/null +++ b/src/drivers/storage/pci_sdhci.c @@ -0,0 +1,104 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <string.h> + +#include "storage_common.h" +#include "sdhci.h" + + +typedef struct { + SdhciHost sdhci_host; + struct device* sdhci_dev; + char dev_name[0x20]; +} PciSdhciHost; + +PciSdhciHost *gHostPtr; + +/* Discover the register file address of the PCI SDHCI device. */ +static int attach_device(SdhciHost *host) +{ + PciSdhciHost *pci_host; + uint32_t addr; + + pci_host = container_of(host, PciSdhciHost, sdhci_host); + addr = pci_read_config32(pci_host->sdhci_dev, PCI_BASE_ADDRESS_0); + + if (addr == ((uint32_t)~0)) { + printk(BIOS_DEBUG,"%s: Error: %s not found\n", + __func__, pci_host->dev_name); + return -1; + } + + host->ioaddr = (void *) (addr & ~0xf); + + return 0; +} + +/* Initialize an HDHCI port */ +SdhciHost *new_pci_sdhci_host(struct device* dev, int platform_info, + int clock_min, int clock_max) +{ + PciSdhciHost *host; + int removable = platform_info & SDHCI_PLATFORM_REMOVABLE; + + host = malloc(sizeof(*host)); + memset(host,0,sizeof(*host)); + + gHostPtr = host; + + host->sdhci_dev = dev; + host->sdhci_host.quirks = SDHCI_QUIRK_NO_HISPD_BIT | + SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER; + + if (platform_info & SDHCI_PLATFORM_NO_EMMC_HS200) + host->sdhci_host.quirks |= SDHCI_QUIRK_NO_EMMC_HS200; + + if (platform_info & SDHCI_PLATFORM_EMMC_1V8_POWER) + host->sdhci_host.quirks |= SDHCI_QUIRK_EMMC_1V8_POWER; + + host->sdhci_host.attach = attach_device; + host->sdhci_host.clock_f_min = clock_min; + host->sdhci_host.clock_f_max = clock_max; + host->sdhci_host.removable = removable; + + if (!removable) + /* + * The value translates to 'block access mode, supporting + * 1.7..1.95 and 2.7..3.6 voltage ranges, which is typical for + * eMMC devices. + */ + host->sdhci_host.mmc_ctrlr.hardcoded_voltage = 0x40ff8080; + + /* + * Need to program host->ioaddr for SD/MMC read/write operation + */ + attach_device(&host->sdhci_host); + + add_sdhci(&host->sdhci_host); + + return &host->sdhci_host; +} + +SdhciHost* sdhci_get_host_ptr( void ) +{ + return &gHostPtr->sdhci_host; +} + diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c new file mode 100644 index 0000000..54cc54d --- /dev/null +++ b/src/drivers/storage/sdhci.c @@ -0,0 +1,721 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen <leiwen(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen(a)cmst.csiro.au, 27-Jan-01. + */ + +#include "mmc.h" +#include "sdhci.h" + +#include <delay.h> +#include <assert.h> +#include <endian.h> +#include <stdint.h> +#include <timer.h> +#include <string.h> + +static void sdhci_reset(SdhciHost *host, u8 mask) +{ + unsigned long timeout; + struct mono_time current, end; + + /* Wait max 100 ms */ + timeout = 100; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout); + + + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) { + printk(BIOS_DEBUG,"Reset 0x%x never completed.\n", (int)mask); + return; + } + udelay(1000); + } +} + +static void sdhci_cmd_done(SdhciHost *host, MmcCommand *cmd) +{ + int i; + if (cmd->resp_type & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + cmd->response[i] = sdhci_readl(host, + SDHCI_RESPONSE + (3-i)*4) << 8; + if (i != 3) + cmd->response[i] |= sdhci_readb(host, + SDHCI_RESPONSE + (3-i)*4-1); + } + } else { + cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); + } +} + +static void sdhci_transfer_pio(SdhciHost *host, MmcData *data) +{ + int i; + char *offs; + for (i = 0; i < data->blocksize; i += 4) { + offs = data->dest + i; + if (data->flags == MMC_DATA_READ) + *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); + else + sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); + } +} + +static int sdhci_transfer_data(SdhciHost *host, MmcData *data, + unsigned int start_addr) +{ + unsigned int stat, rdy, mask, timeout, block = 0; + + timeout = 1000000; + rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; + mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; + do { + stat = sdhci_readl(host, SDHCI_INT_STATUS); + if (stat & SDHCI_INT_ERROR) { + printk(BIOS_DEBUG,"Error detected in status(0x%X)!\n", stat); + return -1; + } + if (stat & rdy) { + if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) + continue; + sdhci_writel(host, rdy, SDHCI_INT_STATUS); + sdhci_transfer_pio(host, data); + data->dest += data->blocksize; + if (++block >= data->blocks) + break; + } + if (timeout-- > 0) + udelay(10); + else { + printk(BIOS_DEBUG,"Transfer data timeout\n"); + return -1; + } + } while (!(stat & SDHCI_INT_DATA_END)); + return 0; +} + +static void sdhci_alloc_adma_descs(SdhciHost *host, u32 need_descriptors) +{ + if (host->adma_descs) { + if (host->adma_desc_count < need_descriptors) { + /* Previously allocated array is too small */ + free(host->adma_descs); + host->adma_desc_count = 0; + host->adma_descs = NULL; + } + } + + if (!host->adma_descs) { + host->adma_descs = malloc(need_descriptors * + sizeof(*host->adma_descs)); + if (host->adma_descs == NULL) + die("fail to malloc adma_descs\n"); + host->adma_desc_count = need_descriptors; + } + + memset(host->adma_descs, 0, sizeof(*host->adma_descs) * + need_descriptors); +} + +static void sdhci_alloc_adma64_descs(SdhciHost *host, u32 need_descriptors) +{ + if (host->adma64_descs) { + if (host->adma_desc_count < need_descriptors) { + /* Previously allocated array is too small */ + free(host->adma64_descs); + host->adma_desc_count = 0; + host->adma64_descs = NULL; + } + } + + if (!host->adma64_descs) { + host->adma64_descs = malloc(need_descriptors * + sizeof(*host->adma64_descs)); + if (host->adma64_descs == NULL) + die("fail to malloc adma64_descs\n"); + + host->adma_desc_count = need_descriptors; + } + + memset(host->adma64_descs, 0, sizeof(*host->adma64_descs) * + need_descriptors); +} + +static int sdhci_setup_adma(SdhciHost *host, MmcData *data) +{ + int i, togo, need_descriptors; + char *buffer_data; + u16 attributes; + + togo = data->blocks * data->blocksize; + if (!togo) { + printk(BIOS_DEBUG,"%s: MmcData corrupted: %d blocks of %d bytes\n", + __func__, data->blocks, data->blocksize); + return -1; + } + + need_descriptors = 1 + togo / SDHCI_MAX_PER_DESCRIPTOR; + + if (host->dma64) + sdhci_alloc_adma64_descs(host, need_descriptors); + else + sdhci_alloc_adma_descs(host, need_descriptors); + + buffer_data = data->dest; + + /* Now set up the descriptor chain. */ + for (i = 0; togo; i++) { + unsigned desc_length; + + if (togo < SDHCI_MAX_PER_DESCRIPTOR) + desc_length = togo; + else + desc_length = SDHCI_MAX_PER_DESCRIPTOR; + togo -= desc_length; + + attributes = SDHCI_ADMA_VALID | SDHCI_ACT_TRAN; + if (togo == 0) + attributes |= SDHCI_ADMA_END; + + if (host->dma64) { + host->adma64_descs[i].addr = (uintptr_t) buffer_data; + host->adma64_descs[i].addr_hi = 0; + host->adma64_descs[i].length = desc_length; + host->adma64_descs[i].attributes = attributes; + + } else { + host->adma_descs[i].addr = (uintptr_t) buffer_data; + host->adma_descs[i].length = desc_length; + host->adma_descs[i].attributes = attributes; + } + + buffer_data += desc_length; + } + + if (host->dma64) + sdhci_writel(host, (uintptr_t) host->adma64_descs, + SDHCI_ADMA_ADDRESS); + else + sdhci_writel(host, (uintptr_t) host->adma_descs, + SDHCI_ADMA_ADDRESS); + + return 0; +} + +static int sdhci_complete_adma(SdhciHost *host, MmcCommand *cmd) +{ + int retry; + u32 stat = 0, mask; + + mask = SDHCI_INT_RESPONSE | SDHCI_INT_ERROR; + + retry = 10000; /* Command should be done in way less than 10 ms. */ + while (--retry) { + stat = sdhci_readl(host, SDHCI_INT_STATUS); + if (stat & mask) + break; + udelay(1); + } + + sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); + + if (retry && !(stat & SDHCI_INT_ERROR)) { + /* Command OK, let's wait for data transfer completion. */ + mask = SDHCI_INT_DATA_END | + SDHCI_INT_ERROR | SDHCI_INT_ADMA_ERROR; + + /* Transfer should take 10 seconds tops. */ + retry = 10 * 1000 * 1000; + while (--retry) { + stat = sdhci_readl(host, SDHCI_INT_STATUS); + if (stat & mask) + break; + udelay(1); + } + + sdhci_writel(host, stat, SDHCI_INT_STATUS); + if (retry && !(stat & SDHCI_INT_ERROR)) { + sdhci_cmd_done(host, cmd); + return 0; + } + } + + printk(BIOS_DEBUG,"%s: transfer error, stat %#x, adma error %#x, retry %d\n", + __func__, stat, sdhci_readl(host, SDHCI_ADMA_ERROR), retry); + + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + + if (stat & SDHCI_INT_TIMEOUT) + return MMC_TIMEOUT; + else + return MMC_COMM_ERR; +} + +static int sdhci_send_command_bounced(MmcCtrlr *mmc_ctrl, MmcCommand *cmd, + MmcData *data) +{ + unsigned int stat = 0; + int ret = 0; + u32 mask, flags; + unsigned int timeout, start_addr = 0; + struct mono_time current, end; + SdhciHost *host = container_of(mmc_ctrl, SdhciHost, mmc_ctrlr); + + /* Wait max 1 s */ + timeout = 1000; + + sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); + mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; + + /* We shouldn't wait for data inihibit for stop commands, even + though they might use busy signaling */ + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + mask &= ~SDHCI_DATA_INHIBIT; + + while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { + if (timeout == 0) { + printk(BIOS_DEBUG,"Controller never released inhibit bit(s), " + "present state %#8.8x.\n", + sdhci_readl(host, SDHCI_PRESENT_STATE)); + return MMC_COMM_ERR; + } + timeout--; + udelay(1000); + } + + mask = SDHCI_INT_RESPONSE; + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->resp_type & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->resp_type & MMC_RSP_BUSY) { + flags = SDHCI_CMD_RESP_SHORT_BUSY; + mask |= SDHCI_INT_DATA_END; + } else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->resp_type & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + if (data) + flags |= SDHCI_CMD_DATA; + + /* Set Transfer mode regarding to data flag */ + if (data) { + u16 mode = 0; + + sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, + data->blocksize), + SDHCI_BLOCK_SIZE); + + if (data->flags == MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; + + if (data->blocks > 1) + mode |= SDHCI_TRNS_BLK_CNT_EN | + SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12; + + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + if (host->host_caps & MMC_AUTO_CMD12) { + if (sdhci_setup_adma(host, data)) + return -1; + + mode |= SDHCI_TRNS_DMA; + } + sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); + } + + sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); + sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); + + if (data && (host->host_caps & MMC_AUTO_CMD12)) + return sdhci_complete_adma(host, cmd); + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, 2550); + + do { + stat = sdhci_readl(host, SDHCI_INT_STATUS); + if (stat & SDHCI_INT_ERROR) + break; + timer_monotonic_get(&current); + /* Apply max timeout for R1b-type CMD defined in eMMC ext_csd + except for erase ones */ + if (mono_time_after(&current, &end)) { + if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) + return 0; + else { + printk(BIOS_DEBUG,"Timeout for status update!\n"); + return MMC_TIMEOUT; + } + } + } while ((stat & mask) != mask); + + if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { + sdhci_cmd_done(host, cmd); + sdhci_writel(host, mask, SDHCI_INT_STATUS); + } else + ret = -1; + + if (!ret && data) + ret = sdhci_transfer_data(host, data, start_addr); + + if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) + udelay(1000); + + stat = sdhci_readl(host, SDHCI_INT_STATUS); + sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); + + if (!ret) + return 0; + + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + if (stat & SDHCI_INT_TIMEOUT) + return MMC_TIMEOUT; + else + return MMC_COMM_ERR; +} + +static int sdhci_send_command(MmcCtrlr *mmc_ctrl, MmcCommand *cmd, + MmcData *data) +{ + void *buf; + size_t len; + int ret; + + if (data) { + if (data->flags & MMC_DATA_READ) { + buf = data->dest; + } else { + buf = (void *)data->src; + } + len = data->blocks * data->blocksize; + } + + ret = sdhci_send_command_bounced(mmc_ctrl, cmd, data); + + return ret; +} + +static int sdhci_set_clock(SdhciHost *host, unsigned int clock) +{ + unsigned int div, clk, timeout; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return 0; + + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { + /* Version 3.00 divisors must be a multiple of 2. */ + if (host->clock_base <= clock) + div = 1; + else { + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { + if ((host->clock_base / div) <= clock) + break; + } + } + } else { + /* Version 2.00 divisors must be a power of 2. */ + for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { + if ((host->clock_base / div) <= clock) + break; + } + } + div >>= 1; + + if (host->set_clock) + host->set_clock(host, div); + + if (clock == MMC_CLOCK_200MHZ) { + sdhci_writew(host, SDHCI_CTRL_UHS_SDR104 + | SDHCI_CTRL_VDD_180 | SDHCI_CTRL_DRV_TYPE_A + , SDHCI_HOST_CONTROL2); + } + clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) + << SDHCI_DIVIDER_HI_SHIFT; + clk |= SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = 20; + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + printk(BIOS_DEBUG,"Internal clock never stabilised.\n"); + return -1; + } + timeout--; + udelay(1000); + } + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + return 0; +} + +/* Find leftmost set bit in a 32 bit integer */ +static int fls(u32 x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +static void sdhci_set_power(SdhciHost *host, unsigned short power) +{ + u8 pwr = 0; + + if (power != (unsigned short)-1) { + switch (1 << power) { + case MMC_VDD_165_195: + pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + pwr = SDHCI_POWER_330; + break; + } + } + + if (pwr == 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + return; + } + + if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + + pwr |= SDHCI_POWER_ON; + + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); +} + +static void sdhci_set_ios(MmcCtrlr *mmc_ctrlr) +{ + u32 ctrl; + SdhciHost *host = container_of(mmc_ctrlr, + SdhciHost, mmc_ctrlr); + if (host->set_control_reg) + host->set_control_reg(host); + if (mmc_ctrlr->bus_hz != host->clock) + sdhci_set_clock(host, mmc_ctrlr->bus_hz); + /* Switch to 1.8 volt for HS200 */ + if (mmc_ctrlr->caps & MMC_MODE_1V8_VDD) + if (mmc_ctrlr->bus_hz == MMC_CLOCK_200MHZ) + sdhci_set_power(host, MMC_VDD_165_195_SHIFT); + /* Set bus width */ + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (mmc_ctrlr->bus_width == 8) { + ctrl &= ~SDHCI_CTRL_4BITBUS; + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + ctrl |= SDHCI_CTRL_8BITBUS; + } else { + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + ctrl &= ~SDHCI_CTRL_8BITBUS; + if (mmc_ctrlr->bus_width == 4) + ctrl |= SDHCI_CTRL_4BITBUS; + else + ctrl &= ~SDHCI_CTRL_4BITBUS; + } + if (mmc_ctrlr->bus_hz > 26000000) + ctrl |= SDHCI_CTRL_HISPD; + else + ctrl &= ~SDHCI_CTRL_HISPD; + + if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) + ctrl &= ~SDHCI_CTRL_HISPD; + + if (host->host_caps & MMC_AUTO_CMD12) { + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (host->dma64) + ctrl |= SDHCI_CTRL_ADMA64; + else + ctrl |= SDHCI_CTRL_ADMA32; + } + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + +/* Prepare SDHCI controller to be initialized */ +static int sdhci_pre_init(SdhciHost *host) +{ + unsigned int caps; + + if (host->attach) { + int rv = host->attach(host); + if (rv) + return rv; + } + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION) & 0xff; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + + if (caps & SDHCI_CAN_DO_ADMA2) + host->host_caps |= MMC_AUTO_CMD12; + + /* get base clock frequency from CAP register */ + if (!(host->quirks & SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN)) { + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + host->clock_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) + >> SDHCI_CLOCK_BASE_SHIFT; + else + host->clock_base = (caps & SDHCI_CLOCK_BASE_MASK) + >> SDHCI_CLOCK_BASE_SHIFT; + } + + if (host->clock_base == 0) { + printk(BIOS_DEBUG,"Hardware doesn't specify base clock frequency\n"); + return -1; + } + + host->clock_base *= 1000000; + + if (host->clock_f_max) + host->mmc_ctrlr.f_max = host->clock_f_max; + else + host->mmc_ctrlr.f_max = host->clock_base; + + if (host->clock_f_min) { + host->mmc_ctrlr.f_min = host->clock_f_min; + } else { + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + host->mmc_ctrlr.f_min = + host->clock_base / SDHCI_MAX_DIV_SPEC_300; + else + host->mmc_ctrlr.f_min = + host->clock_base / SDHCI_MAX_DIV_SPEC_200; + } + + if (caps & SDHCI_CAN_VDD_330) + host->mmc_ctrlr.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + if (caps & SDHCI_CAN_VDD_300) + host->mmc_ctrlr.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps & SDHCI_CAN_VDD_180) + host->mmc_ctrlr.voltages |= MMC_VDD_165_195; + + if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) + host->mmc_ctrlr.voltages |= host->voltages; + + if (host->quirks & SDHCI_QUIRK_NO_EMMC_HS200) + host->mmc_ctrlr.caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | + MMC_MODE_4BIT | MMC_MODE_HC; + else + host->mmc_ctrlr.caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | + MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS_200MHz; + + if (host->quirks & SDHCI_QUIRK_EMMC_1V8_POWER) + host->mmc_ctrlr.caps |= MMC_MODE_1V8_VDD; + + if (caps & SDHCI_CAN_DO_8BIT) + host->mmc_ctrlr.caps |= MMC_MODE_8BIT; + if (host->host_caps) + host->mmc_ctrlr.caps |= host->host_caps; + if (caps & SDHCI_CAN_64BIT) + host->dma64 = 1; + + sdhci_reset(host, SDHCI_RESET_ALL); + + return 0; +} + +int sdhci_init(SdhciHost *host) +{ + int rv = sdhci_pre_init(host); + + if (rv) + return rv; /* The error has been already reported */ + + sdhci_set_power(host, fls(host->mmc_ctrlr.voltages) - 1); + + if (host->quirks & SDHCI_QUIRK_NO_CD) { + unsigned int status; + + sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, + SDHCI_HOST_CONTROL); + + status = sdhci_readl(host, SDHCI_PRESENT_STATE); + while ((!(status & SDHCI_CARD_PRESENT)) || + (!(status & SDHCI_CARD_STATE_STABLE)) || + (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) + status = sdhci_readl(host, SDHCI_PRESENT_STATE); + } + + /* Enable only interrupts served by the SD controller */ + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, + SDHCI_INT_ENABLE); + /* Mask all sdhci interrupt sources */ + sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); + + /* Set timeout to maximum, shouldn't happen if everything's right. */ + sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); + + udelay(10000); + return 0; +} + +void add_sdhci(SdhciHost *host) +{ + host->mmc_ctrlr.send_cmd = &sdhci_send_command; + host->mmc_ctrlr.set_ios = &sdhci_set_ios; + + /* TODO(vbendeb): check if SDHCI spec allows to retrieve this value. */ + host->mmc_ctrlr.b_max = 65535; +} + + diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h new file mode 100644 index 0000000..c44edad --- /dev/null +++ b/src/drivers/storage/sdhci.h @@ -0,0 +1,363 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen <leiwen(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen(a)cmst.csiro.au, 27-Jan-01. + */ +#ifndef __DRIVER_STORAGE_SDHCI_H__ +#define __DRIVER_STORAGE_SDHCI_H__ + +#include "mmc.h" +#include <device/pci_ops.h> + +/* + * Controller registers + */ + +#define SDHCI_DMA_ADDRESS 0x00 + +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) + +#define SDHCI_BLOCK_COUNT 0x06 + +#define SDHCI_ARGUMENT 0x08 + +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA 0x01 +#define SDHCI_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_TRNS_ACMD12 0x04 +#define SDHCI_TRNS_READ 0x10 +#define SDHCI_TRNS_MULTI 0x20 + +#define SDHCI_COMMAND 0x0E +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 +#define SDHCI_CMD_ABORTCMD 0xC0 + +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) +#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) + +#define SDHCI_RESPONSE 0x10 + +#define SDHCI_BUFFER 0x20 + +#define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DATA_INHIBIT 0x00000002 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_STATE_STABLE 0x00020000 +#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 +#define SDHCI_WRITE_PROTECT 0x00080000 + +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_CTRL_LED 0x01 +#define SDHCI_CTRL_4BITBUS 0x02 +#define SDHCI_CTRL_HISPD 0x04 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_SDMA 0x00 +#define SDHCI_CTRL_ADMA1 0x08 +#define SDHCI_CTRL_ADMA32 0x10 +#define SDHCI_CTRL_ADMA64 0x18 +#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_CD_TEST_INS 0x40 +#define SDHCI_CTRL_CD_TEST 0x80 + +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define SDHCI_WAKE_UP_CONTROL 0x2B +#define SDHCI_WAKE_ON_INT 0x01 +#define SDHCI_WAKE_ON_INSERT 0x02 +#define SDHCI_WAKE_ON_REMOVE 0x04 + +#define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 + +#define SDHCI_TIMEOUT_CONTROL 0x2E + +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_ENABLE 0x34 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ADMA_ERROR 0x02000000 + +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ + SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) +#define SDHCI_INT_ALL_MASK ((unsigned int)-1) + +#define SDHCI_ACMD12_ERR 0x3C + +#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_CTRL_UHS_MASK 0x0007 +#define SDHCI_CTRL_UHS_SDR12 0x0000 +#define SDHCI_CTRL_UHS_SDR25 0x0001 +#define SDHCI_CTRL_UHS_SDR50 0x0002 +#define SDHCI_CTRL_UHS_SDR104 0x0003 +#define SDHCI_CTRL_UHS_DDR50 0x0004 +#define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */ +#define SDHCI_CTRL_VDD_180 0x0008 +#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 +#define SDHCI_CTRL_DRV_TYPE_B 0x0000 +#define SDHCI_CTRL_DRV_TYPE_A 0x0010 +#define SDHCI_CTRL_DRV_TYPE_C 0x0020 +#define SDHCI_CTRL_DRV_TYPE_D 0x0030 +#define SDHCI_CTRL_EXEC_TUNING 0x0040 +#define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + +#define SDHCI_CAPABILITIES 0x40 +#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F +#define SDHCI_TIMEOUT_CLK_SHIFT 0 +#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define SDHCI_CLOCK_BASE_MASK 0x00003F00 +#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 +#define SDHCI_CLOCK_BASE_SHIFT 8 +#define SDHCI_MAX_BLOCK_MASK 0x00030000 +#define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_8BIT 0x00040000 +#define SDHCI_CAN_DO_ADMA2 0x00080000 +#define SDHCI_CAN_DO_ADMA1 0x00100000 +#define SDHCI_CAN_DO_HISPD 0x00200000 +#define SDHCI_CAN_DO_SDMA 0x00400000 +#define SDHCI_CAN_VDD_330 0x01000000 +#define SDHCI_CAN_VDD_300 0x02000000 +#define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT 0x10000000 + +#define SDHCI_CAPABILITIES_1 0x44 + +#define SDHCI_MAX_CURRENT 0x48 + +/* 4C-4F reserved for more max current */ + +#define SDHCI_SET_ACMD12_ERROR 0x50 +#define SDHCI_SET_INT_ERROR 0x52 + +#define SDHCI_ADMA_ERROR 0x54 + +/* 55-57 reserved */ + +#define SDHCI_ADMA_ADDRESS 0x58 + +/* 60-FB reserved */ + +#define SDHCI_SLOT_INT_STATUS 0xFC + +#define SDHCI_HOST_VERSION 0xFE +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + +/* + * End of controller registers. + */ + +#define SDHCI_MAX_DIV_SPEC_200 256 +#define SDHCI_MAX_DIV_SPEC_300 2046 + +/* +* platform_infos +*/ +#define SDHCI_PLATFORM_REMOVABLE (1 << 0) +#define SDHCI_PLATFORM_NO_EMMC_HS200 (1 << 1) +#define SDHCI_PLATFORM_EMMC_1V8_POWER (1 << 2) +#define SDHCI_PLATFORM_NO_CLK_BASE (1 << 3) +/* + * quirks + */ +#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) +#define SDHCI_QUIRK_REG32_RW (1 << 1) +#define SDHCI_QUIRK_BROKEN_R1B (1 << 2) +#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) +#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) +#define SDHCI_QUIRK_NO_CD (1 << 5) +#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) +#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) +#define SDHCI_QUIRK_NO_EMMC_HS200 (1 << 8) +#define SDHCI_QUIRK_EMMC_1V8_POWER (1 << 9) +#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 10) + +/* + * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. + */ +#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) +#define SDHCI_DEFAULT_BOUNDARY_ARG (7) + +/* ADMA packet descriptor */ +typedef struct { + u16 attributes; + u16 length; + u32 addr; +} SdhciAdma; + +typedef struct { + u16 attributes; + u16 length; + u32 addr; + u32 addr_hi; +} SdhciAdma64; + +#define SDHCI_MAX_PER_DESCRIPTOR 0x10000 + +/* ADMA descriptor attributes */ +#define SDHCI_ADMA_VALID (1 << 0) +#define SDHCI_ADMA_END (1 << 1) +#define SDHCI_ADMA_INT (1 << 2) +#define SDHCI_ACT_NOP (0 << 4) +#define SDHCI_ACT_TRAN (2 << 4) +#define SDHCI_ACT_LINK (3 << 4) + +typedef struct sdhci_host SdhciHost; + +struct sdhci_host { + MmcCtrlr mmc_ctrlr; + char *name; + void *ioaddr; + + int initialized; + unsigned quirks; + unsigned host_caps; + unsigned version; + unsigned clock; /* current, min and max interface clocks */ + unsigned clock_f_min; + unsigned clock_f_max; + unsigned clock_base; /* controller base clock */ + int removable; + unsigned voltages; + + /* + * Dynamically allocated array of ADMA descriptors to use for data + * transfers + */ + SdhciAdma *adma_descs; + SdhciAdma64 *adma64_descs; + /* select 32bit or 64bit ADMA operations */ + unsigned dma64; + + /* Number of ADMA descriptors currently in the array. */ + int adma_desc_count; + + int (*attach)(SdhciHost *host); + void (*set_control_reg)(SdhciHost *host); + void (*set_clock)(SdhciHost *host, unsigned int div); +}; + + +static inline void sdhci_writel(SdhciHost *host, u32 val, int reg) +{ + writel(val, host->ioaddr + reg); +} + +static inline void sdhci_writew(SdhciHost *host, u16 val, int reg) +{ + writew(val, host->ioaddr + reg); +} + +static inline void sdhci_writeb(SdhciHost *host, u8 val, int reg) +{ + writeb(val, host->ioaddr + reg); +} +static inline u32 sdhci_readl(SdhciHost *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static inline u16 sdhci_readw(SdhciHost *host, int reg) +{ + return readw(host->ioaddr + reg); +} + +static inline u8 sdhci_readb(SdhciHost *host, int reg) +{ + return readb(host->ioaddr + reg); +} + +void add_sdhci(SdhciHost *host); +int sdhci_init(SdhciHost *host); +SdhciHost* sdhci_get_host_ptr( void ); + +/* Add SDHCI controller from PCI */ +SdhciHost *new_pci_sdhci_host(struct device *dev, + int platform_info, + int clock_min, + int clock_max); + +/* Add SDHCI controller with memory address */ +SdhciHost *new_mem_sdhci_host(void *ioaddr, + int platform_info, + int clock_min, + int clock_max, + int clock_base); + +#endif diff --git a/src/drivers/storage/storage_common.h b/src/drivers/storage/storage_common.h new file mode 100644 index 0000000..f4beae7 --- /dev/null +++ b/src/drivers/storage/storage_common.h @@ -0,0 +1,28 @@ +#ifndef __COMMON_STORAGE_H__ +#define __COMMON_STORAGE_H__ + +#include <stdint.h> + +#define readb(_a) (*(volatile const unsigned char *) (_a)) +#define readw(_a) (*(volatile const unsigned short *) (_a)) +#define readl(_a) (*(volatile const unsigned int *) (_a)) + +#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) +#define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v)) +#define writel(_v, _a) (*(volatile unsigned int *) (_a) = (_v)) + +#define DMA_MINALIGN (64) +#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) + \ + DMA_MINALIGN - 1]; \ + type *name = (type *) ALIGN((uintptr_t)__##name, DMA_MINALIGN) + +/* NOOPs mirroring ARM's cache API, since x86 devices usually cache snoop */ +#define dcache_invalidate_by_mva(addr, len) +#define dcache_clean_invalidate_by_mva(addr, len) + +typedef u32 pcidev_t; +typedef uint64_t lba_t; + +#endif /*__COMMON_STORAGE_H__ */

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Patch merged into coreboot/master: util/cbfstool: Add cbfs-compression-tool
by gerrit＠coreboot.org 12 Jan '17

12 Jan '17

the following patch was just integrated into master: commit c88d16baaf3e88029b40d43eb254e90613b95187 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 11 15:26:58 2017 +0100 util/cbfstool: Add cbfs-compression-tool cbfs-compression-tool provides a way to benchmark the compression algorithms as used by cbfstool (and coreboot) and allows to pre-compress data for later consumption by cbfstool (once it supports the format). For an impression, the benchmark's results on my machine: measuring 'none' compressing 10485760 bytes to 10485760 took 0 seconds measuring 'LZMA' compressing 10485760 bytes to 1736 took 2 seconds measuring 'LZ4' compressing 10485760 bytes to 41880 took 0 seconds And a possible use for external compression, parallel and non-parallel (60MB in 53 files compressed to 650KB on a machine with 40 threads): $ time (ls -1 *.* |xargs -n 1 -P $(nproc) -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA) real 0m0.786s user 0m11.440s sys 0m0.044s $ time (ls -1 *.* |xargs -n 1 -P 1 -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA) real 0m10.444s user 0m10.280s sys 0m0.064s Change-Id: I40be087e85d09a895b1ed277270350ab65a4d6d4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18099 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18099 for details. -gerrit

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Patch merged into coreboot/master: util/cbfstool: compile with -O2 by default
by gerrit＠coreboot.org 12 Jan '17

12 Jan '17

the following patch was just integrated into master: commit 8474e7d7e83e92f3d7118311e2e35dc86dcc3ef5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 11 17:17:18 2017 +0100 util/cbfstool: compile with -O2 by default This speeds up the lzma encoder approximately four-fold. Change-Id: Ibf896098799693ddd0f8a6c74bda2e518ecea869 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18098 for details. -gerrit

1 0

Patch set updated for coreboot: util/cbfstool: Enable adding precompressed files to cbfs
by Patrick Georgi 12 Jan '17

12 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18102 -gerrit commit 0410e7dc70eae67420db98d3450e7c515fb3ba35 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 11 18:38:11 2017 +0100 util/cbfstool: Enable adding precompressed files to cbfs cbfstool ... add ... -c precompression assumes the input file to be created by cbfs-compression-tool's compress command and uses that to add the file with correct metadata. When adding the locale_*.bin files to Chrome OS images, this provides a nice speedup (since we can parallelize the precompression and avoid compressing everything twice) while creating a bit-identical file. Change-Id: Iadd106672c505909528b55e2cd43c914b95b6c6d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfstool.c | 64 +++++++++++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index de50ff3..9f79969 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -79,6 +79,7 @@ static struct param { bool machine_parseable; int fit_empty_entries; enum comp_algo compression; + int precompression; enum vb2_hash_algorithm hash; /* for linux payloads */ char *initrd; @@ -439,33 +440,46 @@ static int cbfstool_convert_raw(struct buffer *buffer, unused uint32_t *offset, struct cbfs_file *header) { char *compressed; - int compressed_size; - - comp_func_ptr compress = compression_function(param.compression); - if (!compress) - return -1; - compressed = calloc(buffer->size, 1); - - if (compress(buffer->data, buffer->size, - compressed, &compressed_size)) { - WARN("Compression failed - disabled\n"); + int decompressed_size, compressed_size; + comp_func_ptr compress; + + decompressed_size = buffer->size; + if (param.precompression) { + param.compression = le32toh(((uint32_t *)buffer->data)[0]); + decompressed_size = le32toh(((uint32_t *)buffer->data)[1]); + compressed_size = buffer->size - 8; + compressed = malloc(compressed_size); + if (!compressed) + return -1; + memcpy(compressed, buffer->data + 8, compressed_size); } else { - struct cbfs_file_attr_compression *attrs = - (struct cbfs_file_attr_compression *) - cbfs_add_file_attr(header, - CBFS_FILE_ATTR_TAG_COMPRESSION, - sizeof(struct cbfs_file_attr_compression)); - if (attrs == NULL) + compress = compression_function(param.compression); + if (!compress) return -1; - attrs->compression = htonl(param.compression); - attrs->decompressed_size = htonl(buffer->size); - - free(buffer->data); - buffer->data = compressed; - buffer->size = compressed_size; + compressed = calloc(buffer->size, 1); - header->len = htonl(buffer->size); + if (compress(buffer->data, buffer->size, + compressed, &compressed_size)) { + WARN("Compression failed - disabled\n"); + return 0; + } } + + struct cbfs_file_attr_compression *attrs = + (struct cbfs_file_attr_compression *) + cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_COMPRESSION, + sizeof(struct cbfs_file_attr_compression)); + if (attrs == NULL) + return -1; + attrs->compression = htonl(param.compression); + attrs->decompressed_size = htonl(decompressed_size); + + free(buffer->data); + buffer->data = compressed; + buffer->size = compressed_size; + + header->len = htonl(buffer->size); return 0; } @@ -1347,6 +1361,10 @@ int main(int argc, char **argv) optarg); break; case 'c': { + if (strcmp(optarg, "precompression") == 0) { + param.precompression = 1; + break; + } int algo = cbfs_parse_comp_algo(optarg); if (algo >= 0) param.compression = algo;

1 0

Patch set updated for coreboot: riscv: get SBI calls to work
by Ronald G. Minnich 12 Jan '17

12 Jan '17

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18097 -gerrit commit 5d78c0faf833155d7d4827912f991c232af9c894 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 10 18:06:48 2017 -0800 riscv: get SBI calls to work SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/bootblock.S | 14 ++++++----- src/arch/riscv/include/mcall.h | 55 ++++++++++++++++++++++++++++++------------ src/arch/riscv/mcall.c | 25 +++++++++++++++++-- src/arch/riscv/trap_handler.c | 12 ++++----- src/arch/riscv/trap_util.S | 12 ++++++--- 5 files changed, 83 insertions(+), 35 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index c54c0e2..43bca90 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -16,6 +16,7 @@ */ #include <arch/encoding.h> +#include <mcall.h> .section ".text._start", "ax", %progbits @@ -30,8 +31,14 @@ _start: # and the stack must be page-aligned. la sp, _estack + # poison the stack + la t1, _stack + li t0, 0xdeadbeef + sd t0, 0(t1) + # make room for HLS and initialize it - addi sp, sp, -64 // MENTRY_FRAME_SIZE + addi sp, sp, -HLS_SIZE + // Once again, the docs and toolchain disagree. // Rather than get fancy I'll just lock this down // until it all stabilizes. @@ -39,11 +46,6 @@ _start: csrr a0, 0xf14 call hls_init - # poison the stack - la t1, _stack - li t0, 0xdeadbeef - sd t0, 0(t1) - la t0, trap_entry csrw mtvec, t0 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index a43b9cf..d74bdf1 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -16,35 +16,56 @@ #ifndef _MCALL_H #define _MCALL_H +// NOTE: this is the size of hls_t below. A static_assert would be +// nice to have. +#define HLS_SIZE 64 + +/* We save 37 registers, currently. */ +#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) + +#define MCALL_HART_ID 0 +#define MCALL_CONSOLE_PUTCHAR 1 +#define MCALL_CONSOLE_GETCHAR 2 +#define MCALL_HTIF_SYSCALL 3 +#define MCALL_SEND_IPI 4 +#define MCALL_CLEAR_IPI 5 +#define MCALL_SHUTDOWN 6 +#define MCALL_SET_TIMER 7 +#define MCALL_REMOTE_SFENCE_VM 8 +#define MCALL_REMOTE_FENCE_I 9 +#define MCALL_CONFIG_STRING_BASE 10 +#define MCALL_CONFIG_STRING_SIZE 11 + +#ifndef __ASSEMBLER__ + #include <arch/encoding.h> #include <atomic.h> #include <stdint.h> -#define HLS_SIZE 64 -#define MENTRY_FRAME_SIZE HLS_SIZE - typedef struct { - unsigned long base; - unsigned long size; - unsigned long node_id; + unsigned long base; + unsigned long size; + unsigned long node_id; } memory_block_info; typedef struct { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; + unsigned long dev; + unsigned long cmd; + unsigned long data; + unsigned long sbi_private_data; } sbi_device_message; typedef struct { - sbi_device_message* device_request_queue_head; - unsigned long device_request_queue_size; - sbi_device_message* device_response_queue_head; - sbi_device_message* device_response_queue_tail; + sbi_device_message *device_request_queue_head; + unsigned long device_request_queue_size; + sbi_device_message *device_response_queue_head; + sbi_device_message *device_response_queue_tail; - int hart_id; - int ipi_pending; + int hart_id; + int ipi_pending; + uint64_t *timecmp; + uint64_t *time; } hls_t; #define MACHINE_STACK_TOP() ({ \ @@ -67,4 +88,6 @@ uintptr_t mcall_send_ipi(uintptr_t recipient); uintptr_t mcall_shutdown(void); void hls_init(uint32_t hart_id); // need to call this before launching linux +#endif // __ASSEMBLER__ + #endif diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index aa61ae4..37a9366 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -34,6 +34,8 @@ #include <string.h> #include <vm.h> +int mcalldebug; // set this interactively for copious debug. + uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) { if (id == 0) { @@ -74,9 +76,17 @@ uintptr_t mcall_shutdown(void) return 0; } -uintptr_t mcall_set_timer(unsigned long long when) +uintptr_t mcall_set_timer(uint64_t when) { - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + uint64_t *timecmp = HLS()->timecmp; + + if (mcalldebug) + printk(BIOS_SPEW, + "hart %d: HLS %p: mcall timecmp@%p to 0x%llx\n", + HLS()->hart_id, HLS(), timecmp, when); + *timecmp = when; + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); return 0; } @@ -94,8 +104,19 @@ uintptr_t mcall_dev_resp(void) void hls_init(uint32_t hart_id) { + query_result res; + + printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS()); memset(HLS(), 0, sizeof(*HLS())); HLS()->hart_id = hart_id; + + res = query_config_string(configstring(), "rtc{addr"); + HLS()->time = (void *)get_uint(res); + res = query_config_string(configstring(), "core{0{0{timecmp"); + HLS()->timecmp = (void *)get_uint(res); + + printk(BIOS_SPEW, "Time is %p and timecmp is %p\n", + HLS()->time, HLS()->timecmp); } uintptr_t mcall_console_putchar(uint8_t ch) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 5681209..9a8947c 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -64,9 +64,6 @@ void handle_supervisor_call(trapframe *tf) { returnValue = mcall_shutdown(); break; case SBI_ECALL_SET_TIMER: - printk(BIOS_DEBUG, - "Setting timer to %p (current time is %p)...\n", - (void *)arg0, (void *)rdtime()); returnValue = mcall_set_timer(arg0); break; case SBI_ECALL_QUERY_MEMORY: @@ -152,7 +149,7 @@ static void gettimer(void) static void interrupt_handler(trapframe *tf) { uint64_t cause = tf->cause & ~0x8000000000000000ULL; - uint32_t ssip, ssie; + uint32_t msip, ssie; switch (cause) { case IRQ_M_TIMER: @@ -183,10 +180,11 @@ static void interrupt_handler(trapframe *tf) if (!timecmp) gettimer(); + //printk(BIOS_SPEW, "timer interrupt\n"); *timecmp = (uint64_t) -1; - ssip = read_csr(sip); - ssip |= SIP_STIP; - write_csr(sip, ssip); + msip = read_csr(mip); + msip |= SIP_STIP; + write_csr(mip, msip); break; default: printk(BIOS_EMERG, "======================================\n"); diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 3357959..ae32379 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -15,6 +15,8 @@ */ #include <bits.h> +#include <mcall.h> + .macro restore_regs # restore x registers LOAD x1,1*REGBYTES(a0) @@ -100,16 +102,17 @@ # get faulting insn, if it wasn't a fetch-related trap li x5,-1 STORE x5,36*REGBYTES(x2) -1: + .endm +.globl estack .text .global supervisor_trap_entry supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - li sp, 0x80FFF0 - 64 - 1:addi sp,sp,-320 + la sp, _estack + addi sp,sp,-MENTRY_FRAME_SIZE save_tf move a0,sp jal trap_handler @@ -127,7 +130,8 @@ trap_entry: # TODO: Use the old stack pointer (plus an offset) for exceptions in machine # mode, to avoid overwriting stack data. - li sp, 0x8000fff0 + la sp, _estack + addi sp,sp,-MENTRY_FRAME_SIZE save_tf move a0,sp

1 0

New patch to review for coreboot: Combine Baytrail ChromeOS devices using variant scheme
by Matt DeVillier 12 Jan '17

12 Jan '17

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18129 -gerrit commit d909695ea90fcf9e6eb4d501c90242656e544d6d Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Jan 12 12:19:21 2017 -0600 Combine Baytrail ChromeOS devices using variant scheme Combine existing boards google/enguarde and google/ninja using their common reference board google/rambi as a baseboard. Variants contain board specific data: - DPTF ACPI components - I2C ACPI devices - RAM config / SPD data - devicetree config - GPIOs - board-specific HW components (e.g., LAN) Additionally, some minor cleanup/changes were made: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting The existing enguarde and ninja boards are removed. Variant setup modeled after google/auron Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/enguarde/Kconfig | 51 ----- src/mainboard/google/enguarde/Kconfig.name | 2 - src/mainboard/google/enguarde/Makefile.inc | 25 --- src/mainboard/google/enguarde/acpi/dptf.asl | 87 -------- src/mainboard/google/enguarde/acpi/ec.asl | 20 -- src/mainboard/google/enguarde/acpi/mainboard.asl | 196 ----------------- src/mainboard/google/enguarde/acpi/superio.asl | 27 --- src/mainboard/google/enguarde/acpi/video.asl | 39 ---- src/mainboard/google/enguarde/acpi_tables.c | 62 ------ src/mainboard/google/enguarde/board_info.txt | 3 - src/mainboard/google/enguarde/chromeos.c | 66 ------ src/mainboard/google/enguarde/chromeos.fmd | 38 ---- src/mainboard/google/enguarde/cmos.layout | 133 ------------ src/mainboard/google/enguarde/devicetree.cb | 101 --------- src/mainboard/google/enguarde/dsdt.asl | 53 ----- src/mainboard/google/enguarde/ec.c | 48 ----- src/mainboard/google/enguarde/ec.h | 59 ------ src/mainboard/google/enguarde/fadt.c | 46 ---- src/mainboard/google/enguarde/gpio.c | 231 -------------------- src/mainboard/google/enguarde/irqroute.c | 18 -- src/mainboard/google/enguarde/irqroute.h | 60 ------ src/mainboard/google/enguarde/mainboard.c | 174 --------------- src/mainboard/google/enguarde/mainboard_smi.c | 142 ------------- src/mainboard/google/enguarde/onboard.h | 34 --- src/mainboard/google/enguarde/romstage.c | 99 --------- src/mainboard/google/enguarde/spd/Makefile.inc | 49 ----- .../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 --- .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 --- .../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 --- .../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 --- .../spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex | 17 -- .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 17 -- src/mainboard/google/enguarde/w25q64.c | 70 ------- src/mainboard/google/ninja/Kconfig | 53 ----- src/mainboard/google/ninja/Kconfig.name | 2 - src/mainboard/google/ninja/Makefile.inc | 26 --- src/mainboard/google/ninja/acpi/dptf.asl | 89 -------- src/mainboard/google/ninja/acpi/ec.asl | 20 -- src/mainboard/google/ninja/acpi/mainboard.asl | 93 -------- src/mainboard/google/ninja/acpi/superio.asl | 25 --- src/mainboard/google/ninja/acpi/video.asl | 38 ---- src/mainboard/google/ninja/acpi_tables.c | 62 ------ src/mainboard/google/ninja/board_info.txt | 3 - src/mainboard/google/ninja/chromeos.c | 68 ------ src/mainboard/google/ninja/chromeos.fmd | 38 ---- src/mainboard/google/ninja/cmos.layout | 132 ------------ src/mainboard/google/ninja/devicetree.cb | 102 --------- src/mainboard/google/ninja/dsdt.asl | 53 ----- src/mainboard/google/ninja/ec.c | 49 ----- src/mainboard/google/ninja/ec.h | 59 ------ src/mainboard/google/ninja/fadt.c | 46 ---- src/mainboard/google/ninja/gpio.c | 228 -------------------- src/mainboard/google/ninja/irqroute.c | 18 -- src/mainboard/google/ninja/irqroute.h | 54 ----- src/mainboard/google/ninja/lan.c | 191 ----------------- src/mainboard/google/ninja/mainboard.c | 164 --------------- src/mainboard/google/ninja/mainboard_smi.c | 143 ------------- src/mainboard/google/ninja/onboard.h | 38 ---- src/mainboard/google/ninja/romstage.c | 99 --------- src/mainboard/google/ninja/spd/Makefile.inc | 49 ----- .../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 --- .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 --- .../spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex | 17 -- .../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 --- .../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 --- src/mainboard/google/ninja/w25q64.c | 70 ------- src/mainboard/google/rambi/Kconfig | 47 +++-- src/mainboard/google/rambi/Kconfig.name | 9 + src/mainboard/google/rambi/Makefile.inc | 15 +- src/mainboard/google/rambi/acpi/dptf.asl | 32 +-- .../google/rambi/acpi/lightsensor_lsd.asl | 55 +++++ src/mainboard/google/rambi/acpi/mainboard.asl | 233 +-------------------- src/mainboard/google/rambi/acpi/superio.asl | 9 +- .../google/rambi/acpi/touchscreen_amtel.asl | 56 +++++ src/mainboard/google/rambi/acpi/trackpad_amtel.asl | 53 +++++ src/mainboard/google/rambi/acpi/trackpad_elan.asl | 53 +++++ src/mainboard/google/rambi/board_info.txt | 4 + src/mainboard/google/rambi/devicetree.cb | 102 --------- src/mainboard/google/rambi/gpio.c | 231 -------------------- src/mainboard/google/rambi/mainboard.c | 12 +- src/mainboard/google/rambi/onboard.h | 40 ---- src/mainboard/google/rambi/romstage.c | 20 +- src/mainboard/google/rambi/spd/Makefile.inc | 45 ---- .../spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex | 17 ++ .../spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex | 17 ++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 17 ++ .../google/rambi/variants/enguarde/Makefile.inc | 49 +++++ .../google/rambi/variants/enguarde/devicetree.cb | 101 +++++++++ .../google/rambi/variants/enguarde/gpio.c | 230 ++++++++++++++++++++ .../enguarde/include/variant/acpi/dptf.asl | 41 ++++ .../enguarde/include/variant/acpi/mainboard.asl | 21 ++ .../variants/enguarde/include/variant/onboard.h | 36 ++++ .../variants/enguarde/include/variant/variant.h | 37 ++++ .../google/rambi/variants/ninja/Makefile.inc | 49 +++++ .../google/rambi/variants/ninja/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/ninja/gpio.c | 227 ++++++++++++++++++++ .../variants/ninja/include/variant/acpi/dptf.asl | 43 ++++ .../ninja/include/variant/acpi/mainboard.asl | 0 .../rambi/variants/ninja/include/variant/onboard.h | 40 ++++ .../rambi/variants/ninja/include/variant/variant.h | 37 ++++ src/mainboard/google/rambi/variants/ninja/lan.c | 191 +++++++++++++++++ .../google/rambi/variants/rambi/Makefile.inc | 45 ++++ .../google/rambi/variants/rambi/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/rambi/gpio.c | 230 ++++++++++++++++++++ .../variants/rambi/include/variant/acpi/dptf.asl | 43 ++++ .../rambi/include/variant/acpi/mainboard.asl | 24 +++ .../rambi/variants/rambi/include/variant/onboard.h | 40 ++++ .../rambi/variants/rambi/include/variant/variant.h | 34 +++ 108 files changed, 2073 insertions(+), 4968 deletions(-) diff --git a/src/mainboard/google/enguarde/Kconfig b/src/mainboard/google/enguarde/Kconfig deleted file mode 100644 index c2842bb..0000000 --- a/src/mainboard/google/enguarde/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -if BOARD_GOOGLE_ENGUARDE - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_BAYTRAIL - select EC_GOOGLE_CHROMEEC - select ENABLE_BUILTIN_COM1 - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - -config CHROMEOS - select VBOOT_VBNV_CMOS - select LID_SWITCH - select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/enguarde - -config MAINBOARD_PART_NUMBER - string - default "Enguarde" - -config VGA_BIOS_FILE - string - default "pci8086,0f31.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "" - -config GBB_HWID - string - depends on CHROMEOS - default "ENGUARDE TEST A-A 0128" - -endif # BOARD_GOOGLE_ENGUARDE diff --git a/src/mainboard/google/enguarde/Kconfig.name b/src/mainboard/google/enguarde/Kconfig.name deleted file mode 100644 index 2145c8c..0000000 --- a/src/mainboard/google/enguarde/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_ENGUARDE - bool "Enguarde" diff --git a/src/mainboard/google/enguarde/Makefile.inc b/src/mainboard/google/enguarde/Makefile.inc deleted file mode 100644 index da7053a..0000000 --- a/src/mainboard/google/enguarde/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd - -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += gpio.c -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -ramstage-y += irqroute.c -ramstage-y += w25q64.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/enguarde/acpi/dptf.asl b/src/mainboard/google/enguarde/acpi/dptf.asl deleted file mode 100644 index cf82fa6..0000000 --- a/src/mainboard/google/enguarde/acpi/dptf.asl +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 - -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 - -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ -}) - -/* Mainboard specific _PDL is 1GHz */ -Name (MPDL, 8) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, // Revision - Package () { // Power Limit 1 - 0, // PowerLimitIndex, 0 for Power Limit 1 - 1600, // PowerLimitMinimum - 6200, // PowerLimitMaximum - 1000, // TimeWindowMinimum - 1000, // TimeWindowMaximum - 200 // StepSize - }, - Package () { // Power Limit 2 - 1, // PowerLimitIndex, 1 for Power Limit 2 - 8000, // PowerLimitMinimum - 8000, // PowerLimitMaximum - 1000, // TimeWindowMinimum - 1000, // TimeWindowMaximum - 1000 // StepSize - } -}) - -/* Include Baytrail DPTF */ -#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/enguarde/acpi/ec.asl b/src/mainboard/google/enguarde/acpi/ec.asl deleted file mode 100644 index fb81ae0..0000000 --- a/src/mainboard/google/enguarde/acpi/ec.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/enguarde/ec.h> - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/enguarde/acpi/mainboard.asl b/src/mainboard/google/enguarde/acpi/mainboard.asl deleted file mode 100644 index 9396485..0000000 --- a/src/mainboard/google/enguarde/acpi/mainboard.asl +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/enguarde/onboard.h> - -Scope (\_SB) -{ - Device (LID0) - { - Name (_HID, EisaId ("PNP0C0D")) - Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 }) - Method (_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - } - - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - Name (_UID, 1) - } - - /* Wake device for touchpad */ - Device (TPAD) - { - Name (_HID, EisaId ("PNP0C0E")) - Name (_UID, 1) - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - Name (RBUF, ResourceTemplate() - { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_CRS) - { - /* Return interrupt if I2C1 is PCI mode */ - If (LEqual (\S1EN, 0)) { - Return (^RBUF) - } - - /* Return empty resource template otherwise */ - Return (ResourceTemplate() {}) - } - } -} - -Scope (\_SB.I2C1) -{ - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 3) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C1", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.I2C2) -{ - Device (CODC) - { - /* - * TODO(dlaurie): Need official HID. - * - * The current HID is created from the Maxim Integrated - * PCI Vendor ID 193Ch and a shortened device identifier. - */ - Name (_HID, "193C9890") - Name (_DDN, "Maxim 98090 Codec") - Name (_UID, 1) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x10, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C2", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_CODEC_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} - -Scope (\_SB.I2C5) -{ - Device (ALSI) - { - /* - * TODO(dlaurie): Need official HID. - * - * The current HID is created from the Intersil PNP - * Vendor ID "LSD" and a shortened device identifier. - */ - Name (_HID, EisaId ("LSD2918")) - Name (_DDN, "Intersil 29018 Ambient Light Sensor") - Name (_UID, 1) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x44, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C5", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_ALS_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S5EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} - -Scope (\_SB.LPEA) -{ - Name (GBUF, ResourceTemplate () - { - /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 14 } - - /* Mic Detect (index 1) */ - GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 15 } - }) -} diff --git a/src/mainboard/google/enguarde/acpi/superio.asl b/src/mainboard/google/enguarde/acpi/superio.asl deleted file mode 100644 index b8d7be0..0000000 --- a/src/mainboard/google/enguarde/acpi/superio.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/enguarde/ec.h> -#include <mainboard/google/enguarde/onboard.h> - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -// Override default IRQ settings -#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ} - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/enguarde/acpi/video.asl b/src/mainboard/google/enguarde/acpi/video.asl deleted file mode 100644 index 1405b04..0000000 --- a/src/mainboard/google/enguarde/acpi/video.asl +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} - diff --git a/src/mainboard/google/enguarde/acpi_tables.c b/src/mainboard/google/enguarde/acpi_tables.c deleted file mode 100644 index e2add77..0000000 --- a/src/mainboard/google/enguarde/acpi_tables.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/acpi.h> -#include <soc/nvs.h> -#include <soc/iomap.h> - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 1; - - /* Enable DPTF */ - gnvs->dpte = 1; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/google/enguarde/board_info.txt b/src/mainboard/google/enguarde/board_info.txt deleted file mode 100644 index 3e630d3..0000000 --- a/src/mainboard/google/enguarde/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: laptop -ROM protocol: SPI -Flashrom support: y diff --git a/src/mainboard/google/enguarde/chromeos.c b/src/mainboard/google/enguarde/chromeos.c deleted file mode 100644 index 68fb0a7..0000000 --- a/src/mainboard/google/enguarde/chromeos.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ -#define WP_STATUS_PAD 36 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. - */ -#if defined(__PRE_RAM__) - ssus_disable_internal_pull(WP_STATUS_PAD); -#endif - - /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/enguarde/chromeos.fmd b/src/mainboard/google/enguarde/chromeos.fmd deleted file mode 100644 index 113fba6..0000000 --- a/src/mainboard/google/enguarde/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/google/enguarde/cmos.layout b/src/mainboard/google/enguarde/cmos.layout deleted file mode 100644 index b419315..0000000 --- a/src/mainboard/google/enguarde/cmos.layout +++ /dev/null @@ -1,133 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/enguarde/devicetree.cb b/src/mainboard/google/enguarde/devicetree.cb deleted file mode 100644 index f3792fe..0000000 --- a/src/mainboard/google/enguarde/devicetree.cb +++ /dev/null @@ -1,101 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Enguarde board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 on end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/enguarde/dsdt.asl b/src/mainboard/google/enguarde/dsdt.asl deleted file mode 100644 index e21b3d1..0000000 --- a/src/mainboard/google/enguarde/dsdt.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define ENABLE_TPM - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x05, // DSDT revision: ACPI v5.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/baytrail/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/baytrail/acpi/globalnvs.asl> - - #include <soc/intel/baytrail/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - //#include <soc/intel/baytrail/acpi/northcluster.asl> - #include <soc/intel/baytrail/acpi/southcluster.asl> - } - - /* Dynamic Platform Thermal Framework */ - #include "acpi/dptf.asl" - } - - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - /* Chipset specific sleep states */ - #include <soc/intel/baytrail/acpi/sleepstates.asl> - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/enguarde/ec.c b/src/mainboard/google/enguarde/ec.c deleted file mode 100644 index 33c8d24..0000000 --- a/src/mainboard/google/enguarde/ec.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void mainboard_ec_init(void) -{ - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/google/enguarde/ec.h b/src/mainboard/google/enguarde/ec.h deleted file mode 100644 index 4a4599c..0000000 --- a/src/mainboard/google/enguarde/ec.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */ -#define EC_SCI_GPI 24 -/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ -#define EC_SMI_GPI 23 - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#endif diff --git a/src/mainboard/google/enguarde/fadt.c b/src/mainboard/google/enguarde/fadt.c deleted file mode 100644 index 2434d1a..0000000 --- a/src/mainboard/google/enguarde/fadt.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/enguarde/gpio.c b/src/mainboard/google/enguarde/gpio.c deleted file mode 100644 index 8ba5f50..0000000 --- a/src/mainboard/google/enguarde/gpio.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <soc/gpio.h> -#include "irqroute.h" - -/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */ -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ - GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ - GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ - GPIO_NC, /* S0_NC03 - NC */ - GPIO_NC, /* S0_NC04 - NC */ - GPIO_NC, /* S0_NC05 - NC */ - GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ - GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ - GPIO_NC, /* S0_NC08 - NC */ - GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ - GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ - GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ - GPIO_NC, /* S0_NC12 - NC */ - GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ - GPIO_NC, /* S0_NC14 - NC */ - GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ - GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ - GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ - GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ - GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ - GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ - GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ - GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ - GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ - GPIO_NC, /* S0_NC24 - NC */ - GPIO_NC, /* S0_NC25 - NC */ - GPIO_NC, /* S0_NC26 - NC */ - GPIO_END -}; - -/* SCORE GPIOs */ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ - GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ - GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ - GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ - GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ - GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ - GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ - GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ - GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ - GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ - GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ - GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ - GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ - GPIO_NC, /* S0-SC013 - NC */ - GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ - GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ - GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ - GPIO_NC, /* S0-SC027 - NC */ - GPIO_NC, /* S0-SC028 - NC */ - GPIO_NC, /* S0-SC029 - NC */ - GPIO_NC, /* S0-SC030 - NC */ - GPIO_NC, /* S0-SC031 - NC */ - GPIO_NC, /* S0-SC032 - NC */ - GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ - GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ - GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ - GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ - GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ - GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ - GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ - GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ - GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ - GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ - GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ - GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ - GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ - GPIO_DEFAULT, /* S0-SC054 - NC */ - GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ - GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ - GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ - GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ - GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ - GPIO_NC, /* S0-SC060 - NC */ - GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ - GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ - GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ - GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ - GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ - GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ - GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ - GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ - GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ - GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ - GPIO_NC, /* S0-SC071 - NC */ - GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ - GPIO_NC, /* S0-SC073 - NC */ - GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ - GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ - GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ - GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ - GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ - GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ - GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ - GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ - GPIO_NC, /* S0-SC082 - NC */ - GPIO_NC, /* S0-SC083 - NC */ - GPIO_NC, /* S0-SC084 - NC */ - GPIO_NC, /* S0-SC085 - NC */ - GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ - GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ - GPIO_NC, /* S0-SC088 - I2C_5_SDA */ - GPIO_NC, /* S0-SC089 - I2C_5_SCL */ - GPIO_NC, /* S0-SC090 - NC */ - GPIO_NC, /* S0-SC091 - NC */ - GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ - GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ - GPIO_NC, /* S0-SC094 - NC */ - GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ - GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ - GPIO_NC, /* S0-SC097 - NC */ - GPIO_NC, /* S0-SC098 - NC */ - GPIO_NC, /* S0-SC099 - NC */ - GPIO_NC, /* S0-SC100 - NC */ - GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ - GPIO_END -}; - -/* SSUS GPIOs */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ - GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ - GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ - GPIO_FUNC(6, PULL_UP, 20K), /* S503 - LTE_WAKE_L# - INT */ - GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ - GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ - GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ - GPIO_NC, /* S508 - NC */ - GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ - GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ - GPIO_FUNC0, /* S511 - SUSPWRDNACK */ - GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ - GPIO_FUNC0, /* S513 - SLP_SX */ - GPIO_NC, /* S514 - NC */ - GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ - GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ - GPIO_NC, /* S517 - NC */ - GPIO_FUNC0, /* S518 - SUS_STAT# */ - GPIO_FUNC0, /* S519 - USB_OC0# */ - GPIO_FUNC0, /* S520 - USB_OC1# */ - GPIO_NC, /* S521 - NC */ - GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ - GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ - GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ - GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ - GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ - GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ - GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ - GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ - GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ - GPIO_NC, /* S531 - NC */ - GPIO_NC, /* S532 - NC */ - GPIO_NC, /* S533 - NC */ - GPIO_NC, /* S534 - NC */ - GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ - GPIO_NC, /* S536 - NC */ - GPIO_INPUT, /* S537 - RAM_ID0 */ - GPIO_INPUT, /* S538 - RAM_ID1 */ - GPIO_INPUT, /* S539 - RAM_ID2 */ - GPIO_NC, /* S540 - NC */ - GPIO_NC, /* S541 - NC */ - GPIO_NC, /* S542 - NC */ - GPIO_NC, /* S543 - NC */ - GPIO_END -}; - -static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { - [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, - [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, - [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, - [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, -}; - -static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { - [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = &core_dedicated_irq, - .sus_dirq = &sus_dedicated_irq, -}; - -struct soc_gpio_config* mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/google/enguarde/irqroute.c b/src/mainboard/google/enguarde/irqroute.c deleted file mode 100644 index f2bb352..0000000 --- a/src/mainboard/google/enguarde/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/enguarde/irqroute.h b/src/mainboard/google/enguarde/irqroute.h deleted file mode 100644 index 75d416b..0000000 --- a/src/mainboard/google/enguarde/irqroute.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/irq.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) - -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, DISABLE), \ - PIRQ_PIC(B, DISABLE), \ - PIRQ_PIC(C, DISABLE), \ - PIRQ_PIC(D, DISABLE), \ - PIRQ_PIC(E, DISABLE), \ - PIRQ_PIC(F, DISABLE), \ - PIRQ_PIC(G, DISABLE), \ - PIRQ_PIC(H, DISABLE) - -/* CORE bank DIRQs - up to 16 supported */ -#define TPAD_IRQ_OFFSET 0 -#define TOUCH_IRQ_OFFSET 1 -#define I8042_IRQ_OFFSET 2 -#define ALS_IRQ_OFFSET 3 -/* Corresponding SCORE GPIO pins */ -#define TPAD_IRQ_GPIO 55 -#define TOUCH_IRQ_GPIO 72 -#define I8042_IRQ_GPIO 101 -#define ALS_IRQ_GPIO 70 - -/* SUS bank DIRQs - up to 16 supported */ -#define CODEC_IRQ_OFFSET 0 -/* Corresponding SUS GPIO pins */ -#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/enguarde/mainboard.c b/src/mainboard/google/enguarde/mainboard.c deleted file mode 100644 index 7ca55b5..0000000 --- a/src/mainboard/google/enguarde/mainboard.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <smbios.h> -#include "ec.h" -#include "onboard.h" -#include <soc/gpio.h> -#include <bootstate.h> -#include <vendorcode/google/chromeos/chromeos.h> - -void mainboard_suspend_resume(void) -{ -} - -#if CONFIG_VGA_ROM_RUN -static int int15_handler(void) -{ - int res = 1; - - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); - - switch (X86_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default - */ - X86_AX = 0x005f; - X86_CX = 0x0001; - res = 1; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV - * bit 2 = EFP (HDMI) - * bit 3 = LFP (eDP)* - * bit 4 = CRT2 - * bit 5 = TV2 - * bit 6 = EFP2 - * bit 7 = LFP2 - */ - X86_AX = 0x005f; - X86_CX = 0x0008; - res = 1; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - X86_AX = 0x005f; - X86_CX = 0x0003; - res = 1; - break; - case 0x5f70: - switch ((X86_CX >> 8) & 0xff) { - case 0: - /* Get Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 1: - /* Set Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 2: - /* Get SG/Non-SG mode */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", - ((X86_CX >> 8) & 0xff)); - break; - } - break; - - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); - break; - } - return res; -} -#endif - -static void mainboard_init(device_t dev) -{ - mainboard_ec_init(); -} - -static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) -{ - int len = 0; - - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - BOARD_TRACKPAD_I2C_BUS, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - return len; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if CONFIG_VGA_ROM_RUN - /* Install custom int15 handler for VGA OPROM */ - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -static void edp_vdden_cb(void *unused) -{ - ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL); diff --git a/src/mainboard/google/enguarde/mainboard_smi.c b/src/mainboard/google/enguarde/mainboard_smi.c deleted file mode 100644 index 62ad92f..0000000 --- a/src/mainboard/google/enguarde/mainboard_smi.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <elog.h> - -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -#include <soc/nvs.h> -#include <soc/pmc.h> - -/* The wake gpio is SUS_GPIO[0]. */ -#define WAKE_GPIO_EN SUS_GPIO_EN0 - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; -} - -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - -/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that - * this includes the enable bits in the lower 16 bits. */ -void mainboard_smi_gpi(uint32_t alt_gpio_smi) -{ - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -} - -void mainboard_smi_sleep(uint8_t slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - if (smm_get_gnvs()->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - /* Enable wake pin in GPE block. */ - enable_gpe(WAKE_GPIO_EN); - break; - case 5: - if (smm_get_gnvs()->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); -} - -int mainboard_smi_apmc(uint8_t apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } - return 0; -} diff --git a/src/mainboard/google/enguarde/onboard.h b/src/mainboard/google/enguarde/onboard.h deleted file mode 100644 index 3fda837..0000000 --- a/src/mainboard/google/enguarde/onboard.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#include "irqroute.h" - -/* PCH wake signal from EC. */ -#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) -#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) -#define BOARD_TRACKPAD_I2C_BUS 0 -#define BOARD_TRACKPAD_I2C_ADDR 0x15 - -#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) -#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) -#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) - -#endif diff --git a/src/mainboard/google/enguarde/romstage.c b/src/mainboard/google/enguarde/romstage.c deleted file mode 100644 index 2c3bb38..0000000 --- a/src/mainboard/google/enguarde/romstage.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/mrc_wrapper.h> -#include <soc/romstage.h> - -/* - * RAM_ID[2:0] are on GPIO_SSUS[39:37] - * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz - * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz - * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b101 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz - * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - */ -static const uint32_t dual_channel_config = - (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6); - -#define SPD_SIZE 256 -#define GPIO_SSUS_37_PAD 57 -#define GPIO_SSUS_38_PAD 50 -#define GPIO_SSUS_39_PAD 58 - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) -{ - int ram_id = 0; - - /* The ram_id[2:0] pullups on enguarde are too large for the default 20K - * pulldown on the pad. Therefore, disable the internal pull resistor to - * read high values correctly. */ - ssus_disable_internal_pull(GPIO_SSUS_37_PAD); - ssus_disable_internal_pull(GPIO_SSUS_38_PAD); - ssus_disable_internal_pull(GPIO_SSUS_39_PAD); - - ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); - ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); - ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); - - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - - if (ram_id >= total_spds) - return NULL; - - /* Single channel configs */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; - - return &spd_file_content[SPD_SIZE * ram_id]; -} - -void mainboard_romstage_entry(struct romstage_params *rp) -{ - void *spd_content; - int dual_channel = 0; - void *spd_file; - size_t spd_fsize; - - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; - - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); - if (!spd_file) - die("SPD data not found."); - - /* Both channels are always present. */ - spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, - &dual_channel); - mp.mainboard.dram_data[0] = spd_content; - if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; - - rp->mrc_params = &mp; - romstage_common(rp); -} diff --git a/src/mainboard/google/enguarde/spd/Makefile.inc b/src/mainboard/google/enguarde/spd/Makefile.inc deleted file mode 100644 index 5e0042a..0000000 --- a/src/mainboard/google/enguarde/spd/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -SPD_BIN = $(obj)/spd.bin - -# Order matters for SPD sources. The following indicies -# define the SPD data to use. -# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz -# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz -# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz -# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b101 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz -# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz -# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz -SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA -SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 -SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA -SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 -SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0 -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/enguarde/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/enguarde/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex deleted file mode 100644 index 4bd8e0e..0000000 --- a/src/mainboard/google/enguarde/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 03 11 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -00 05 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 22 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 41 5f -48 4d 54 33 31 32 53 36 -44 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/enguarde/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/enguarde/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex deleted file mode 100644 index ff4fd29..0000000 --- a/src/mainboard/google/enguarde/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 ff ab -48 4d 54 34 32 35 53 36 -41 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/enguarde/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/enguarde/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex deleted file mode 100644 index f99c92a..0000000 --- a/src/mainboard/google/enguarde/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 03 11 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 86 -50 00 3c 3c 01 40 83 05 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2c 00 -00 00 00 00 00 00 6a 15 -34 4b 54 46 32 35 36 36 -34 48 5a 2d 31 47 36 45 -31 20 45 31 80 2c 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/enguarde/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/enguarde/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex deleted file mode 100644 index f3bcb56..0000000 --- a/src/mainboard/google/enguarde/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 04 19 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 86 -20 08 3c 3c 01 40 83 05 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2c 00 -00 00 00 00 00 00 19 d2 -34 4b 54 46 32 35 36 36 -34 48 5a 2d 31 47 36 45 -31 20 45 31 80 2c 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/enguarde/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex b/src/mainboard/google/enguarde/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex deleted file mode 100644 index 96cf568..0000000 --- a/src/mainboard/google/enguarde/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Samsung K4B2G1646Q-BYK0 -92 12 0B 03 03 11 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 00 05 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 20 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 -4b 34 42 32 47 31 36 34 36 51 2d 42 59 4b 30 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/enguarde/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/enguarde/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex deleted file mode 100644 index ac9a0e0..0000000 --- a/src/mainboard/google/enguarde/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Samsung K4B4G1646Q-HYK0 -92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 -4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/enguarde/w25q64.c b/src/mainboard/google/enguarde/w25q64.c deleted file mode 100644 index a9ed8ac..0000000 --- a/src/mainboard/google/enguarde/w25q64.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/spi.h> - -/* - * SPI lockdown configuration W25Q64FW. - */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) -#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) - -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, - .lvscc = SPI_VSCC, - .uvscc = SPI_VSCC, -}; - -int mainboard_get_spi_config(struct spi_config *cfg) -{ - memcpy(cfg, &spi_config, sizeof(*cfg)); - - return 0; -} diff --git a/src/mainboard/google/ninja/Kconfig b/src/mainboard/google/ninja/Kconfig deleted file mode 100644 index 4c28e1a..0000000 --- a/src/mainboard/google/ninja/Kconfig +++ /dev/null @@ -1,53 +0,0 @@ -if BOARD_GOOGLE_NINJA - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_BAYTRAIL - select EC_GOOGLE_CHROMEEC - select ENABLE_BUILTIN_COM1 - select DRIVERS_UART_8250IO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - -config CHROMEOS - select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC - select LID_SWITCH - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - select PHYSICAL_REC_SWITCH - -config MAINBOARD_DIR - string - default google/ninja - -config MAINBOARD_PART_NUMBER - string - default "Ninja" - -config VGA_BIOS_FILE - string - default "pci8086,0f31.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "" - -config GBB_HWID - string - depends on CHROMEOS - default "NINJA TEST A-A 0653" - -endif # BOARD_GOOGLE_NINJA diff --git a/src/mainboard/google/ninja/Kconfig.name b/src/mainboard/google/ninja/Kconfig.name deleted file mode 100644 index 17ed8db..0000000 --- a/src/mainboard/google/ninja/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_NINJA - bool "Ninja" diff --git a/src/mainboard/google/ninja/Makefile.inc b/src/mainboard/google/ninja/Makefile.inc deleted file mode 100644 index 1c21aae..0000000 --- a/src/mainboard/google/ninja/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd - -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -ramstage-y += gpio.c -ramstage-y += irqroute.c -ramstage-y += w25q64.c -ramstage-y += lan.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/ninja/acpi/dptf.asl b/src/mainboard/google/ninja/acpi/dptf.asl deleted file mode 100644 index be9bd65..0000000 --- a/src/mainboard/google/ninja/acpi/dptf.asl +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 105 - -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 80 - -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 80 - -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 80 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ -}) - -/* Mainboard specific _PDL is 1GHz */ -Name (MPDL, 8) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, // Revision - Package () { // Power Limit 1 - 0, // PowerLimitIndex, 0 for Power Limit 1 - 1600, // PowerLimitMinimum - 6200, // PowerLimitMaximum - 1000, // TimeWindowMinimum - 1000, // TimeWindowMaximum - 200 // StepSize - }, - Package () { // Power Limit 2 - 1, // PowerLimitIndex, 1 for Power Limit 2 - 8000, // PowerLimitMinimum - 8000, // PowerLimitMaximum - 1000, // TimeWindowMinimum - 1000, // TimeWindowMaximum - 1000 // StepSize - } -}) - -/* Include Baytrail DPTF */ -#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/ninja/acpi/ec.asl b/src/mainboard/google/ninja/acpi/ec.asl deleted file mode 100644 index 147b67d..0000000 --- a/src/mainboard/google/ninja/acpi/ec.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/ninja/ec.h> - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/ninja/acpi/mainboard.asl b/src/mainboard/google/ninja/acpi/mainboard.asl deleted file mode 100644 index 513fe7d..0000000 --- a/src/mainboard/google/ninja/acpi/mainboard.asl +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/ninja/onboard.h> - -Scope (\_SB) -{ - Device (LID0) - { - Name (_HID, EisaId ("PNP0C0D")) - Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 }) - Method (_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - } - - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - Name (_UID, 1) - } -} - -Scope (\_SB.I2C2) -{ - Device (CODC) - { - /* - * TODO(dlaurie): Need official HID. - * - * The current HID is created from the Maxim Integrated - * PCI Vendor ID 193Ch and a shortened device identifier. - */ - Name (_HID, "193C9890") - Name (_DDN, "Maxim 98090 Codec") - Name (_UID, 1) - - Name (SPKR, 0) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x10, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C2", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_CODEC_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} - -Scope (\_SB.LPEA) -{ - Name (GBUF, ResourceTemplate () - { - /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 14 } - - /* Mic Detect (index 1) */ - GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 15 } - }) -} diff --git a/src/mainboard/google/ninja/acpi/superio.asl b/src/mainboard/google/ninja/acpi/superio.asl deleted file mode 100644 index 92abb12..0000000 --- a/src/mainboard/google/ninja/acpi/superio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/ninja/ec.h> -#include <mainboard/google/ninja/onboard.h> - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#undef SIO_EC_ENABLE_PS2K // Disable PS/2 Keyboard - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/ninja/acpi/video.asl b/src/mainboard/google/ninja/acpi/video.asl deleted file mode 100644 index 6894655..0000000 --- a/src/mainboard/google/ninja/acpi/video.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/google/ninja/acpi_tables.c b/src/mainboard/google/ninja/acpi_tables.c deleted file mode 100644 index 9abdbf5..0000000 --- a/src/mainboard/google/ninja/acpi_tables.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/acpi.h> -#include <soc/nvs.h> -#include <soc/iomap.h> - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 1; - - /* Enable DPTF */ - gnvs->dpte = 1; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/google/ninja/board_info.txt b/src/mainboard/google/ninja/board_info.txt deleted file mode 100644 index 57ef3bc..0000000 --- a/src/mainboard/google/ninja/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: half -ROM protocol: SPI -Flashrom support: y diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c deleted file mode 100644 index fa4c66f..0000000 --- a/src/mainboard/google/ninja/chromeos.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> - -/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ -#define WP_STATUS_PAD 36 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {ssus_get_gpio(WP_STATUS_PAD), ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. - */ -#if defined(__PRE_RAM__) - ssus_disable_internal_pull(WP_STATUS_PAD); -#endif - - /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/ninja/chromeos.fmd b/src/mainboard/google/ninja/chromeos.fmd deleted file mode 100644 index 113fba6..0000000 --- a/src/mainboard/google/ninja/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/google/ninja/cmos.layout b/src/mainboard/google/ninja/cmos.layout deleted file mode 100644 index c508d64..0000000 --- a/src/mainboard/google/ninja/cmos.layout +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/ninja/devicetree.cb b/src/mainboard/google/ninja/devicetree.cb deleted file mode 100644 index 6d56130..0000000 --- a/src/mainboard/google/ninja/devicetree.cb +++ /dev/null @@ -1,102 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Ninja board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 on end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 off end # PCIE_PORT2 - device pci 1c.2 on end # PCIE_PORT3 - device pci 1c.3 on end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/ninja/dsdt.asl b/src/mainboard/google/ninja/dsdt.asl deleted file mode 100644 index a37756f..0000000 --- a/src/mainboard/google/ninja/dsdt.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define ENABLE_TPM - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x05, // DSDT revision: ACPI v5.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/baytrail/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/baytrail/acpi/globalnvs.asl> - - #include <soc/intel/baytrail/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - //#include <soc/intel/baytrail/acpi/northcluster.asl> - #include <soc/intel/baytrail/acpi/southcluster.asl> - } - - /* Dynamic Platform Thermal Framework */ - #include "acpi/dptf.asl" - } - - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - /* Chipset specific sleep states */ - #include <soc/intel/baytrail/acpi/sleepstates.asl> - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/ninja/ec.c b/src/mainboard/google/ninja/ec.c deleted file mode 100644 index 147cded..0000000 --- a/src/mainboard/google/ninja/ec.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void mainboard_ec_init(void) -{ - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/google/ninja/ec.h b/src/mainboard/google/ninja/ec.h deleted file mode 100644 index 92c1318..0000000 --- a/src/mainboard/google/ninja/ec.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */ -#define EC_SCI_GPI 24 -/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ -#define EC_SMI_GPI 23 - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#endif diff --git a/src/mainboard/google/ninja/fadt.c b/src/mainboard/google/ninja/fadt.c deleted file mode 100644 index 2434d1a..0000000 --- a/src/mainboard/google/ninja/fadt.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/ninja/gpio.c b/src/mainboard/google/ninja/gpio.c deleted file mode 100644 index 81f01ba..0000000 --- a/src/mainboard/google/ninja/gpio.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <soc/gpio.h> -#include "irqroute.h" - -/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */ -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ - GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ - GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ - GPIO_NC, /* S0_NC03 - NC */ - GPIO_NC, /* S0_NC04 - NC */ - GPIO_NC, /* S0_NC05 - NC */ - GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ - GPIO_FUNC2, /* S0_NC07 - DDI1_DDCDATA */ - GPIO_FUNC2, /* S0_NC08 - DDI1_DDCCLK */ - GPIO_NC, /* S0_NC09 - NC */ - GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ - GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ - GPIO_NC, /* S0_NC12 - NC */ - GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ - GPIO_NC, /* S0_NC14 - NC */ - GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ - GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ - GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ - GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ - GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ - GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ - GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ - GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ - GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ - GPIO_NC, /* S0_NC24 - NC */ - GPIO_NC, /* S0_NC25 - NC */ - GPIO_NC, /* S0_NC26 - NC */ - GPIO_END -}; - -/* SCORE GPIOs */ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ - GPIO_NC, /* S0_SC001 - NC */ - GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ - GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE0# */ - GPIO_NC, /* S0-SC004 - NC# */ - GPIO_FUNC1, /* S0-SC005 - PCIE_CLKREQ_WLAN# */ - GPIO_FUNC1, /* S0-SC006 - PCIE_CLKREQ_LAN# */ - GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ - GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ - GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ - GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ - GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ - GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ - GPIO_NC, /* S0-SC013 - NC */ - GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ - GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ - GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ - GPIO_NC, /* S0-SC027 - NC */ - GPIO_NC, /* S0-SC028 - NC */ - GPIO_NC, /* S0-SC029 - NC */ - GPIO_NC, /* S0-SC030 - NC */ - GPIO_NC, /* S0-SC031 - NC */ - GPIO_NC, /* S0-SC032 - NC */ - GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ - GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ - GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ - GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ - GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ - GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ - GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ - GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ - GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ - GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ - GPIO_FUNC1, /* S0-SC051 - SMB_SOC_DATA (XDP) */ - GPIO_FUNC1, /* S0-SC052 - SMB_SOC_CLK (XDP) */ - GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ - GPIO_DEFAULT, /* S0-SC054 - NC */ - GPIO_NC, /* S0-SC055 - NC */ - GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ - GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ - GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ - GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ - GPIO_NC, /* S0-SC060 - NC */ - GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ - GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ - GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ - GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ - GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ - GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ - GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ - GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ - GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ - GPIO_NC, /* S0-SC070 - NC */ - GPIO_NC, /* S0-SC071 - NC */ - GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ - GPIO_NC, /* S0-SC073 - NC */ - GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ - GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ - GPIO_NC, /* S0-SC076 - NC */ - GPIO_NC, /* S0-SC077 - NC */ - GPIO_NC, /* S0-SC078 - NC */ - GPIO_NC, /* S0-SC079 - NC */ - GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ - GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ - GPIO_NC, /* S0-SC082 - NC */ - GPIO_NC, /* S0-SC083 - NC */ - GPIO_NC, /* S0-SC084 - NC */ - GPIO_NC, /* S0-SC085 - NC */ - GPIO_NC, /* S0-SC086 - NC */ - GPIO_NC, /* S0-SC087 - NC */ - GPIO_NC, /* S0-SC088 - NC */ - GPIO_NC, /* S0-SC089 - NC */ - GPIO_NC, /* S0-SC090 - NC */ - GPIO_NC, /* S0-SC091 - NC */ - GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ - GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ - GPIO_NC, /* S0-SC094 - NC */ - GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ - GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ - GPIO_NC, /* S0-SC097 - NC */ - GPIO_NC, /* S0-SC098 - NC */ - GPIO_NC, /* S0-SC099 - NC */ - GPIO_NC, /* S0-SC100 - NC */ - GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ - GPIO_END -}; - -/* SSUS GPIOs */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ - GPIO_NC, /* S501 - NC */ - GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ - GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ - GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ - GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ - GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ - GPIO_INPUT, /* S508 - SOC_RECOVER- */ - GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ - GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ - GPIO_FUNC0, /* S511 - SUSPWRDNACK */ - GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ - GPIO_FUNC0, /* S513 - SLP_SX */ - GPIO_NC, /* S514 - NC */ - GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ - GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ - GPIO_NC, /* S517 - NC */ - GPIO_FUNC0, /* S518 - SUS_STAT# */ - GPIO_FUNC0, /* S519 - USB_OC0# */ - GPIO_FUNC0, /* S520 - USB_OC1# */ - GPIO_NC, /* S521 - NC */ - GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ - GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ - GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ - GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ - GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ - GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ - GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ - GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ - GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ - GPIO_NC, /* S531 - NC */ - GPIO_NC, /* S532 - NC */ - GPIO_NC, /* S533 - NC */ - GPIO_NC, /* S534 - NC */ - GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ - GPIO_NC, /* S536 - NC */ - GPIO_INPUT, /* S537 - RAM_ID0 */ - GPIO_INPUT, /* S538 - RAM_ID1 */ - GPIO_INPUT, /* S539 - RAM_ID2 */ - GPIO_NC, /* S540 - NC */ - GPIO_NC, /* S541 - NC */ - GPIO_NC, /* S542 - NC */ - GPIO_NC, /* S543 - NC */ - GPIO_END -}; - -static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { - [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, -}; - -static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { - [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = &core_dedicated_irq, - .sus_dirq = &sus_dedicated_irq, -}; - -struct soc_gpio_config* mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/google/ninja/irqroute.c b/src/mainboard/google/ninja/irqroute.c deleted file mode 100644 index db8c512..0000000 --- a/src/mainboard/google/ninja/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/ninja/irqroute.h b/src/mainboard/google/ninja/irqroute.h deleted file mode 100644 index 988aaf4..0000000 --- a/src/mainboard/google/ninja/irqroute.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/irq.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) - -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, DISABLE), \ - PIRQ_PIC(B, DISABLE), \ - PIRQ_PIC(C, DISABLE), \ - PIRQ_PIC(D, DISABLE), \ - PIRQ_PIC(E, DISABLE), \ - PIRQ_PIC(F, DISABLE), \ - PIRQ_PIC(G, DISABLE), \ - PIRQ_PIC(H, DISABLE) - -/* CORE bank DIRQs - up to 16 supported */ -#define I8042_IRQ_OFFSET 2 -/* Corresponding SCORE GPIO pins */ -#define I8042_IRQ_GPIO 101 - -/* SUS bank DIRQs - up to 16 supported */ -#define CODEC_IRQ_OFFSET 0 -/* Corresponding SUS GPIO pins */ -#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/ninja/lan.c b/src/mainboard/google/ninja/lan.c deleted file mode 100644 index dad8692..0000000 --- a/src/mainboard/google/ninja/lan.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <string.h> -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <fmap.h> -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", - *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_DEBUG, - "Error: Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(NINJA_NIC_VENDOR_ID, - NINJA_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((NINJA_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/ninja/mainboard.c b/src/mainboard/google/ninja/mainboard.c deleted file mode 100644 index df9ecfa..0000000 --- a/src/mainboard/google/ninja/mainboard.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <smbios.h> -#include "ec.h" -#include "onboard.h" -#include <soc/gpio.h> -#include <bootstate.h> -#include <vendorcode/google/chromeos/chromeos.h> - -void mainboard_suspend_resume(void) -{ -} - -#if CONFIG_VGA_ROM_RUN -static int int15_handler(void) -{ - int res = 1; - - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); - - switch (X86_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default - */ - X86_AX = 0x005f; - X86_CX = 0x0001; - res = 1; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV - * bit 2 = EFP (HDMI) - * bit 3 = LFP (eDP)* - * bit 4 = CRT2 - * bit 5 = TV2 - * bit 6 = EFP2 - * bit 7 = LFP2 - */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - X86_AX = 0x005f; - X86_CX = 0x0003; - res = 1; - break; - case 0x5f70: - switch ((X86_CX >> 8) & 0xff) { - case 0: - /* Get Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 1: - /* Set Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 2: - /* Get SG/Non-SG mode */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", - ((X86_CX >> 8) & 0xff)); - break; - } - break; - - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); - break; - } - return res; -} -#endif - -static void mainboard_init(device_t dev) -{ - mainboard_ec_init(); - lan_init(); -} - -static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) -{ - return 0; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if CONFIG_VGA_ROM_RUN - /* Install custom int15 handler for VGA OPROM */ - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -static void edp_vdden_cb(void *unused) -{ - ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL); diff --git a/src/mainboard/google/ninja/mainboard_smi.c b/src/mainboard/google/ninja/mainboard_smi.c deleted file mode 100644 index 2669406..0000000 --- a/src/mainboard/google/ninja/mainboard_smi.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <elog.h> - -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -#include <soc/nvs.h> -#include <soc/pmc.h> - -/* The wake gpio is SUS_GPIO[0]. */ -#define WAKE_GPIO_EN SUS_GPIO_EN0 - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; -} - -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - -/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that - * this includes the enable bits in the lower 16 bits. */ -void mainboard_smi_gpi(uint32_t alt_gpio_smi) -{ - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -} - -void mainboard_smi_sleep(uint8_t slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - /* Enable wake pin in GPE block. */ - enable_gpe(WAKE_GPIO_EN); - break; - case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); -} - -int mainboard_smi_apmc(uint8_t apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } - return 0; -} diff --git a/src/mainboard/google/ninja/onboard.h b/src/mainboard/google/ninja/onboard.h deleted file mode 100644 index 5a01bb4..0000000 --- a/src/mainboard/google/ninja/onboard.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#include "irqroute.h" - -#ifndef __ACPI__ -void lan_init(void); -#endif - -/* defines for programming the MAC address */ -#define NINJA_NIC_VENDOR_ID 0x10EC -#define NINJA_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define NINJA_NIC_LED_MODE 0x00 - -/* PCH wake signal from EC. */ -#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) - -#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) -#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) - -#endif diff --git a/src/mainboard/google/ninja/romstage.c b/src/mainboard/google/ninja/romstage.c deleted file mode 100644 index 271d144..0000000 --- a/src/mainboard/google/ninja/romstage.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/mrc_wrapper.h> -#include <soc/romstage.h> - -/* - * RAM_ID[2:0] are on GPIO_SSUS[39:37] - * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz - * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz - * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - */ -static const uint32_t dual_channel_config = - (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); - -#define SPD_SIZE 256 -#define GPIO_SSUS_37_PAD 57 -#define GPIO_SSUS_38_PAD 50 -#define GPIO_SSUS_39_PAD 58 - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) -{ - int ram_id = 0; - - /* The ram_id[2:0] pullups on ninja are too large for the default 20K - * pulldown on the pad. Therefore, disable the internal pull resistor to - * read high values correctly. */ - ssus_disable_internal_pull(GPIO_SSUS_37_PAD); - ssus_disable_internal_pull(GPIO_SSUS_38_PAD); - ssus_disable_internal_pull(GPIO_SSUS_39_PAD); - - ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); - ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); - ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); - - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - - if (ram_id >= total_spds) - return NULL; - - /* Single channel configs */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; - - return &spd_file_content[SPD_SIZE * ram_id]; -} - -void mainboard_romstage_entry(struct romstage_params *rp) -{ - void *spd_content; - int dual_channel = 0; - void *spd_file; - size_t spd_fsize; - - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; - - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); - if (!spd_file) - die("SPD data not found."); - - /* Both channels are always present. */ - spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, - &dual_channel); - mp.mainboard.dram_data[0] = spd_content; - if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; - - rp->mrc_params = &mp; - romstage_common(rp); -} diff --git a/src/mainboard/google/ninja/spd/Makefile.inc b/src/mainboard/google/ninja/spd/Makefile.inc deleted file mode 100644 index b2552d3..0000000 --- a/src/mainboard/google/ninja/spd/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -SPD_BIN = $(obj)/spd.bin - -# Order matters for SPD sources. The following indicies -# define the SPD data to use. -# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz -# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz -# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz -# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz -# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz -# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz -SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA -SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 -SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA -SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex deleted file mode 100644 index 4bd8e0e..0000000 --- a/src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 03 11 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -00 05 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 22 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 41 5f -48 4d 54 33 31 32 53 36 -44 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex deleted file mode 100644 index ff4fd29..0000000 --- a/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 ff ab -48 4d 54 34 32 35 53 36 -41 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex b/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex deleted file mode 100644 index 8ced790..0000000 --- a/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Hynix HMT425S6CFR6A-PBA -92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 -48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 -20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex deleted file mode 100644 index f99c92a..0000000 --- a/src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 03 11 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 86 -50 00 3c 3c 01 40 83 05 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2c 00 -00 00 00 00 00 00 6a 15 -34 4b 54 46 32 35 36 36 -34 48 5a 2d 31 47 36 45 -31 20 45 31 80 2c 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex deleted file mode 100644 index f3bcb56..0000000 --- a/src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 04 19 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 86 -20 08 3c 3c 01 40 83 05 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2c 00 -00 00 00 00 00 00 19 d2 -34 4b 54 46 32 35 36 36 -34 48 5a 2d 31 47 36 45 -31 20 45 31 80 2c 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/ninja/w25q64.c b/src/mainboard/google/ninja/w25q64.c deleted file mode 100644 index a9ed8ac..0000000 --- a/src/mainboard/google/ninja/w25q64.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/spi.h> - -/* - * SPI lockdown configuration W25Q64FW. - */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) -#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) - -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, - .lvscc = SPI_VSCC, - .uvscc = SPI_VSCC, -}; - -int mainboard_get_spi_config(struct spi_config *cfg) -{ - memcpy(cfg, &spi_config, sizeof(*cfg)); - - return 0; -} diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 94354c9..a2bdc43 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -1,7 +1,6 @@ -if BOARD_GOOGLE_RAMBI -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_GOOGLE_BASEBOARD_RAMBI + def_bool n select SOC_INTEL_BAYTRAIL select EC_GOOGLE_CHROMEEC select ENABLE_BUILTIN_COM1 @@ -12,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM +if BOARD_GOOGLE_BASEBOARD_RAMBI + config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES select EC_SOFTWARE_SYNC @@ -23,13 +24,39 @@ config MAINBOARD_DIR string default google/rambi +config VARIANT_DIR + string + default "enguarde" if BOARD_GOOGLE_ENGUARDE + default "ninja" if BOARD_GOOGLE_NINJA + default "rambi" if BOARD_GOOGLE_RAMBI + config MAINBOARD_PART_NUMBER string - default "Rambi" + default "Enguarde" if BOARD_GOOGLE_ENGUARDE + default "Ninja" if BOARD_GOOGLE_NINJA + default "Rambi" if BOARD_GOOGLE_RAMBI + +config GBB_HWID + string + depends on CHROMEOS + default "ENGUARDE TEST A-A 0128" if BOARD_GOOGLE_ENGUARDE + default "NINJA TEST A-A 0653" if BOARD_GOOGLE_NINJA + default "RAMBI TEST A-A 0128" if BOARD_GOOGLE_RAMBI + +config DEVICETREE + string + default "variants/enguarde/devicetree.cb" if BOARD_GOOGLE_ENGUARDE + default "variants/ninja/devicetree.cb" if BOARD_GOOGLE_NINJA + default "variants/rambi/devicetree.cb" if BOARD_GOOGLE_RAMBI + +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "rambi" if BOARD_GOOGLE_RAMBI + default "" config VGA_BIOS_FILE string - default "pci8086,0166.rom" + default "pci8086,0f31.rom" config HAVE_IFD_BIN bool @@ -39,12 +66,4 @@ config HAVE_ME_BIN bool default n -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "rambi" - -config GBB_HWID - string - depends on CHROMEOS - default "RAMBI TEST A-A 0128" -endif # BOARD_GOOGLE_RAMBI +endif # BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name index b1b0b6a..0305bc4 100644 --- a/src/mainboard/google/rambi/Kconfig.name +++ b/src/mainboard/google/rambi/Kconfig.name @@ -1,2 +1,11 @@ +config BOARD_GOOGLE_ENGUARDE + bool "Enguarde" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_NINJA + bool "Ninja" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_RAMBI bool "Rambi" + select BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 65221ac..b08002d 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -13,13 +13,18 @@ ## GNU General Public License for more details. ## -subdirs-y += spd - -romstage-y += chromeos.c -ramstage-y += chromeos.c -ramstage-y += gpio.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += irqroute.c ramstage-y += w25q64.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c + +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index 0b79aad..673ad1c 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -11,34 +11,8 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 - -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 - -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) +/* Include variant DPTF */ +#include <variant/acpi/dptf.asl> /* Mainboard specific _PDL is 1GHz */ Name (MPDL, 8) @@ -83,5 +57,5 @@ Name (MPPC, Package () } }) -/* Include Baytrail DPTF */ +/* Include SoC DPTF */ #include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/rambi/acpi/lightsensor_lsd.asl b/src/mainboard/google/rambi/acpi/lightsensor_lsd.asl new file mode 100644 index 0000000..057f8dc --- /dev/null +++ b/src/mainboard/google/rambi/acpi/lightsensor_lsd.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_ALS_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C5", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 7236c93..bd747d4 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <mainboard/google/rambi/onboard.h> +#include <variant/onboard.h> Scope (\_SB) { @@ -34,7 +34,7 @@ Scope (\_SB) Name (_HID, EisaId ("PNP0C0C")) Name (_UID, 1) } - +#ifdef BOARD_TRACKPAD_IRQ /* Wake device for touchpad */ Device (TPAD) { @@ -52,7 +52,7 @@ Scope (\_SB) Method (_CRS) { - /* Return interrupt if I2C1 is PCI mode */ + /* Only return interrupt if I2C1 is PCI mode */ If (LEqual (\S1EN, 0)) { Return (^RBUF) } @@ -61,7 +61,8 @@ Scope (\_SB) Return (ResourceTemplate() {}) } } - +#endif +#ifdef BOARD_TOUCHSCREEN_IRQ /* Wake device for touchscreen */ Device (TSCR) { @@ -88,114 +89,7 @@ Scope (\_SB) Return (ResourceTemplate() {}) } } -} - -Scope (\_SB.I2C1) -{ - Device (ATPB) - { - Name (_HID, "ATML0000") - Name (_DDN, "Atmel Touchpad Bootloader") - Name (_UID, 1) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x25, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C1", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } - - Device (ATPA) - { - Name (_HID, "ATML0000") - Name (_DDN, "Atmel Touchpad") - Name (_UID, 2) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x4b, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C1", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } - - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 3) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C1", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } +#endif } Scope (\_SB.I2C2) @@ -238,119 +132,6 @@ Scope (\_SB.I2C2) } } -Scope (\_SB.I2C5) -{ - Device (ALSI) - { - /* - * TODO(dlaurie): Need official HID. - * - * The current HID is created from the Intersil PNP - * Vendor ID "LSD" and a shortened device identifier. - */ - Name (_HID, EisaId ("LSD2918")) - Name (_DDN, "Intersil 29018 Ambient Light Sensor") - Name (_UID, 1) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x44, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C5", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_ALS_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S5EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} - -Scope (\_SB.I2C6) -{ - Device (ATSB) - { - Name (_HID, "ATML0001") - Name (_DDN, "Atmel Touchscreen Bootloader") - Name (_UID, 4) - Name (ISTP, 0) /* TouchScreen */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x26, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C6", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } - - Device (ATSA) - { - Name (_HID, "ATML0001") - Name (_DDN, "Atmel Touchscreen") - Name (_UID, 5) - Name (ISTP, 0) /* TouchScreen */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x4a, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C6", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - Scope (\_SB.LPEA) { Name (GBUF, ResourceTemplate () @@ -364,3 +145,5 @@ Scope (\_SB.LPEA) "\\_SB.GPSC") { 15 } }) } + +#include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl index bd52051..adc34aa 100644 --- a/src/mainboard/google/rambi/acpi/superio.asl +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -13,14 +13,17 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ +/* Baseboard configuration */ #include <mainboard/google/rambi/ec.h> -#include <mainboard/google/rambi/onboard.h> #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -// Override default IRQ settings + +/* Variant configuration */ +#include <variant/onboard.h> + +/* Override default IRQ settings */ #define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ} /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl b/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl new file mode 100644 index 0000000..5ae46f8 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C6) +{ + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_CID, EisaId ("PNP0C0E")) + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + } +} diff --git a/src/mainboard/google/rambi/acpi/trackpad_amtel.asl b/src/mainboard/google/rambi/acpi/trackpad_amtel.asl new file mode 100644 index 0000000..97c53d2 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/trackpad_amtel.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C1) +{ + Device (ATPA) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") + Name (_UID, 2) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/acpi/trackpad_elan.asl b/src/mainboard/google/rambi/acpi/trackpad_elan.asl new file mode 100644 index 0000000..16a9a48 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/trackpad_elan.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C1) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/board_info.txt b/src/mainboard/google/rambi/board_info.txt index 3e630d3..8463812 100644 --- a/src/mainboard/google/rambi/board_info.txt +++ b/src/mainboard/google/rambi/board_info.txt @@ -1,3 +1,7 @@ +Vendor name: Google +Board name: Rambi Baytrail Reference Board Category: laptop +ROM package: SOIC-8 ROM protocol: SPI +ROM socketed: n Flashrom support: y diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb deleted file mode 100644 index 5914a62..0000000 --- a/src/mainboard/google/rambi/devicetree.cb +++ /dev/null @@ -1,102 +0,0 @@ -chip soc/intel/baytrail - - # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" - register "sata_ahci" = "0x1" - register "ide_legacy_combined" = "0x0" - - # Route USB ports to XHCI - register "usb_route_to_xhci" = "1" - - # USB Port Disable Mask - register "usb2_port_disable_mask" = "0x0" - register "usb3_port_disable_mask" = "0x0" - - # USB PHY settings - # TODO: These values are from Baytrail and need tuned for Rambi board - register "usb2_per_port_lane0" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" - register "usb2_per_port_lane1" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" - register "usb2_per_port_lane2" = "0x00049209" - register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" - register "usb2_per_port_lane3" = "0x00049a09" - register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" - register "usb2_comp_bg" = "0x4700" - - # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] - - # SD Card controller - register "sdcard_cap_low" = "0x036864b2" - register "sdcard_cap_high" = "0x0" - - # Enable devices in ACPI mode - register "lpe_acpi_mode" = "1" - register "lpss_acpi_mode" = "1" - register "scc_acpi_mode" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - # Enable PIPEA as DP_C - register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "6" # 600ms - register "gpu_pipea_power_on_delay" = "5000" # 500ms - register "gpu_pipea_light_on_delay" = "70" # 7ms - register "gpu_pipea_power_off_delay" = "500" # 50ms - register "gpu_pipea_light_off_delay" = "2000" # 200ms - - # VR PS2 control - register "vnn_ps2_enable" = "1" - register "vcc_ps2_enable" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 11.0 off end # SDIO - device pci 12.0 on end # SD - device pci 13.0 on end # SATA - device pci 14.0 on end # XHCI - device pci 15.0 on end # LPE - device pci 17.0 on end # MMC - device pci 18.0 on end # SIO_DMA1 - device pci 18.1 on end # I2C1 - device pci 18.2 on end # I2C2 - device pci 18.3 off end # I2C3 - device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 - device pci 18.6 on end # I2C6 - device pci 18.7 off end # I2C7 - device pci 1a.0 on end # TXE - device pci 1b.0 on end # HDA - device pci 1c.0 on end # PCIE_PORT1 - device pci 1c.1 on end # PCIE_PORT2 - device pci 1c.2 off end # PCIE_PORT3 - device pci 1c.3 off end # PCIE_PORT4 - device pci 1d.0 on end # EHCI - device pci 1e.0 on end # SIO_DMA2 - device pci 1e.1 off end # PWM1 - device pci 1e.2 off end # PWM2 - device pci 1e.3 off end # HSUART1 - device pci 1e.4 off end # HSUART2 - device pci 1e.5 off end # SPI - device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC Bridge - device pci 1f.3 off end # SMBus - end -end diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c deleted file mode 100644 index dfbc390..0000000 --- a/src/mainboard/google/rambi/gpio.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <soc/gpio.h> -#include "irqroute.h" - -/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */ -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ - GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ - GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ - GPIO_NC, /* S0_NC03 - NC */ - GPIO_NC, /* S0_NC04 - NC */ - GPIO_NC, /* S0_NC05 - NC */ - GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ - GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ - GPIO_NC, /* S0_NC08 - NC */ - GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ - GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ - GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ - GPIO_NC, /* S0_NC12 - NC */ - GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ - GPIO_NC, /* S0_NC14 - NC */ - GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ - GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ - GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ - GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ - GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ - GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ - GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ - GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ - GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ - GPIO_NC, /* S0_NC24 - NC */ - GPIO_NC, /* S0_NC25 - NC */ - GPIO_NC, /* S0_NC26 - NC */ - GPIO_END -}; - -/* SCORE GPIOs */ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ - GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ - GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ - GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ - GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ - GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ - GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ - GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ - GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ - GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ - GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ - GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ - GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ - GPIO_NC, /* S0-SC013 - NC */ - GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ - GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ - GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ - GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ - GPIO_NC, /* S0-SC027 - NC */ - GPIO_NC, /* S0-SC028 - NC */ - GPIO_NC, /* S0-SC029 - NC */ - GPIO_NC, /* S0-SC030 - NC */ - GPIO_NC, /* S0-SC031 - NC */ - GPIO_NC, /* S0-SC032 - NC */ - GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ - GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ - GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ - GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ - GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ - GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ - GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ - GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ - GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ - GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ - GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ - GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ - GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ - GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ - GPIO_DEFAULT, /* S0-SC054 - NC */ - GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ - GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ - GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ - GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ - GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ - GPIO_NC, /* S0-SC060 - NC */ - GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ - GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ - GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ - GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ - GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ - GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ - GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ - GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ - GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ - GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ - GPIO_NC, /* S0-SC071 - NC */ - GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ - GPIO_NC, /* S0-SC073 - NC */ - GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ - GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ - GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ - GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ - GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ - GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ - GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ - GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ - GPIO_NC, /* S0-SC082 - NC */ - GPIO_NC, /* S0-SC083 - NC */ - GPIO_NC, /* S0-SC084 - NC */ - GPIO_NC, /* S0-SC085 - NC */ - GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ - GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ - GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ - GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ - GPIO_NC, /* S0-SC090 - NC */ - GPIO_NC, /* S0-SC091 - NC */ - GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ - GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ - GPIO_NC, /* S0-SC094 - NC */ - GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ - GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ - GPIO_NC, /* S0-SC097 - NC */ - GPIO_NC, /* S0-SC098 - NC */ - GPIO_NC, /* S0-SC099 - NC */ - GPIO_NC, /* S0-SC100 - NC */ - GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ - GPIO_END -}; - -/* SSUS GPIOs */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ - GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ - GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ - GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ - GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ - GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ - GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ - GPIO_NC, /* S508 - NC */ - GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ - GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ - GPIO_FUNC0, /* S511 - SUSPWRDNACK */ - GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ - GPIO_FUNC0, /* S513 - SLP_SX */ - GPIO_NC, /* S514 - NC */ - GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ - GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ - GPIO_NC, /* S517 - NC */ - GPIO_FUNC0, /* S518 - SUS_STAT# */ - GPIO_FUNC0, /* S519 - USB_OC0# */ - GPIO_FUNC0, /* S520 - USB_OC1# */ - GPIO_NC, /* S521 - NC */ - GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ - GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ - GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ - GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ - GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ - GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ - GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ - GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ - GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ - GPIO_NC, /* S531 - NC */ - GPIO_NC, /* S532 - NC */ - GPIO_NC, /* S533 - NC */ - GPIO_NC, /* S534 - NC */ - GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ - GPIO_NC, /* S536 - NC */ - GPIO_INPUT, /* S537 - RAM_ID0 */ - GPIO_INPUT, /* S538 - RAM_ID1 */ - GPIO_INPUT, /* S539 - RAM_ID2 */ - GPIO_NC, /* S540 - NC */ - GPIO_NC, /* S541 - NC */ - GPIO_NC, /* S542 - NC */ - GPIO_NC, /* S543 - NC */ - GPIO_END -}; - -static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { - [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, - [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, - [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, - [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, -}; - -static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { - [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = &core_dedicated_irq, - .sus_dirq = &sus_dedicated_irq, -}; - -struct soc_gpio_config* mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index adbfd96..eaf3079 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -31,7 +31,7 @@ #include <boot/coreboot_tables.h> #include <smbios.h> #include "ec.h" -#include "onboard.h" +#include <variant/onboard.h> #include <soc/gpio.h> #include <bootstate.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -129,13 +129,16 @@ static int int15_handler(void) static void mainboard_init(device_t dev) { mainboard_ec_init(); +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) + lan_init(); +#endif } static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *current) { int len = 0; - +#ifdef BOARD_TRACKPAD_NAME len += smbios_write_type41( current, handle, BOARD_TRACKPAD_NAME, /* name */ @@ -144,7 +147,8 @@ static int mainboard_smbios_data(device_t dev, int *handle, BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ - +#endif +#ifdef BOARD_TOUCHSCREEN_NAME len += smbios_write_type41( current, handle, BOARD_TOUCHSCREEN_NAME, /* name */ @@ -153,7 +157,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ - +#endif return len; } diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h deleted file mode 100644 index 04ed332..0000000 --- a/src/mainboard/google/rambi/onboard.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#include "irqroute.h" - -/* PCH wake signal from EC. */ -#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) -#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) -#define BOARD_TRACKPAD_I2C_BUS 0 -#define BOARD_TRACKPAD_I2C_ADDR 0x4b - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) -#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) -#define BOARD_TOUCHSCREEN_I2C_BUS 5 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ - -#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) -#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) -#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) - -#endif diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index e9dba81..152d5e6 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -20,29 +20,13 @@ #include <soc/gpio.h> #include <soc/mrc_wrapper.h> #include <soc/romstage.h> - -/* - * RAM_ID[2:0] are on GPIO_SSUS[39:37] - * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz - * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz - * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - */ -static const uint32_t dual_channel_config = - (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); - -#define SPD_SIZE 256 -#define GPIO_SSUS_37_PAD 57 -#define GPIO_SSUS_38_PAD 50 -#define GPIO_SSUS_39_PAD 58 +#include <variant/variant.h> static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; - /* The ram_id[2:0] pullups on rambi are too large for the default 20K + /* The ram_id[2:0] pullups are too large for the default 20K * pulldown on the pad. Therefore, disable the internal pull resistor to * read high values correctly. */ ssus_disable_internal_pull(GPIO_SSUS_37_PAD); diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc deleted file mode 100644 index 85956b0..0000000 --- a/src/mainboard/google/rambi/spd/Makefile.inc +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -SPD_BIN = $(obj)/spd.bin - -# Order matters for SPD sources. The following indicies -# define the SPD data to use. -# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz -# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz -# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz -# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz -# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz -SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA -SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 -SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA -SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 -SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex b/src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex new file mode 100644 index 0000000..96cf568 --- /dev/null +++ b/src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B2G1646Q-BYK0 +92 12 0B 03 03 11 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 00 05 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 20 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 +4b 34 42 32 47 31 36 34 36 51 2d 42 59 4b 30 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..ac9a0e0 --- /dev/null +++ b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646Q-HYK0 +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc new file mode 100644 index 0000000..5e0042a --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb new file mode 100644 index 0000000..f3792fe --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Enguarde board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c new file mode 100644 index 0000000..2802aa6 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_NC, /* S0-SC088 - I2C_5_SDA */ + GPIO_NC, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC(6, PULL_UP, 20K), /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..e9b78a8 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..59aff66 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Intersil light sensor */ +#include <mainboard/google/rambi/acpi/lightsensor_lsd.asl> \ No newline at end of file diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h new file mode 100644 index 0000000..1477794 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#define BOARD_ALS_I2C_ADDR 0x44 + +#endif diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h new file mode 100644 index 0000000..08e7563 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/ninja/Makefile.inc b/src/mainboard/google/rambi/variants/ninja/Makefile.inc new file mode 100644 index 0000000..b2552d3 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb new file mode 100644 index 0000000..6d56130 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Ninja board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/ninja/gpio.c b/src/mainboard/google/rambi/variants/ninja/gpio.c new file mode 100644 index 0000000..85d565e --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/gpio.c @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_FUNC2, /* S0_NC07 - DDI1_DDCDATA */ + GPIO_FUNC2, /* S0_NC08 - DDI1_DDCCLK */ + GPIO_NC, /* S0_NC09 - NC */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_NC, /* S0_SC001 - NC */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE0# */ + GPIO_NC, /* S0-SC004 - NC# */ + GPIO_FUNC1, /* S0-SC005 - PCIE_CLKREQ_WLAN# */ + GPIO_FUNC1, /* S0-SC006 - PCIE_CLKREQ_LAN# */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_FUNC1, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_FUNC1, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_NC, /* S0-SC055 - NC */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - NC */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_NC, /* S0-SC076 - NC */ + GPIO_NC, /* S0-SC077 - NC */ + GPIO_NC, /* S0-SC078 - NC */ + GPIO_NC, /* S0-SC079 - NC */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - NC */ + GPIO_NC, /* S0-SC087 - NC */ + GPIO_NC, /* S0-SC088 - NC */ + GPIO_NC, /* S0-SC089 - NC */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_NC, /* S501 - NC */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_INPUT, /* S508 - SOC_RECOVER- */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..7ab3356 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 80 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h new file mode 100644 index 0000000..ec8bcd6 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +#ifndef __ACPI__ +void lan_init(void); +#endif + +/* defines for programming the MAC address */ +#define NINJA_NIC_VENDOR_ID 0x10EC +#define NINJA_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define NINJA_NIC_LED_MODE 0x00 + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +/* Disable PS2 keyboard */ +#undef SIO_EC_ENABLE_PS2K + +#endif diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h new file mode 100644 index 0000000..8d2113c --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c new file mode 100644 index 0000000..3d08ad7 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <variant/onboard.h> + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(NINJA_NIC_VENDOR_ID, + NINJA_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((NINJA_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/rambi/variants/rambi/Makefile.inc b/src/mainboard/google/rambi/variants/rambi/Makefile.inc new file mode 100644 index 0000000..85956b0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb new file mode 100644 index 0000000..5914a62 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Rambi board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/rambi/gpio.c b/src/mainboard/google/rambi/variants/rambi/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..d07ac41 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..acacc5f --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Amtel trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_amtel.asl> + +/* Amtel touchscreen trackpad */ +#include <mainboard/google/rambi/acpi/touchscreen_amtel.asl> diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h b/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h new file mode 100644 index 0000000..b3332a3 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x4b + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h new file mode 100644 index 0000000..44ae0cf --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif

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coreboot-gerrit January 2017