coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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852 discussions

Patch set updated for coreboot: mainboard/google/poppy: Update DQS and DQ Byte mappings for poppy
by Rizwan Qureshi 13 Jan '17

13 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18133 -gerrit commit 445811321d47ca92e52e3b91109339fc52205991 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 12:45:19 2017 +0530 mainboard/google/poppy: Update DQS and DQ Byte mappings for poppy poppy schematics have undergone change after review, update DQS and DQ Byte mappings based on the new schematics. BUG=chrome-os-partner:61856 BRANCH=None TEST= Build and boot all the poppy proto SKUs to OS. Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 70e93d8..790e5ae 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -25,14 +25,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; /* DQ byte map */ const u8 dq_map[2][12] = { - { 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33, + { 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33, 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - { 0, 3, 1, 2, 4, 7, 6, 5 }, + { 2, 3, 1, 0, 4, 7, 6, 5 }, { 5, 6, 0, 3, 4, 7, 2, 1 }, }; /* Rcomp resistor */

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Patch set updated for coreboot: mb/google/poppy: Enable dptf
by Sumeet R Pawnikar 13 Jan '17

13 Jan '17

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17926 -gerrit commit cb47ed3181d4a4baf36a3bd2a3d99d629ed88dfb Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Fri Jan 13 20:05:16 2017 +0530 mb/google/poppy: Enable dptf DPTF Participants: 1. B0D4 2. Battery Charger Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/mainboard/google/poppy/acpi/dptf.asl | 58 ++++++++++++++++++++++++++++++++ src/mainboard/google/poppy/devicetree.cb | 4 +++ src/mainboard/google/poppy/dsdt.asl | 3 ++ 3 files changed, 65 insertions(+) diff --git a/src/mainboard/google/poppy/acpi/dptf.asl b/src/mainboard/google/poppy/acpi/dptf.asl new file mode 100644 index 0000000..3fba587 --- /dev/null +++ b/src/mainboard/google/poppy/acpi/dptf.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 94 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 3000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 4283a34..481900c 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -19,6 +19,9 @@ chip soc/intel/skylake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" @@ -184,6 +187,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_pl2_override" = "7" + register "tcc_offset" = "10" # TCC of 90C device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index c678dfc..ed97848 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -45,6 +45,9 @@ DefinitionBlock( #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" } /* Chrome OS specific */

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Patch merged into coreboot/master: util/cbfstool: Enable adding precompressed files to cbfs
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit ecaa570b60a27d0b1d4c9742013d65591a0ecc92 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 11 18:38:11 2017 +0100 util/cbfstool: Enable adding precompressed files to cbfs cbfstool ... add ... -c precompression assumes the input file to be created by cbfs-compression-tool's compress command and uses that to add the file with correct metadata. When adding the locale_*.bin files to Chrome OS images, this provides a nice speedup (since we can parallelize the precompression and avoid compressing everything twice) while creating a bit-identical file. Change-Id: Iadd106672c505909528b55e2cd43c914b95b6c6d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18102 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18102 for details. -gerrit

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New patch to review for coreboot: util/cbfstool: avoid memleaks and off-by-ones
by Patrick Georgi 13 Jan '17

13 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18134 -gerrit commit 615d332d1039026e6e3c9edd7972bea8d7d93eee Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jan 13 13:30:54 2017 +0100 util/cbfstool: avoid memleaks and off-by-ones Change-Id: Iac136a5dfe76f21aa7c0d5ee4e974e50b955403b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: scan-build 3.8 --- util/cbfstool/cbfs_image.c | 6 ++++++ util/cbfstool/cbfscomptool.c | 5 +++++ util/cbfstool/fmd.c | 2 +- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index e530224..da0335e 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1149,14 +1149,18 @@ static int cbfs_payload_make_elf(struct buffer *buff, uint32_t arch) buffer_splice(&tbuff, buff, segs[i].offset, segs[i].len); } else if (segs[i].type == PAYLOAD_SEGMENT_ENTRY) { + if (name) free(name); break; } if (elf_writer_add_section(ew, &shdr, &tbuff, name)) { ERROR("Unable to add ELF section: %s\n", name); + if (name) free(name); goto out; } + if (name) free(name); + name = NULL; if (empty_sz != 0) { struct buffer b; @@ -1170,8 +1174,10 @@ static int cbfs_payload_make_elf(struct buffer *buff, uint32_t arch) name = strdup(".empty"); if (elf_writer_add_section(ew, &shdr, &b, name)) { ERROR("Unable to add ELF section: %s\n", name); + if (name) free(name); goto out; } + if (name) free(name); } } diff --git a/util/cbfstool/cbfscomptool.c b/util/cbfstool/cbfscomptool.c index 1aa1699..b7a4b1b 100644 --- a/util/cbfstool/cbfscomptool.c +++ b/util/cbfstool/cbfscomptool.c @@ -49,6 +49,7 @@ int benchmark() } char *compressed_data = malloc(bufsize); if (!compressed_data) { + free(data); fprintf(stderr, "out of memory\n"); return 1; } @@ -64,6 +65,8 @@ int benchmark() comp_func_ptr comp = compression_function(algo->type); if (comp == NULL) { printf("no handler associated with algorithm\n"); + free(data); + free(compressed_data); return 1; } @@ -80,6 +83,8 @@ int benchmark() bufsize, outsize, t_e.tv_sec - t_s.tv_sec); } + free(data); + free(compressed_data); return 0; } diff --git a/util/cbfstool/fmd.c b/util/cbfstool/fmd.c index afd8701..7a289d7 100644 --- a/util/cbfstool/fmd.c +++ b/util/cbfstool/fmd.c @@ -289,7 +289,7 @@ static void print_with_prefix(const struct flashmap_descriptor *tree, if (tree->list_len) { puts(":"); - char child_prefix[strlen(pre) + 1]; + char child_prefix[strlen(pre) + 2]; strcpy(child_prefix, pre); strcat(child_prefix, "\t"); fmd_foreach_child(each, tree)

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Patch set updated for coreboot: util/cbfstool: Enable adding precompressed files to cbfs
by Patrick Georgi 13 Jan '17

13 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18102 -gerrit commit 6d7ed75999361112815c1c234f38d61f2409a658 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 11 18:38:11 2017 +0100 util/cbfstool: Enable adding precompressed files to cbfs cbfstool ... add ... -c precompression assumes the input file to be created by cbfs-compression-tool's compress command and uses that to add the file with correct metadata. When adding the locale_*.bin files to Chrome OS images, this provides a nice speedup (since we can parallelize the precompression and avoid compressing everything twice) while creating a bit-identical file. Change-Id: Iadd106672c505909528b55e2cd43c914b95b6c6d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfstool.c | 67 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 45 insertions(+), 22 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index de50ff3..9b5343e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -79,6 +79,7 @@ static struct param { bool machine_parseable; int fit_empty_entries; enum comp_algo compression; + int precompression; enum vb2_hash_algorithm hash; /* for linux payloads */ char *initrd; @@ -439,33 +440,51 @@ static int cbfstool_convert_raw(struct buffer *buffer, unused uint32_t *offset, struct cbfs_file *header) { char *compressed; - int compressed_size; - - comp_func_ptr compress = compression_function(param.compression); - if (!compress) - return -1; - compressed = calloc(buffer->size, 1); - - if (compress(buffer->data, buffer->size, - compressed, &compressed_size)) { - WARN("Compression failed - disabled\n"); + int decompressed_size, compressed_size; + comp_func_ptr compress; + + decompressed_size = buffer->size; + if (param.precompression) { + param.compression = le32toh(((uint32_t *)buffer->data)[0]); + decompressed_size = le32toh(((uint32_t *)buffer->data)[1]); + compressed_size = buffer->size - 8; + compressed = malloc(compressed_size); + if (!compressed) + return -1; + memcpy(compressed, buffer->data + 8, compressed_size); } else { - struct cbfs_file_attr_compression *attrs = - (struct cbfs_file_attr_compression *) - cbfs_add_file_attr(header, - CBFS_FILE_ATTR_TAG_COMPRESSION, - sizeof(struct cbfs_file_attr_compression)); - if (attrs == NULL) + compress = compression_function(param.compression); + if (!compress) + return -1; + compressed = calloc(buffer->size, 1); + if (!compressed) return -1; - attrs->compression = htonl(param.compression); - attrs->decompressed_size = htonl(buffer->size); - free(buffer->data); - buffer->data = compressed; - buffer->size = compressed_size; + if (compress(buffer->data, buffer->size, + compressed, &compressed_size)) { + WARN("Compression failed - disabled\n"); + free(compressed); + return 0; + } + } - header->len = htonl(buffer->size); + struct cbfs_file_attr_compression *attrs = + (struct cbfs_file_attr_compression *) + cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_COMPRESSION, + sizeof(struct cbfs_file_attr_compression)); + if (attrs == NULL) { + free(compressed); + return -1; } + attrs->compression = htonl(param.compression); + attrs->decompressed_size = htonl(decompressed_size); + + free(buffer->data); + buffer->data = compressed; + buffer->size = compressed_size; + + header->len = htonl(buffer->size); return 0; } @@ -1347,6 +1366,10 @@ int main(int argc, char **argv) optarg); break; case 'c': { + if (strcmp(optarg, "precompression") == 0) { + param.precompression = 1; + break; + } int algo = cbfs_parse_comp_algo(optarg); if (algo >= 0) param.compression = algo;

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New patch to review for coreboot: mainboard/google/poppy: Update DQS and DQ Byte mappings for poppy
by Rizwan Qureshi 13 Jan '17

13 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18133 -gerrit commit fc3baeae780e28be7026e7d17068c63a45d6ff22 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 12:45:19 2017 +0530 mainboard/google/poppy: Update DQS and DQ Byte mappings for poppy poppy schematics have undergone change after review, update DQS and DQ Byte mappings for poppy based on the new schematics. Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 70e93d8..790e5ae 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -25,14 +25,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; /* DQ byte map */ const u8 dq_map[2][12] = { - { 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33, + { 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33, 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - { 0, 3, 1, 2, 4, 7, 6, 5 }, + { 2, 3, 1, 0, 4, 7, 6, 5 }, { 5, 6, 0, 3, 4, 7, 2, 1 }, }; /* Rcomp resistor */

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Patch set updated for coreboot: fsp_baytrail: Enable graphic init per default
by Werner Zeh 12 Jan '17

12 Jan '17

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18109 -gerrit commit 57f1292e4246565faf22f4648ce9ee807747344e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:29:04 2017 +0100 fsp_baytrail: Enable graphic init per default Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni(a)kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 8 -------- src/soc/intel/fsp_baytrail/Makefile.inc | 2 +- 3 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 5ff233d..6a3b3c4 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES - select FSP_BAYTRAIL_GFX_INIT select USE_SIEMENS_HWILIB config MAINBOARD_DIR diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 689e625..549ea55 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -95,14 +95,6 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS -config FSP_BAYTRAIL_GFX_INIT - default n - bool - help - Enabling this option will activate graphics init code. With this init, - the graphic power gate registers will be initialized before - VBIOS is executed. - config CPU_MICROCODE_HEADER_FILES string default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 6e16b42..f086665 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -57,7 +57,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c -ramstage-$(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c +ramstage-y += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp

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Patch set updated for coreboot: fsp_baytrail: Enable graphic init per default
by Werner Zeh 12 Jan '17

12 Jan '17

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18109 -gerrit commit 70f5ba371de1ff9704e91696e595616bac0d781d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:29:04 2017 +0100 fsp_baytrail: Enable graphic init per default Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni(a)kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 7 ------- src/soc/intel/fsp_baytrail/Makefile.inc | 2 +- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 5ff233d..6a3b3c4 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES - select FSP_BAYTRAIL_GFX_INIT select USE_SIEMENS_HWILIB config MAINBOARD_DIR diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 689e625..94bfcc8 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -95,13 +95,6 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS -config FSP_BAYTRAIL_GFX_INIT - default n - bool - help - Enabling this option will activate graphics init code. With this init, - the graphic power gate registers will be initialized before - VBIOS is executed. config CPU_MICROCODE_HEADER_FILES string diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 6e16b42..f086665 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -57,7 +57,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c -ramstage-$(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c +ramstage-y += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp

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Patch set updated for coreboot: Run sdhci init on an AP in parallel
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18108 -gerrit commit 8ec9d900fee7b2c7be4d9a82cc3cd18cd93dcdc4 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed Jan 4 17:12:55 2017 -0800 Run sdhci init on an AP in parallel Initialize sdhci and setup mmc on AP. Put the sdhci in transfer mode and set a flag to let payload know that it can just resume operations. Let BSP run in parallel and do work until it is time to write coreboot tables. At that point, make BSP wait for AP to finish up. If AP fails to setup sdhci or mmc, let payload re-initialize everything. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: I86a8b3857685d8638c4cdcd865b16b9454496cb2 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/drivers/storage/sdhci.c | 6 ++++++ src/drivers/storage/sdhci.h | 2 ++ src/lib/coreboot_table.c | 3 +++ src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/mainboard.c | 38 +++++++++++++++++++++++++++++++++++ 5 files changed, 50 insertions(+) diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c index 54cc54d..88d7180 100644 --- a/src/drivers/storage/sdhci.c +++ b/src/drivers/storage/sdhci.c @@ -29,6 +29,8 @@ #include <timer.h> #include <string.h> +atomic_t sdhci_barrier = ATOMIC_INIT(0); + static void sdhci_reset(SdhciHost *host, u8 mask) { unsigned long timeout; @@ -718,4 +720,8 @@ void add_sdhci(SdhciHost *host) host->mmc_ctrlr.b_max = 65535; } +atomic_t* get_sdhci_barrier( void ) +{ + return &sdhci_barrier; +} diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h index c44edad..6ee7a8f 100644 --- a/src/drivers/storage/sdhci.h +++ b/src/drivers/storage/sdhci.h @@ -23,6 +23,7 @@ #include "mmc.h" #include <device/pci_ops.h> +#include <smp/atomic.h> /* * Controller registers @@ -346,6 +347,7 @@ static inline u8 sdhci_readb(SdhciHost *host, int reg) void add_sdhci(SdhciHost *host); int sdhci_init(SdhciHost *host); SdhciHost* sdhci_get_host_ptr( void ); +atomic_t* get_sdhci_barrier(void); /* Add SDHCI controller from PCI */ SdhciHost *new_pci_sdhci_host(struct device *dev, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 932c8fe..85595fc 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -16,6 +16,7 @@ */ #include <arch/cbconfig.h> +#include <cpu/x86/mp.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -161,6 +162,8 @@ static void lb_sdhci_host( struct lb_header *header ) struct lb_sdhci_host_info *lb_host; SdhciHost* host_ptr = sdhci_get_host_ptr(); + barrier_wait_timeout(get_sdhci_barrier(),500); + lb_host = (struct lb_sdhci_host_info *)lb_new_record(header); lb_host->tag = LB_TAG_SDHCI_HOST; diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 0766577..89c483e 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF select MAINBOARD_HAS_I2C_TPM_CR50 select TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION + select DRIVERS_STORAGE if BOARD_GOOGLE_BASEBOARD_REEF diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 702269c..e7a80cc 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -28,6 +28,41 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> +#include <drivers/storage/sdhci.h> +#include <cpu/cpu.h> +#include <cpu/x86/mp.h> +#include <soc/pci_devs.h> + +#define EMMC_SD_CLOCK_MIN 400000 +#define EMMC_CLOCK_MAX 200000000 +#define SD_CLOCK_MAX 52000000 + +static void platform_emmc_init(void) +{ + SdhciHost *host; + + host = new_pci_sdhci_host(EMMC_DEV, + SDHCI_PLATFORM_NO_EMMC_HS200, + EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX); + sdhci_init(host); + mmc_setup_media(&host->mmc_ctrlr,0); + host->initialized = 1; + + // Let BSP continue + release_barrier(get_sdhci_barrier()); +} + +static void run_on_single_ap(void) +{ + struct cpu_info *info; + + info = cpu_info(); + + if( info->index != 1 ) + return; + + platform_emmc_init(); +} static void mainboard_init(void *chip_info) { @@ -35,6 +70,9 @@ static void mainboard_init(void *chip_info) const struct pad_config *pads; size_t num; + if (mp_run_on_aps(&run_on_single_ap, 1000) < 0) + printk(BIOS_ERR, "failed to run sdhci init\n"); + boardid = board_id(); printk(BIOS_INFO, "Board ID: %d\n", boardid);

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Patch set updated for coreboot: Add a lock with timeout
by Bora Guvendik 12 Jan '17

12 Jan '17

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18107 -gerrit commit d4af553342746a054a696b04347932564e3f7541 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed Jan 4 16:51:31 2017 -0800 Add a lock with timeout In case something goes wrong on one of the cpus, add the ability to use a lock with timeout so that other cpus don't wait forever. Turn lock and release into apis BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/cpu/x86/mp_init.c | 21 +++++++++++++++++++-- src/include/cpu/x86/mp.h | 6 ++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c989963..f137ede 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -138,7 +138,7 @@ struct cpu_map { /* Keep track of APIC and device structure for each CPU. */ static struct cpu_map cpus[CONFIG_MAX_CPUS]; -static inline void barrier_wait(atomic_t *b) +inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) { asm ("pause"); @@ -146,7 +146,24 @@ static inline void barrier_wait(atomic_t *b) mfence(); } -static inline void release_barrier(atomic_t *b) +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms) +{ + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_msecs(&end, timeout_ms); + + while (atomic_read(b) == 0) { + timer_monotonic_get(&current); + if (mono_time_after(&current, &end)) + break; + asm ("pause"); + } + mfence(); +} + +inline void release_barrier(atomic_t *b) { mfence(); atomic_set(b, 1); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b9b4d57..113ed84 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -151,4 +151,10 @@ void smm_initiate_relocation_parallel(void); /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +inline void barrier_wait(atomic_t *b); + +inline void release_barrier(atomic_t *b); + +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms); + #endif /* _X86_MP_H_ */

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coreboot-gerrit January 2017