coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

1 participants
852 discussions

New patch to review for coreboot: [WIP] nb/i945/gma.c: Set pwm backlight frequency instead of using magic numbers
by Arthur Heymans 14 Jan '17

14 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit 082722b0fca450c92d03faa369285238b4a027fb Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 [WIP] nb/i945/gma.c: Set pwm backlight frequency instead of using magic numbers The core display clock on 945gm is fixed on 400MHz according to linux src. This assumes that the BLC_PWM_CTL reg has similar semantics as later Intel chipsets namely: pwm_freq = cdclock / (128 * (BLC_PWM_CTL[31:17] << 1)). It reduces default pwm freq on 945gm board since it was unreasonably high (> 10000Hz). This value should be fine for LED backlit display (1000Hz) but since all those boards have CCFL by default a lower value might be desired (~100Hz). Most board currently have smm code that rely on legacy mode operation of blacklight duty cycle. It reuses some gm45 code to set up panel. UNTESTED Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 +- src/mainboard/lenovo/t60/devicetree.cb | 2 +- src/mainboard/lenovo/x60/devicetree.cb | 2 +- src/northbridge/intel/i945/chip.h | 7 ++- src/northbridge/intel/i945/gma.c | 88 +++++++++++++++++++++++++---- 5 files changed, 86 insertions(+), 15 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..d8a5b40 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "1000" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..6ef95d5 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "1000" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..1e99379 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "1000" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..5bbda81 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,13 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..ef57b20 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -46,6 +46,20 @@ #define PGETBL_ENABLED 0x00000001 #define BASE_FREQUENCY 100000 +#define CORE_DISPLAY_CLOCK 400000 +#define DEFAULT_PWM 1000 + +static struct resource *gtt_res = NULL; + +u32 gtt_read(u32 reg) +{ + return read32(res2mmio(gtt_res, reg, 0)); +} + +void gtt_write(u32 reg, u32 data) +{ + write32(res2mmio(gtt_res, reg, 0), data); +} static int gtt_setup(void *mmiobase) { @@ -292,17 +306,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(pmmio + DSPPOS(0), 0); - /* Backlight init. */ - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC, 0x011d011a); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC_SELF, 0x0001003f); - write32(pmmio + FW_BLC, 0x011d0109); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(pmmio + DSPADDR(0), 0); write32(pmmio + DSPSURF(0), 0); @@ -579,6 +582,64 @@ static int probe_edid(u8 *pmmio, u8 slave) return 1; } +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + blc_mod = CORE_DISPLAY_CLOCK / (128 * pwm_freq); + + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(PP_ON_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(PP_ON_DELAYS, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(PP_OFF_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(PP_OFF_DELAYS, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = (CORE_DISPLAY_CLOCK / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + gtt_write(PP_DIVISOR, reg32); + } + + /* Backlight init. */ + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC, 0x011d011a); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC_SELF, 0x0001003f); + gtt_write(FW_BLC, 0x011d0109); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + if (conf->pwm_freq == 0) { + reg32 = BLM_LEGACY_MODE | 0x01280128; + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, DEFAULT_PWM)); + } else { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); + } +} static void gma_func0_init(struct device *dev) { @@ -596,6 +657,8 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); @@ -623,6 +686,9 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + + panel_setup(dev); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

1 0

Patch set updated for coreboot: libpayload: Enable USB HID in veyron configuration
by Paul Kocialkowski 14 Jan '17

14 Jan '17

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17930 -gerrit commit fe7689192927ef590b5981999bbf4b834d06b781 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Dec 19 20:23:44 2016 +0100 libpayload: Enable USB HID in veyron configuration This enables USB HID support in the veyron config, since it seems to work correctly and is needed for interaction with depthcharge on devices without an embedded keyboard (such as veyron_mickey). Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- payloads/libpayload/configs/config.veyron | 1 - 1 file changed, 1 deletion(-) diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron index e80535c..b643e92 100644 --- a/payloads/libpayload/configs/config.veyron +++ b/payloads/libpayload/configs/config.veyron @@ -4,4 +4,3 @@ CONFIG_LP_8250_SERIAL_CONSOLE=y CONFIG_LP_TIMER_RK3288=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_DWC2=y -# CONFIG_LP_USB_HID is not set

1 0

New patch to review for coreboot: mainboard/google/snappy: disable unused devices
by Wisley Chen 14 Jan '17

14 Jan '17

Wisley Chen (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18140 -gerrit commit c6d7c37c5ba69da8795f14c8a31a8a8aa0701a86 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Sat Jan 14 23:19:16 2017 +0800 mainboard/google/snappy: disable unused devices The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- src/mainboard/google/reef/variants/snappy/devicetree.cb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index e46483e..d420481 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -200,15 +200,15 @@ chip soc/intel/apollolake device i2c 0x9 on end end end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 + device pci 18.3 off end # - UART 3 device pci 19.0 on end # - SPI 0 - device pci 19.1 on end # - SPI 1 - device pci 19.2 on end # - SPI 2 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 device pci 1a.0 on end # - PWM device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC

1 0

New patch to review for coreboot: riscv: fix up issues related to M-mode misalign traps
by Ronald G. Minnich 13 Jan '17

13 Jan '17

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18139 -gerrit commit ee7d3b858c50b4c930250c1442759003947c1267 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Jan 13 18:27:34 2017 -0800 riscv: fix up issues related to M-mode misalign traps First, make sure that the lb_record allocator allocates 128-bit-aligned pointers. This ensures safety up to rv128. Second, if we take an interrupt in M-mode, panic. We have no plans to support that. If you have alignment issues in M-mode it's a sign you need to fix your firmware. This gets me back up to a shell prompt on harvey, where before we would fail with an alignment trap in coreboot. Change-Id: Id683fe2baa8cbea9abfccab72cf66a44fc04429e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/trap_handler.c | 6 ++++++ src/lib/coreboot_table.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 9a8947c..272622c 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -150,6 +150,12 @@ static void interrupt_handler(trapframe *tf) { uint64_t cause = tf->cause & ~0x8000000000000000ULL; uint32_t msip, ssie; + bool mprv = !!(tf->status & MSTATUS_MPRV); + + if (mprv) { + print_trap_information(tf); + die("Interrupt in M-mode. Fix your firmware"); + } switch (cause) { case IRQ_M_TIMER: diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f8da658..dadedc8 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -88,6 +88,14 @@ struct lb_record *lb_new_record(struct lb_header *header) rec = lb_last_record(header); if (header->table_entries) { header->table_bytes += rec->size; + // If the rec->size is not aligned to something reasonable, + // some architectures can take alignment traps. + // Round up table_bytes to something that is future-proof, + // namely 128 bits (16 bytes). This will ensure that even + // the 128-bit RISCV won't get traps. + // We have roundup macros all over the tree; we need to + // clean that up at some point. + header->table_bytes = (header->table_bytes + 15) & ~0xf; } rec = lb_last_record(header); header->table_entries++;

1 0

Patch set updated for coreboot: riscv: get SBI calls to work
by Ronald G. Minnich 13 Jan '17

13 Jan '17

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18097 -gerrit commit a94517f6db705ff73ce1c4c856bf3fab4dcf73cb Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 10 18:06:48 2017 -0800 riscv: get SBI calls to work SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/bootblock.S | 14 ++++++----- src/arch/riscv/include/mcall.h | 55 ++++++++++++++++++++++++++++++------------ src/arch/riscv/mcall.c | 25 +++++++++++++++++-- src/arch/riscv/trap_handler.c | 12 ++++----- src/arch/riscv/trap_util.S | 12 ++++++--- 5 files changed, 83 insertions(+), 35 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index c54c0e2..43bca90 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -16,6 +16,7 @@ */ #include <arch/encoding.h> +#include <mcall.h> .section ".text._start", "ax", %progbits @@ -30,8 +31,14 @@ _start: # and the stack must be page-aligned. la sp, _estack + # poison the stack + la t1, _stack + li t0, 0xdeadbeef + sd t0, 0(t1) + # make room for HLS and initialize it - addi sp, sp, -64 // MENTRY_FRAME_SIZE + addi sp, sp, -HLS_SIZE + // Once again, the docs and toolchain disagree. // Rather than get fancy I'll just lock this down // until it all stabilizes. @@ -39,11 +46,6 @@ _start: csrr a0, 0xf14 call hls_init - # poison the stack - la t1, _stack - li t0, 0xdeadbeef - sd t0, 0(t1) - la t0, trap_entry csrw mtvec, t0 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index a43b9cf..d74bdf1 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -16,35 +16,56 @@ #ifndef _MCALL_H #define _MCALL_H +// NOTE: this is the size of hls_t below. A static_assert would be +// nice to have. +#define HLS_SIZE 64 + +/* We save 37 registers, currently. */ +#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) + +#define MCALL_HART_ID 0 +#define MCALL_CONSOLE_PUTCHAR 1 +#define MCALL_CONSOLE_GETCHAR 2 +#define MCALL_HTIF_SYSCALL 3 +#define MCALL_SEND_IPI 4 +#define MCALL_CLEAR_IPI 5 +#define MCALL_SHUTDOWN 6 +#define MCALL_SET_TIMER 7 +#define MCALL_REMOTE_SFENCE_VM 8 +#define MCALL_REMOTE_FENCE_I 9 +#define MCALL_CONFIG_STRING_BASE 10 +#define MCALL_CONFIG_STRING_SIZE 11 + +#ifndef __ASSEMBLER__ + #include <arch/encoding.h> #include <atomic.h> #include <stdint.h> -#define HLS_SIZE 64 -#define MENTRY_FRAME_SIZE HLS_SIZE - typedef struct { - unsigned long base; - unsigned long size; - unsigned long node_id; + unsigned long base; + unsigned long size; + unsigned long node_id; } memory_block_info; typedef struct { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; + unsigned long dev; + unsigned long cmd; + unsigned long data; + unsigned long sbi_private_data; } sbi_device_message; typedef struct { - sbi_device_message* device_request_queue_head; - unsigned long device_request_queue_size; - sbi_device_message* device_response_queue_head; - sbi_device_message* device_response_queue_tail; + sbi_device_message *device_request_queue_head; + unsigned long device_request_queue_size; + sbi_device_message *device_response_queue_head; + sbi_device_message *device_response_queue_tail; - int hart_id; - int ipi_pending; + int hart_id; + int ipi_pending; + uint64_t *timecmp; + uint64_t *time; } hls_t; #define MACHINE_STACK_TOP() ({ \ @@ -67,4 +88,6 @@ uintptr_t mcall_send_ipi(uintptr_t recipient); uintptr_t mcall_shutdown(void); void hls_init(uint32_t hart_id); // need to call this before launching linux +#endif // __ASSEMBLER__ + #endif diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index aa61ae4..37a9366 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -34,6 +34,8 @@ #include <string.h> #include <vm.h> +int mcalldebug; // set this interactively for copious debug. + uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) { if (id == 0) { @@ -74,9 +76,17 @@ uintptr_t mcall_shutdown(void) return 0; } -uintptr_t mcall_set_timer(unsigned long long when) +uintptr_t mcall_set_timer(uint64_t when) { - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + uint64_t *timecmp = HLS()->timecmp; + + if (mcalldebug) + printk(BIOS_SPEW, + "hart %d: HLS %p: mcall timecmp@%p to 0x%llx\n", + HLS()->hart_id, HLS(), timecmp, when); + *timecmp = when; + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); return 0; } @@ -94,8 +104,19 @@ uintptr_t mcall_dev_resp(void) void hls_init(uint32_t hart_id) { + query_result res; + + printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS()); memset(HLS(), 0, sizeof(*HLS())); HLS()->hart_id = hart_id; + + res = query_config_string(configstring(), "rtc{addr"); + HLS()->time = (void *)get_uint(res); + res = query_config_string(configstring(), "core{0{0{timecmp"); + HLS()->timecmp = (void *)get_uint(res); + + printk(BIOS_SPEW, "Time is %p and timecmp is %p\n", + HLS()->time, HLS()->timecmp); } uintptr_t mcall_console_putchar(uint8_t ch) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 5681209..9a8947c 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -64,9 +64,6 @@ void handle_supervisor_call(trapframe *tf) { returnValue = mcall_shutdown(); break; case SBI_ECALL_SET_TIMER: - printk(BIOS_DEBUG, - "Setting timer to %p (current time is %p)...\n", - (void *)arg0, (void *)rdtime()); returnValue = mcall_set_timer(arg0); break; case SBI_ECALL_QUERY_MEMORY: @@ -152,7 +149,7 @@ static void gettimer(void) static void interrupt_handler(trapframe *tf) { uint64_t cause = tf->cause & ~0x8000000000000000ULL; - uint32_t ssip, ssie; + uint32_t msip, ssie; switch (cause) { case IRQ_M_TIMER: @@ -183,10 +180,11 @@ static void interrupt_handler(trapframe *tf) if (!timecmp) gettimer(); + //printk(BIOS_SPEW, "timer interrupt\n"); *timecmp = (uint64_t) -1; - ssip = read_csr(sip); - ssip |= SIP_STIP; - write_csr(sip, ssip); + msip = read_csr(mip); + msip |= SIP_STIP; + write_csr(mip, msip); break; default: printk(BIOS_EMERG, "======================================\n"); diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 3357959..ae32379 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -15,6 +15,8 @@ */ #include <bits.h> +#include <mcall.h> + .macro restore_regs # restore x registers LOAD x1,1*REGBYTES(a0) @@ -100,16 +102,17 @@ # get faulting insn, if it wasn't a fetch-related trap li x5,-1 STORE x5,36*REGBYTES(x2) -1: + .endm +.globl estack .text .global supervisor_trap_entry supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - li sp, 0x80FFF0 - 64 - 1:addi sp,sp,-320 + la sp, _estack + addi sp,sp,-MENTRY_FRAME_SIZE save_tf move a0,sp jal trap_handler @@ -127,7 +130,8 @@ trap_entry: # TODO: Use the old stack pointer (plus an offset) for exceptions in machine # mode, to avoid overwriting stack data. - li sp, 0x8000fff0 + la sp, _estack + addi sp,sp,-MENTRY_FRAME_SIZE save_tf move a0,sp

1 0

New patch to review for coreboot: mainboard/google/poppy: SD card changes
by Furquan Shaikh 13 Jan '17

13 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18138 -gerrit commit 73531fa8a9fc376eb8512a89c910f7113824ec35 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Jan 13 17:27:36 2017 -0800 mainboard/google/poppy: SD card changes 1. Disable WP 2. Pass SD card detect info in ACPI BUG=chrome-os-partner:60713 BRANCH=None TEST=Verified that OS is able to detect SD card and read/write to it. Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/devicetree.cb | 3 +++ src/mainboard/google/poppy/gpio.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 8699bc1..a9e0cef 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -185,6 +185,9 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_pl2_override" = "7" + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_G7" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index 914b8ed..0a2544c 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -210,7 +210,7 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),

1 0

Patch merged into coreboot/master: amd/mct: Add default values to highest_rank_count for DDR2
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit a19d44d2764be4dba55cad96abea12d92c8e1f0d Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 17:47:37 2017 -0600 amd/mct: Add default values to highest_rank_count for DDR2 The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/18078 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18078 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit 9d490daf8d8327f8f01123cf152edf75474f54ce Author: Kane Chen <kane.chen(a)intel.com> Date: Wed Jan 11 12:53:58 2017 +0800 soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree This code allows people to override the usb2 eye pattern UPD settings for boards. BUG=chrome-os-partner:61031 BRANCH=None TEST=Usb2 function ok and make sure fsp upd is overridden Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e Signed-off-by: Kane Chen <kane.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/18060 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18060 for details. -gerrit

1 0

Patch merged into coreboot/master: apollolake: Update UPD header files for FSP 1.3.0
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit e7056a82e098f3d1eb368ef4be021264cb54f20a Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Thu Jan 5 12:47:27 2017 -0800 apollolake: Update UPD header files for FSP 1.3.0 These updated header files contain USB tuning parameters as well as some general cleanup of unused parameters in the UPD Headers. This patch along with the upcoming FSP 1.3.0 release will allow for USB tuning on apollolake platforms. CQ-DEPEND=CL:*315403 BUG=chrome-os-partner:61031 Change-Id: Id7cce1ea83057630d508523ada18c5425804535e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Reviewed-on: https://review.coreboot.org/18046 Reviewed-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18046 for details. -gerrit

1 0

Patch set updated for coreboot: mainboard/google/reef: Ignore SPI IOSTANDBY
by Lijian Zhao 13 Jan '17

13 Jan '17

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18137 -gerrit commit add89359c60f5dcb55fab4c3750ee9205f4725cc Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Fri Jan 13 14:01:42 2017 -0800 mainboard/google/reef: Ignore SPI IOSTANDBY SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- .../google/reef/variants/baseboard/gpio.c | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index d5e5917..0c5975a 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -238,20 +238,21 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ /* Fast SPI */ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ - PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ - PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ - PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE), /* FST_SPI_CS2_N */ /* SIO_SPI_0 - Used for FP */ - PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ - PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ - PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ - PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ - PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ /* SIO_SPI_1 -- largely unused */ PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */

1 0

← Newer
1
...
43
44
45
46
47
48
49
...
86
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2017