coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/google/reef: Ignore SPI IOSTANDBY
by Lijian Zhao 13 Jan '17

13 Jan '17

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18137 -gerrit commit 14e31808d385fde90f6e62d07436e947100ccc4d Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Fri Jan 13 14:01:42 2017 -0800 mainboard/google/reef: Ignore SPI IOSTANDBY SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- .../google/reef/variants/baseboard/gpio.c | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index d5e5917..01fca14 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -238,20 +238,21 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ /* Fast SPI */ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ - PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ - PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ - PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */ /* SIO_SPI_0 - Used for FP */ - PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ - PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ - PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ - PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ - PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ + PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE), /* FST_SPI_CS2_N */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ /* SIO_SPI_1 -- largely unused */ PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */

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New patch to review for coreboot: mainboard/google/reef: Ignore SPI IOSTANDBY
by Lijian Zhao 13 Jan '17

13 Jan '17

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18137 -gerrit commit 0de419ab45fa0267e65c24a963b8620ad974f16a Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Fri Jan 13 14:01:42 2017 -0800 mainboard/google/reef: Ignore SPI IOSTANDBY SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97,GPIO_99, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- .../google/reef/variants/baseboard/gpio.c | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index d5e5917..bcc6332 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -238,20 +238,21 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ /* Fast SPI */ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ - PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ - PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ - PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */ /* SIO_SPI_0 - Used for FP */ - PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ - PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ - PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ - PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ - PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ + PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE), /* FST_SPI_CS2_N */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ /* SIO_SPI_1 -- largely unused */ PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */

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New patch to review for coreboot: intel: Fix copy/paste error in license text
by Marshall Dawson 13 Jan '17

13 Jan '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18136 -gerrit commit 71b44cbd1e2e885f877ae672a0ecc604996a1868 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Jan 13 14:23:49 2017 -0700 intel: Fix copy/paste error in license text Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/intel/galileo/reg_access.c | 2 +- src/soc/intel/braswell/bootblock/bootblock.c | 2 +- src/soc/intel/braswell/include/soc/iosf.h | 2 +- src/soc/intel/braswell/include/soc/msr.h | 2 +- src/soc/intel/braswell/include/soc/pcie.h | 2 +- src/soc/intel/braswell/iosf.c | 2 +- src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c | 2 +- src/soc/intel/fsp_broadwell_de/include/soc/msr.h | 2 +- src/soc/intel/quark/reg_access.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 3a8001b..c595dff 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 45bda05..79d44e0 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index c0b3f06..464f1cd 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index d998e68..47e9bcd 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h index 39776bb..1515fc2 100644 --- a/src/soc/intel/braswell/include/soc/pcie.h +++ b/src/soc/intel/braswell/include/soc/pcie.h @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 9a26757..990c2b5 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c b/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c index c026c83..73c3f28 100644 --- a/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c +++ b/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index c409ec8..da9ebb9 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 2ddb99b..d58fd1f 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */

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New patch to review for coreboot: util/scripts: extend cross-repo-cherrypick
by Patrick Georgi 13 Jan '17

13 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18135 -gerrit commit be1375d19be0c8652dce4a00d39b03d899b86d39 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jan 13 19:11:29 2017 +0100 util/scripts: extend cross-repo-cherrypick The script now automatically discovers the original branch (if known) and configures itself appropriately. Additionally, commit messages for changes coming _from_ upstream will be prefixed with "UPSTREAM: ". With the optional --cros argument, it also adds a BUG/BRANCH/TEST block at the right place in the commit message (right above the metadata) if one doesn't already exist. Change-Id: I81864ddca62fd99a9eb905d7075e5b53f58c4eb5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/scripts/cross-repo-cherrypick | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/util/scripts/cross-repo-cherrypick b/util/scripts/cross-repo-cherrypick index 9247cc2..0f2acf8 100755 --- a/util/scripts/cross-repo-cherrypick +++ b/util/scripts/cross-repo-cherrypick @@ -2,7 +2,7 @@ # rebase.sh - rebase helper script # -# Copyright 2015 Google Inc. +# Copyright 2015, 2017 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,7 +15,7 @@ # # Adapt to your remote branch: -BRANCH="cros/chromeos-2016.05" +BRANCH="origin/master" # When pulling in patches from another tree from a gerrit repository, # do the following at the end of a larger cherry-pick series: @@ -26,10 +26,32 @@ BRANCH="cros/chromeos-2016.05" # Alternatively, you can run util/gitconfig/rebase.sh after every # individual cherry-pick. +# use $0 --cros to add a stub BUG/BRANCH/TEST block + commit_message() { git log -n 1 | grep "^ " | cut -c5- } +ORIGIN_HOST=$( commit_message |grep "^Reviewed-on: " |head -1 |cut -d/ -f3 ) +case "${ORIGIN_HOST}" in + review.coreboot.org) + BRANCH="origin/master" + MESSAGE_PREFIX="UPSTREAM: " + ;; + chromium-review.googlesource.com) + BRANCH="cros/chromeos-2016.05" + MESSAGE_PREFIX="" + ;; +esac + +# lines must be backwards due to tac(1) +SPLICE_CMD="" +if test "$1" = "--cros"; then + if test -z "$( commit_message |egrep '^(BUG|TEST)=')"; then + SPLICE_CMD='print "\nTEST=none\nBRANCH=none\nBUG=none\n"' + fi +fi + CHID=$( commit_message | grep -i "^Change-Id: I" ) CID=$( git log -n1 --grep "^$CHID$" --pretty=%H $BRANCH ) GUID="$(git config user.name) <$(git config user.email)>" @@ -37,9 +59,11 @@ GUID="$(git config user.name) <$(git config user.email)>" # TBD: Don't add Original- to empty lines, and possibly make script more # solid for commits with an unexpected order of meta data lines. -commit_message | tac | awk '/^$/ { - if (end==0) - print "Original-Commit-Id: '"$CID"'\nSigned-off-by: '"$GUID"'"; +(printf "${MESSAGE_PREFIX}"; commit_message) | tac | awk '/^$/ { + if (end==0) { + print "Original-Commit-Id: '"${CID}"'\nSigned-off-by: '"${GUID}"'"; + '"${SPLICE_CMD}"' + } end=1 }; { if (end==0)

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Patch merged into coreboot/master: aopen/dxplplusu: Switch to 2MiB flash
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit 9bafa2947bd76b44e9c360c7bb2c75ab2d0cd1e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 15:39:56 2016 +0200 aopen/dxplplusu: Switch to 2MiB flash Change-Id: Iedc15823dc24b3211fe7954cdf4302934a517afb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17919 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/poppy: Disable EC SW sync
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit 8525b8c3bd1e01e4aeb0eb88447640b68ebceeed Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Jan 12 02:58:23 2017 -0800 mainboard/google/poppy: Disable EC SW sync BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that EC SW sync is disabled Change-Id: I399b26aa64084f5d5e91a2e585281dc48fa81c89 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18114 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/poppy: Enable touchscreen in ACPI
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit 13dae93501877e92f3cd81e450829c0c2e37b18a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Jan 12 02:06:47 2017 -0800 mainboard/google/poppy: Enable touchscreen in ACPI BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that touchscreen works on poppy. Change-Id: I0fd605048b91b126ca5b5f8c1c4d6d3f46f866a3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18113 Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18113 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/poppy: Correct the index for SPD binaries
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit e539ffbb70909d58e4bd7c095389d113bb947539 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 11 22:16:40 2017 -0800 mainboard/google/poppy: Correct the index for SPD binaries BUG=chrome-os-partner:60513 BRANCH=None TEST=Picks up correct SPD for index. Change-Id: Iac683ab3b8151747940b0ad7e257da3d9b0ac622 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18112 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18112 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/poppy: Enable SD card
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit b3b5dd93e97ea5b66b6280866494adcb36471a64 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 11 20:32:55 2017 -0800 mainboard/google/poppy: Enable SD card BUG=chrome-os-partner:60713 BRANCH=None TEST=sdcard is detected. Change-Id: I9ec0cabff0ed7973f5e7dd2c1eae346ae6a1aa99 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18111 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18111 for details. -gerrit

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Patch merged into coreboot/master: fsp_baytrail: Enable graphic init per default
by gerrit＠coreboot.org 13 Jan '17

13 Jan '17

the following patch was just integrated into master: commit deed5fbebdb879beccbe2421f1dd3af33301c51a Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 12 06:29:04 2017 +0100 fsp_baytrail: Enable graphic init per default Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni(a)kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18109 for details. -gerrit

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coreboot-gerrit January 2017