coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

1 participants
852 discussions

Patch set updated for coreboot: google/pyro: Add ELAN touch screen support
by Kevin Chiu 10 Jan '17

10 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18086 -gerrit commit 3fb2a8d61f7e5c368cf23e2273ea77329f0400ef Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Tue Jan 10 22:31:05 2017 +0800 google/pyro: Add ELAN touch screen support Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index b5e050e..66305ef 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -174,6 +174,23 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "pwr_mgmt_type" = "GPIO_EXPORT" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + + chip drivers/generic/gpio_regulator + register "name" = ""vcc33"" + register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enabled_on_boot" = "1" + device generic 0 on end + end + + device i2c 10 on end + end end # - I2C 3 device pci 17.0 on chip drivers/i2c/generic

1 0

New patch to review for coreboot: google/pyro: ELAN touch screen support
by Kevin Chiu 10 Jan '17

10 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18086 -gerrit commit 93f2c59a5508f41ba6a62114b92f22ff8abf2080 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Tue Jan 10 22:31:05 2017 +0800 google/pyro: ELAN touch screen support To add ELAN touch screen support for Pyro BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index b5e050e..66305ef 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -174,6 +174,23 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "pwr_mgmt_type" = "GPIO_EXPORT" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + + chip drivers/generic/gpio_regulator + register "name" = ""vcc33"" + register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enabled_on_boot" = "1" + device generic 0 on end + end + + device i2c 10 on end + end end # - I2C 3 device pci 17.0 on chip drivers/i2c/generic

1 0

Patch merged into coreboot/master: buildgcc: try curl if wget is not present
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit df1ff231e4d378f25ba0d986191287a3af690a68 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 7 09:28:43 2017 +0100 buildgcc: try curl if wget is not present There are systems that come with curl but not wget (eg macOS) and they now have to install one less additional dependency. Also fix some cosmetic issues in console output and require valid certificates on https downloads. Change-Id: Idc2ce892fbb6629aebfe1ae2a95dcef4d5d93aca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18048 for details. -gerrit

1 0

Patch set updated for coreboot: buildgcc: try curl if wget is not present
by Patrick Georgi 10 Jan '17

10 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18048 -gerrit commit 53faf27d74d52d49b7b4f39839ed271eca69fd3a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 7 09:28:43 2017 +0100 buildgcc: try curl if wget is not present There are systems that come with curl but not wget (eg macOS) and they now have to install one less additional dependency. Also fix some cosmetic issues in console output and require valid certificates on https downloads. Change-Id: Idc2ce892fbb6629aebfe1ae2a95dcef4d5d93aca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/buildgcc | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0dfca26..1cefcd5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -130,9 +130,9 @@ please_install() *) solution="using your OS packaging system" ;; esac - printf "${RED}ERROR:${red} Missing tool: Please install \'$1\'. (eg $solution)${NC}\n" >&2 + printf "${RED}ERROR:${red} Missing tool: Please install '$1'. (eg $solution)${NC}\n" >&2 if [ -n "$2" ]; then - printf "${RED}ERROR:${red} or install \'$2\'.${NC}\n" >&2 + printf "${RED}ERROR:${red} or install '$2'.${NC}\n" >&2 fi } @@ -282,15 +282,6 @@ compute_sum() { printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" } -download_showing_percentage() { - url=$1 - printf " ..${red} 0%%" - wget --no-check-certificate $url 2>&1 | while read line; do - echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' - done - printf "${NC}" -} - download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" @@ -299,7 +290,7 @@ download() { printf " * $FILE " if test -f tarballs/$FILE && check_sum $FILE ; then - printf "(cached)" + echo "(cached)" else printf "(downloading from $archive)" rm -f tarballs/$FILE @@ -310,10 +301,9 @@ download() { fi if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE.${NC}\n" + printf "${RED}Failed to download $FILE.${NC}\n" exit 1 fi - printf "\n" } unpack_and_patch() { @@ -891,9 +881,25 @@ searchtool flex flex > /dev/null searchtool g++ "Free Software Foundation" nofail > /dev/null || \ searchtool clang "clang version" nofail > /dev/null || \ searchtool clang "LLVM" "" "g++" > /dev/null -searchtool wget > /dev/null searchtool bzip2 "bzip2," > /dev/null +if searchtool wget "GNU" nofail > /dev/null; then + download_showing_percentage() { + url=$1 + printf " ..${red} 0%%" + wget $url 2>&1 | while read line; do + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + done + echo "${NC}" + } +elif searchtool curl "^curl " > /dev/null; then + download_showing_percentage() { + url=$1 + echo + curl -#OL $url + } +fi + check_for_library "-lz" "zlib (zlib1g-dev or zlib-devel)" CC=cc

1 0

New patch to review for coreboot: devtree: Drop unused parameter show_devs_tree() call
by Kyösti Mälkki 10 Jan '17

10 Jan '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18085 -gerrit commit 481192e72a42431e0ea126630779f3d52c0cdc52 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 15 10:04:21 2016 +0300 devtree: Drop unused parameter show_devs_tree() call Change-Id: I14c044bb32713ef4133bce8a8238a2bc200c4959 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 2 +- src/device/device_util.c | 8 ++++---- src/include/device/device.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 9ea32cc..0231ec7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -989,7 +989,7 @@ void dev_enumerate(void) show_all_devs(BIOS_SPEW, "Before device enumeration."); printk(BIOS_SPEW, "Compare with tree...\n"); - show_devs_tree(root, BIOS_SPEW, 0, 0); + show_devs_tree(root, BIOS_SPEW, 0); if (root->chip_ops && root->chip_ops->enable_dev) root->chip_ops->enable_dev(root); diff --git a/src/device/device_util.c b/src/device/device_util.c index cd33aac..1a0a60f 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -813,7 +813,7 @@ void print_resource_tree(struct device *root, int debug_level, const char *msg) resource_tree(root, debug_level, 0); } -void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum) +void show_devs_tree(struct device *dev, int debug_level, int depth) { char depth_str[20]; int i; @@ -830,7 +830,7 @@ void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum) for (link = dev->link_list; link; link = link->next) { for (sibling = link->children; sibling; sibling = sibling->sibling) - show_devs_tree(sibling, debug_level, depth + 1, i); + show_devs_tree(sibling, debug_level, depth + 1); } } @@ -839,7 +839,7 @@ void show_all_devs_tree(int debug_level, const char *msg) /* Bail if not printing to screen. */ if (!do_printk(debug_level, "Show all devs in tree form... %s\n", msg)) return; - show_devs_tree(all_devices, debug_level, 0, -1); + show_devs_tree(all_devices, debug_level, 0); } void show_devs_subtree(struct device *root, int debug_level, const char *msg) @@ -849,7 +849,7 @@ void show_devs_subtree(struct device *root, int debug_level, const char *msg) dev_path(root), msg)) return; do_printk(debug_level, "%s\n", msg); - show_devs_tree(root, debug_level, 0, -1); + show_devs_tree(root, debug_level, 0); } void show_all_devs(int debug_level, const char *msg) diff --git a/src/include/device/device.h b/src/include/device/device.h index 39bf718..47509f7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -214,7 +214,7 @@ void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned co /* Debug functions */ void print_resource_tree(struct device * root, int debug_level, const char *msg); -void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); +void show_devs_tree(struct device *dev, int debug_level, int depth); void show_devs_subtree(struct device *root, int debug_level, const char *msg); void show_all_devs(int debug_level, const char *msg); void show_all_devs_tree(int debug_level, const char *msg);

1 0

Patch merged into coreboot/master: intel/i82801dx: Support 2MiB FWH part
by gerrit＠coreboot.org 10 Jan '17

10 Jan '17

the following patch was just integrated into master: commit 3d0288d6767fc4b0ddeb270392a22bf1894767cd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 15:39:44 2016 +0200 intel/i82801dx: Support 2MiB FWH part Default setting of southbridge assigned 1MiB of memory for FWH ID 0, while 2MiB is commercially available. Only remap IDs when large ROM is requested in case some board uses multiple FWH parts. Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17918 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/17918 for details. -gerrit

1 0

New patch to review for coreboot: skylake: Do not pass VBT to FSP if display init not required
by Duncan Laurie 09 Jan '17

09 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18084 -gerrit commit 9190f4d316edb467e6ee34ce56cb47d444124e89 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:23:39 2017 -0800 skylake: Do not pass VBT to FSP if display init not required The FSP 2.0 change broke the logic for determining whether or not to execute the GOP binary. Modify the FSP 2.0 code to do the right thing and check for display_init_required() before passing VBT into FSP and the GOP binary. BUG=chrome-os-partner:61726 TEST=disable developer mode and ensure FSP does not run GOP Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/chip_fsp20.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index a1e76a9..2aef65a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -14,6 +14,7 @@ */ #include <chip.h> +#include <bootmode.h> #include <bootstate.h> #include <device/pci.h> #include <fsp/api.h> @@ -108,9 +109,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); /* Load VBT */ - if (!is_s3_wakeup) + if (is_s3_wakeup) { + printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); + } else if (display_init_required()) { + /* Get VBT data */ vbt_data = fsp_load_vbt(); - + if (vbt_data) + printk(BIOS_DEBUG, "Passing VBT to GOP\n"); + else + printk(BIOS_DEBUG, "VBT not found!\n"); + } else { + printk(BIOS_DEBUG, "Not passing VBT to GOP\n"); + } params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {

1 0

New patch to review for coreboot: soc/intel/skylake: Rename car_stage.S for fsp2_0
by Boon Tiong Teo 09 Jan '17

09 Jan '17

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18083 -gerrit commit d2c6026298c4288ba8e8d7063be22fbdca701913 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Tue Jan 10 21:10:40 2017 +0800 soc/intel/skylake: Rename car_stage.S for fsp2_0 Cosmatic changes to rename car_stage.S to car_stage_fsp20.S. Tested on Kabylake Rvp11. Change-Id: I869df6eb746e3982e5912c272255eab6cb008838 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/soc/intel/skylake/romstage/Makefile.inc | 2 +- src/soc/intel/skylake/romstage/car_stage.S | 131 ----------------------- src/soc/intel/skylake/romstage/car_stage_fsp20.S | 131 +++++++++++++++++++++++ 3 files changed, 132 insertions(+), 132 deletions(-) diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 877712f..c19301f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,6 +1,6 @@ verstage-y += power_state.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S romstage-y += pmc.c romstage-y += power_state.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S deleted file mode 100644 index c6401fa..0000000 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <rules.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -.section ".text" -.global car_stage_entry - -car_stage_entry: - - /* Enter the C code */ - call car_stage_c_entry - -/* - * Car teardown - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - - #include <soc/car_teardown.S> - - /* Display the MTRRs */ - call soc_display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - call copy_and_run diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S new file mode 100644 index 0000000..c6401fa --- /dev/null +++ b/src/soc/intel/skylake/romstage/car_stage_fsp20.S @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <rules.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.section ".text" +.global car_stage_entry + +car_stage_entry: + + /* Enter the C code */ + call car_stage_c_entry + +/* + * Car teardown + */ + /* + * eax: New stack address + */ + + /* Switch to the stack in RAM */ + movl %eax, %esp + + #include <soc/car_teardown.S> + + /* Display the MTRRs */ + call soc_display_mtrrs + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Clear all of the variable MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx + clr %eax + clr %edx + +1: + testl %ebx, %ebx + jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ + wrmsr + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ + wrmsr + inc %ecx + + dec %ebx + jmp 2b +2: + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + call copy_and_run

1 0

New patch to review for coreboot: SPI: Fix command-response behavior
by Kyösti Mälkki 09 Jan '17

09 Jan '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18082 -gerrit commit 5665add99e44f61b1a6d5e3880e6bbcb672d2bfe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 10 06:25:57 2017 +0200 SPI: Fix command-response behavior Fix SPI flash ops regressions after commit: c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING When spi_flash_cmd() is called with argument response==NULL, only send out command without reading back the response. Change-Id: I28a94f208b4a1983d45d69d46db41391e267891d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/spi/spi_flash.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index a0e3105..95362f2 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -49,11 +49,14 @@ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, [1] = { .dout = NULL, .bytesout = 0, .din = din, .bytesin = bytes_in }, }; + size_t count = ARRAY_SIZE(vectors); + if (!bytes_in) + count = 1; if (spi_claim_bus(spi)) return ret; - if (spi_xfer_vector(spi, vectors, ARRAY_SIZE(vectors)) == 0) + if (spi_xfer_vector(spi, vectors, count) == 0) ret = 0; spi_release_bus(spi);

1 0

Patch set updated for coreboot: mainboard/intel/leafhill: initial leafhill board changes
by Brenton Dong 09 Jan '17

09 Jan '17

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18039 -gerrit commit 80f00adc8616805abbd0aa1014ba482688fb0c66 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Jan 4 16:39:43 2017 -0700 mainboard/intel/leafhill: initial leafhill board changes This commit makes the initial changes to support the Intel Leaf Hill CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set. The google/reef directory is used as a template, and the same IFWI stitching process as reef is used to generate a bootable image. Apollo Lake silicon requires a boot media region called IFWI which includes assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware. Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 100 +----- src/mainboard/intel/leafhill/Kconfig.name | 3 +- src/mainboard/intel/leafhill/Makefile.inc | 16 - src/mainboard/intel/leafhill/board_info.txt | 8 +- src/mainboard/intel/leafhill/boardid.c | 29 -- src/mainboard/intel/leafhill/bootblock.c | 10 - src/mainboard/intel/leafhill/brd_gpio.h | 62 ++++ src/mainboard/intel/leafhill/chromeos.c | 51 --- src/mainboard/intel/leafhill/chromeos.fmd | 53 --- src/mainboard/intel/leafhill/devicetree.cb | 235 +++++++++++++ src/mainboard/intel/leafhill/dsdt.asl | 26 -- src/mainboard/intel/leafhill/ec.c | 71 ---- src/mainboard/intel/leafhill/leafhill.fmd | 40 +++ src/mainboard/intel/leafhill/mainboard.c | 100 +----- src/mainboard/intel/leafhill/romstage.c | 106 +++++- src/mainboard/intel/leafhill/smihandler.c | 52 --- .../intel/leafhill/variants/baseboard/Makefile.inc | 10 - .../intel/leafhill/variants/baseboard/boardid.c | 22 -- .../leafhill/variants/baseboard/devicetree.cb | 235 ------------- .../intel/leafhill/variants/baseboard/gpio.c | 391 --------------------- .../baseboard/include/baseboard/acpi/dptf.asl | 89 ----- .../variants/baseboard/include/baseboard/ec.h | 76 ---- .../variants/baseboard/include/baseboard/gpio.h | 53 --- .../baseboard/include/baseboard/variants.h | 49 --- .../intel/leafhill/variants/baseboard/memory.c | 155 -------- .../intel/leafhill/variants/baseboard/nhlt.c | 44 --- .../intel/leafhill/variants/pyro/Makefile.inc | 1 - .../intel/leafhill/variants/pyro/devicetree.cb | 211 ----------- .../variants/pyro/include/variant/acpi/dptf.asl | 89 ----- .../leafhill/variants/pyro/include/variant/ec.h | 21 -- .../leafhill/variants/pyro/include/variant/gpio.h | 21 -- .../intel/leafhill/variants/pyro/memory.c | 114 ------ .../variants/reef/include/variant/acpi/dptf.asl | 16 - .../leafhill/variants/reef/include/variant/ec.h | 21 -- .../leafhill/variants/reef/include/variant/gpio.h | 21 -- .../intel/leafhill/variants/snappy/devicetree.cb | 223 ------------ .../variants/snappy/include/variant/acpi/dptf.asl | 89 ----- .../leafhill/variants/snappy/include/variant/ec.h | 21 -- .../variants/snappy/include/variant/gpio.h | 21 -- 39 files changed, 449 insertions(+), 2506 deletions(-) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index 30e1658..ded4d24 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -1,108 +1,24 @@ +if BOARD_INTEL_LEAFHILL -config BOARD_GOOGLE_BASEBOARD_REEF - def_bool n +config BOARD_SPECIFIC_OPTIONS + def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select I2C_TPM - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_TPM2 - select MAINBOARD_HAS_I2C_TPM_CR50 - select TPM2 - select GOOGLE_SMBIOS_MAINBOARD_VERSION - -if BOARD_INTEL_LEAFHILL - -config BASEBOARD_REEF_LAPTOP - def_bool n - select SYSTEM_TYPE_LAPTOP - -config DRIVER_TPM_I2C_BUS - hex - default 0x2 - -config DRIVER_TPM_I2C_ADDR - hex - default 0x50 - -config DRIVER_TPM_I2C_IRQ - int - default 60 # GPE0_DW1_28 - -config CHROMEOS - select EC_GOOGLE_CHROMEEC_SWITCHES - select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - select LID_SWITCH if BASEBOARD_REEF_LAPTOP - -config DRIVERS_I2C_DA7219 - default y - -config DRIVERS_I2C_GENERIC - default y - -config DRIVERS_I2C_WACOM - default y - -config DRIVERS_PS2_KEYBOARD - default y - -config DRIVERS_GENERIC_GPIO_REGULATOR - default y +# select HAVE_INTEL_FIRMWARE +# select HAVE_ME_BIN +# select LOCK_MANAGEMENT_ENGINE config MAINBOARD_DIR string default intel/leafhill -config VARIANT_DIR - string - default "reef" - default "pyro" if BOARD_GOOGLE_PYRO - default "snappy" if BOARD_GOOGLE_SNAPPY - config DEVICETREE string - default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO - default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY - default "variants/baseboard/devicetree.cb" + default "devicetree.cb" config MAINBOARD_PART_NUMBER string - default "Reef" - default "Pyro" if BOARD_GOOGLE_PYRO - default "Snappy" if BOARD_GOOGLE_SNAPPY - -config MAINBOARD_FAMILY - string - default "Google_Reef" - -config GBB_HWID - string - depends on CHROMEOS - default "REEF TEST 3240" if BOARD_GOOGLE_REEF - default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO - default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY - -config MAX_CPUS - int - default 8 - -config UART_FOR_CONSOLE - int - default 2 - -config INCLUDE_NHLT_BLOBS - bool "Include blobs for audio." - select NHLT_DMIC_1CH_16B - select NHLT_DMIC_2CH_16B - select NHLT_DMIC_4CH_16B - select NHLT_DA7219 - select NHLT_MAX98357 - -config DRIVERS_GENERIC_MAX98357A - default y + default "Leafhill" endif # BOARD_INTEL_LEAFHILL diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name index d6d66e7..391203c 100644 --- a/src/mainboard/intel/leafhill/Kconfig.name +++ b/src/mainboard/intel/leafhill/Kconfig.name @@ -1,4 +1,3 @@ config BOARD_INTEL_LEAFHILL bool "Leafhill" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP + diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc index ac654fb..9e3e892 100644 --- a/src/mainboard/intel/leafhill/Makefile.inc +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -1,19 +1,3 @@ bootblock-y += bootblock.c -bootblock-y += ec.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += boardid.c - -ramstage-y += boardid.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += ec.c ramstage-y += mainboard.c - -verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include - -subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt index 9b1f2a4..e0e5501 100644 --- a/src/mainboard/intel/leafhill/board_info.txt +++ b/src/mainboard/intel/leafhill/board_info.txt @@ -1,6 +1,6 @@ -Vendor name: Google -Board name: Reef Apollolake Reference Board -Category: laptop +Vendor name: Intel +Board name: Leafhill Reference Board +Category: eval ROM protocol: SPI -ROM socketed: n +ROM socketed: y Flashrom support: y diff --git a/src/mainboard/intel/leafhill/boardid.c b/src/mainboard/intel/leafhill/boardid.c deleted file mode 100644 index f240fca..0000000 --- a/src/mainboard/intel/leafhill/boardid.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <boardid.h> -#include <stddef.h> - -uint8_t board_id(void) -{ - MAYBE_STATIC int id = -1; - - if (id < 0) - id = variant_board_id(); - - return id; -} diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c index 57d20d9..3de44a8 100644 --- a/src/mainboard/intel/leafhill/bootblock.c +++ b/src/mainboard/intel/leafhill/bootblock.c @@ -13,20 +13,10 @@ * GNU General Public License for more details. */ -#include <baseboard/variants.h> #include <bootblock_common.h> -#include <ec/ec.h> #include <soc/lpc.h> -#include <soc/gpio.h> -#include <variant/ec.h> void bootblock_mainboard_init(void) { - const struct pad_config *pads; - size_t num; - lpc_configure_pads(); - pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); - mainboard_ec_init(); } diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h new file mode 100644 index 0000000..33b839b --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/leafhill/chromeos.c b/src/mainboard/intel/leafhill/chromeos.c deleted file mode 100644 index 256db16..0000000 --- a/src/mainboard/intel/leafhill/chromeos.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <boot/coreboot_tables.h> -#include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> -#include <variant/gpio.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/leafhill/chromeos.fmd b/src/mainboard/intel/leafhill/chromeos.fmd deleted file mode 100644 index 3c289a1..0000000 --- a/src/mainboard/intel/leafhill/chromeos.fmd +++ /dev/null @@ -1,53 +0,0 @@ -FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x17b000 - GBB@0x17c000 0x40000 - RO_UNUSED@0x1bc000 0x40000 - } - } - MISC_RW@0x400000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 - } - RW_SECTION_A@0x430000 0x480000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x46ffc0 - RW_FWID_A@0x47ffc0 0x40 - } - RW_SECTION_B@0x8b0000 0x480000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x46ffc0 - RW_FWID_B@0x47ffc0 0x40 - } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 -} diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb new file mode 100644 index 0000000..7db4f15 --- /dev/null +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -0,0 +1,235 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_122" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C0 for audio codec at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }" + + # Enable I2C2 bus early for TPM at 400kHz + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 57, + .fall_time_ns = 28, + }" + + # touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }" + + # trackpad at 400kHz + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 114, + .fall_time_ns = 164, + }" + + # digitizer at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "pwr_mgmt_type" = "GPIO_EXPORT" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + + chip drivers/generic/gpio_regulator + register "name" = ""vcc33"" + register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enabled_on_boot" = "1" + device generic 0 on end + end + + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on + chip drivers/i2c/wacom + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_DT_DESC, + .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index dc63436..004523a 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -13,9 +13,6 @@ * GNU General Public License for more details. */ -#include <variant/ec.h> -#include <variant/gpio.h> - DefinitionBlock( "dsdt.aml", "DSDT", @@ -40,29 +37,6 @@ DefinitionBlock( } } - /* Chrome OS specific */ - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> - - /* Chrome OS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include <ec/google/chromeec/acpi/superio.asl> - /* ACPI code for EC functions */ - #include <ec/google/chromeec/acpi/ec.asl> - } - - /* Dynamic Platform Thermal Framework */ - Scope (\_SB) - { - /* Per board variant specific definitions. */ - #include <variant/acpi/dptf.asl> - /* Include soc specific DPTF changes */ - #include <soc/intel/apollolake/acpi/dptf.asl> - /* Include common dptf ASL files */ - #include <soc/intel/common/acpi/dptf/dptf.asl> - } } diff --git a/src/mainboard/intel/leafhill/ec.c b/src/mainboard/intel/leafhill/ec.c deleted file mode 100644 index 646216b..0000000 --- a/src/mainboard/intel/leafhill/ec.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <ec/ec.h> -#include <ec/google/chromeec/ec.h> -#include <rules.h> -#include <soc/lpc.h> -#include <variant/ec.h> - -static void ramstage_ec_init(void) -{ - printk(BIOS_ERR, "mainboard: EC init\n"); - - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0) - ; - - /* Restore SCI event mask */ - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); - } - - /* Clear wake event mask */ - google_chromeec_set_wake_mask(0); -} - -static void bootblock_ec_init(void) -{ - uint16_t ec_ioport_base; - size_t ec_ioport_size; - - /* - * Set up LPC decoding for the ChromeEC I/O port ranges: - * - Ports 62/66, 60/64, and 200->208 - * - ChromeEC specific communication I/O ports. - */ - lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200); - google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); - lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); -} - -void mainboard_ec_init(void) -{ - if (ENV_RAMSTAGE) - ramstage_ec_init(); - else if (ENV_BOOTBLOCK) - bootblock_ec_init(); -} diff --git a/src/mainboard/intel/leafhill/leafhill.fmd b/src/mainboard/intel/leafhill/leafhill.fmd new file mode 100644 index 0000000..3da8467 --- /dev/null +++ b/src/mainboard/intel/leafhill/leafhill.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + WP_RO@0x0 0x400000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x1ff000 + RO_VPD@0x200000 0x4000 + RO_SECTION@0x204000 0x1fc000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x1bb000 + RO_UNUSED@0x1bc000 0x40000 + } + } + MISC_RW@0x400000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/intel/leafhill/mainboard.c b/src/mainboard/intel/leafhill/mainboard.c index 702269c..f7a2ef1 100644 --- a/src/mainboard/intel/leafhill/mainboard.c +++ b/src/mainboard/intel/leafhill/mainboard.c @@ -13,111 +13,13 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> -#include <baseboard/variants.h> -#include <boardid.h> -#include <console/console.h> #include <device/device.h> -#include <ec/ec.h> -#include <gpio.h> -#include <nhlt.h> -#include <smbios.h> -#include <soc/gpio.h> -#include <soc/nhlt.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <variant/ec.h> -#include <variant/gpio.h> static void mainboard_init(void *chip_info) { - int boardid; - const struct pad_config *pads; - size_t num; - - boardid = board_id(); - printk(BIOS_INFO, "Board ID: %d\n", boardid); - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); - - mainboard_ec_init(); -} - -/* - * There are 2 pins on reef-like boards that can be used for SKU'ing - * board differences. They each have optional stuffing for a pullup and - * a pulldown. This way we can generate 9 different values with the - * 2 pins. - */ -static int board_sku(void) -{ - static int board_sku_num = -1; - gpio_t board_sku_gpios[] = { - [1] = GPIO_17, [0] = GPIO_16, - }; - const size_t num = ARRAY_SIZE(board_sku_gpios); - - if (board_sku_num < 0) - board_sku_num = gpio_base3_value(board_sku_gpios, num); - - return board_sku_num; -} - -const char *smbios_mainboard_sku(void) -{ - static char sku_str[5]; /* sku[0-8] */ - - snprintf(sku_str, sizeof(sku_str), "sku%d", board_sku()); - - return sku_str; -} - -void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, - const char **oem_table_id, - uint32_t *oem_revision) -{ - *oem_id = "reef"; - *oem_table_id = CONFIG_VARIANT_DIR; - *oem_revision = board_sku(); -} - -static unsigned long mainboard_write_acpi_tables( - device_t device, unsigned long current, acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - const char *oem_id = NULL; - const char *oem_table_id = NULL; - uint32_t oem_revision = 0; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - variant_nhlt_init(nhlt); - variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision); - - end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id, oem_revision); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - -static void mainboard_enable(device_t dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + /* Nothing Here Yet */ } struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c index 0e9917f..5c784ba 100644 --- a/src/mainboard/intel/leafhill/romstage.c +++ b/src/mainboard/intel/leafhill/romstage.c @@ -13,17 +13,107 @@ * GNU General Public License for more details. */ -#include <baseboard/variants.h> -#include <soc/meminit.h> +#include <string.h> #include <soc/romstage.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; void mainboard_memory_init_params(FSPM_UPD *memupd) { - meminit_lpddr4_by_sku(&memupd->FspmConfig, - variant_lpddr4_config(), variant_memory_sku()); -} + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -void mainboard_save_dimm_info(void) -{ - save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku()); + /* DRAM Config settings */ + memupd->FspmConfig.Package = 0x1; + memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LASR = 0x0; + memupd->FspmConfig.ScramblerSupport = 0x1; + memupd->FspmConfig.ChannelHashMask = 0x36; + memupd->FspmConfig.SliceHashMask = 0x9; + memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ChannelsSlicesEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.RmtMode = 0x0; + memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.LowMemoryMaxValue = 0x0; + memupd->FspmConfig.DisableFastBoot = 0x0; + memupd->FspmConfig.HighMemoryMaxValue = 0x0; + memupd->FspmConfig.DIMM0SPDAddress = 0x0; + memupd->FspmConfig.DIMM1SPDAddress = 0x0; + memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; + memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_Option = 0x3; + memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_TristateClk1 = 0x0; + memupd->FspmConfig.Ch0_Mode2N = 0x0; + memupd->FspmConfig.Ch0_OdtLevels = 0x0; + memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; + memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_Option = 0x3; + memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_TristateClk1 = 0x0; + memupd->FspmConfig.Ch1_Mode2N = 0x0; + memupd->FspmConfig.Ch1_OdtLevels = 0x0; + memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; + memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_Option = 0x3; + memupd->FspmConfig.Ch2_OdtConfig = 0x0; + memupd->FspmConfig.Ch2_TristateClk1 = 0x0; + memupd->FspmConfig.Ch2_Mode2N = 0x0; + memupd->FspmConfig.Ch2_OdtLevels = 0x0; + memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; + memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_Option = 0x3; + memupd->FspmConfig.Ch3_OdtConfig = 0x0; + memupd->FspmConfig.Ch3_TristateClk1 = 0x0; + memupd->FspmConfig.Ch3_Mode2N = 0x0; + memupd->FspmConfig.Ch3_OdtLevels = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.MrcDataSaving = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x0; + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; } diff --git a/src/mainboard/intel/leafhill/smihandler.c b/src/mainboard/intel/leafhill/smihandler.c deleted file mode 100644 index fe4f8c4..0000000 --- a/src/mainboard/intel/leafhill/smihandler.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <baseboard/variants.h> -#include <cpu/x86/smm.h> -#include <ec/google/chromeec/smm.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <soc/gpio.h> -#include <variant/ec.h> -#include <variant/gpio.h> - -void mainboard_smi_gpi_handler(const struct gpi_status *sts) -{ - if (gpi_status_get(sts, EC_SMI_GPI)) - chromeec_smi_process_events(); -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_sleep_gpio_table(&num); - gpio_configure_pads(pads, num); - - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, - MAINBOARD_EC_S5_WAKE_EVENTS); -} - -int mainboard_smi_apmc(u8 apmc) -{ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, - MAINBOARD_EC_SMI_EVENTS); - return 0; -} diff --git a/src/mainboard/intel/leafhill/variants/baseboard/Makefile.inc b/src/mainboard/intel/leafhill/variants/baseboard/Makefile.inc deleted file mode 100644 index d2d344c..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -bootblock-y += gpio.c - -romstage-y += boardid.c -romstage-y += memory.c - -ramstage-y += boardid.c -ramstage-y += gpio.c -ramstage-y += nhlt.c - -smm-y += gpio.c diff --git a/src/mainboard/intel/leafhill/variants/baseboard/boardid.c b/src/mainboard/intel/leafhill/variants/baseboard/boardid.c deleted file mode 100644 index 26f1588..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/boardid.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <ec/google/chromeec/ec.h> - -uint8_t __attribute__((weak)) variant_board_id(void) -{ - return google_chromeec_get_board_version(); -} diff --git a/src/mainboard/intel/leafhill/variants/baseboard/devicetree.cb b/src/mainboard/intel/leafhill/variants/baseboard/devicetree.cb deleted file mode 100644 index 7db4f15..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/devicetree.cb +++ /dev/null @@ -1,235 +0,0 @@ -chip soc/intel/apollolake - - device cpu_cluster 0 on - device lapic 0 on end - end - - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt - # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, - }" - - # digitizer at 400kHz - register "i2c[5]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - - device domain 0 on - device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 - device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - - device i2c 10 on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOM50C1_HID, - .cid = PNP0C50_CID, - .desc = WCOM_DT_DESC, - .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), - }" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 5 - device pci 17.2 off end # - I2C 6 - device pci 17.3 off end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 - device pci 19.1 off end # - SPI 1 - device pci 19.2 off end # - SPI 2 - device pci 1a.0 on end # - PWM - device pci 1b.0 on end # - SDCARD - device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device pci 1f.1 on end # - SMBUS - end -end diff --git a/src/mainboard/intel/leafhill/variants/baseboard/gpio.c b/src/mainboard/intel/leafhill/variants/baseboard/gpio.c deleted file mode 100644 index d5e5917..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/gpio.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -/* - * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' - * table found in EDS vol 1, but some pins aren't grouped functionally in - * the table so those were moved for more logical grouping. - */ -static const struct pad_config gpio_table[] = { - /* PCIE_WAKE[0:3]_N */ - PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE), /* WLAN */ - PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */ - - /* EMMC interface */ - PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ - PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ - PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ - PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ - PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ - PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ - PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ - PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ - PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ - PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ - - /* SDIO -- unused. */ - PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ - PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ - /* Configure SDIO to enable power gating */ - PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ - PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ - PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ - PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ - - /* SDCARD */ - /* Pull down clock by 20K */ - PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ - PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ - PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ - PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ - PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ - /* Card detect is active LOW. Pull up by 20K */ - PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ - PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ - /* CLK feedback, internal signal, needs 20K pull down */ - PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ - /* No h/w write proect for uSD cards, pull down by 20K */ - PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ - /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ - PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ - - /* SMBus -- unused. */ - PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ - PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ - PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ - - /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ - PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ - PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ - PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ - PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ - PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ - PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ - PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ - - /* I2C0 - Audio */ - PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ - PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ - - /* I2C1 - NFC with external pulls */ - PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */ - PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */ - - /* I2C2 - TPM */ - PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ - PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ - - /* I2C3 - touch */ - PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */ - PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */ - - /* I2C4 - trackpad */ - PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */ - PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */ - - /* I2C5 -- pen with external pulls */ - PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */ - PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */ - - /* I2C6-7 -- unused. */ - PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ - PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ - PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ - PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ - - /* Audio Amp - I2S6 */ - PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */ - PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */ - PAD_CFG_GPI(GPIO_148, UP_20K, DEEP), /* ISH_GPIO_2 - unused */ - PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */ - - /* NFC Reset */ - PAD_CFG_GPO(GPIO_150, 1, DEEP), /* ISH_GPIO_4 */ - - PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* ISH_GPIO_5 - unused */ - - /* Touch enable */ - PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ - - PAD_CFG_GPI(GPIO_153, UP_20K, DEEP), /* ISH_GPIO_7 - unused */ - PAD_CFG_GPI(GPIO_154, UP_20K, DEEP), /* ISH_GPIO_8 - unused */ - PAD_CFG_GPI(GPIO_155, UP_20K, DEEP), /* ISH_GPIO_9 - unused */ - - /* PCIE_CLKREQ[0:3]_N */ - PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), /* WLAN with external pull */ - PAD_CFG_GPI(GPIO_210, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_211, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_212, UP_20K, DEEP), /* unused */ - - /* OSC_CLK_OUT_[0:4] -- unused */ - PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP), - - /* PMU Signals */ - PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */ - PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ - PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ - PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ - PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ - PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */ - PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ - PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ - PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ - PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ - PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ - PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ - - /* DDI[0:1] SDA and SCL -- unused */ - PAD_CFG_GPI(GPIO_187, UP_20K, DEEP), /* HV_DDI0_DDC_SDA */ - PAD_CFG_GPI(GPIO_188, UP_20K, DEEP), /* HV_DDI0_DDC_SCL */ - PAD_CFG_GPI(GPIO_189, UP_20K, DEEP), /* HV_DDI1_DDC_SDA */ - PAD_CFG_GPI(GPIO_190, UP_20K, DEEP), /* HV_DDI1_DDC_SCL */ - - /* MIPI I2C -- unused */ - PAD_CFG_GPI(GPIO_191, UP_20K, DEEP), /* MIPI_I2C_SDA */ - PAD_CFG_GPI(GPIO_192, UP_20K, DEEP), /* MIPI_I2C_SCL */ - - /* Panel 0 control */ - PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */ - PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */ - PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */ - - /* Panel 1 control -- unused */ - PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */ - PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */ - PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */ - - /* Hot plug detect. */ - PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ - PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ - - /* MDSI signals -- unused */ - PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */ - PAD_CFG_GPI(GPIO_202, UP_20K, DEEP), /* MDSI_A_TE */ - - /* USB overcurrent pins. */ - PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ - PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ - - /* PMC SPI -- almost entirely unused */ - PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), - PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */ - PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), - PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP), - PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP), - PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP), - - /* PMIC Signals Unused signals related to an old PMIC interface */ - PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */ - PAD_CFG_GPI(GPIO_213, NONE, DEEP), /* unused external pull */ - PAD_CFG_GPI(GPIO_214, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_215, UP_20K, DEEP), /* unused */ - PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */ - PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP), /* unused */ - PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ - PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ - PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ - - /* I2S1 -- largely unused */ - PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */ - PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ - PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */ - PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */ - PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */ - - /* DMIC or I2S4 */ - PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ - PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */ - PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ - PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ - PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */ - - /* I2S2 -- Headset amp */ - PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */ - PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* AVS_I2S2_BCLK */ - PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* AVS_I2S2_SW_SYNC */ - PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* AVS_I2S2_SDI */ - PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* AVS_I2S2_SDO */ - - /* I2S3 -- largely unused. */ - PAD_CFG_GPI(GPIO_89, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_90, UP_20K, DEEP), /* GPS_HOST_WAKE */ - PAD_CFG_GPO(GPIO_91, 1, DEEP), /* GPS_EN */ - PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ - - /* Fast SPI */ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ - PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ - PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ - PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ - - /* SIO_SPI_0 - Used for FP */ - PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ - PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ - PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ - PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ - PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ - - /* SIO_SPI_1 -- largely unused */ - PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */ - PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ - PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ - /* Headset interrupt */ - PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ - PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ - - /* SIO_SPI_2 -- unused */ - PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* SIO_SPI_2_CLK */ - PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ - PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ - PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ - /* WLAN_PE_RST - default to deasserted. */ - PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ - PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ - - /* Debug tracing. */ - PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ - PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), - - PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ - PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */ - PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ - PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ - PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ - PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ - PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */ - PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ - PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ - PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ - PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ - PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ - PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ - PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ - PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ - PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ - PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ - PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ - PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ - PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ - PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ - PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ - - /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ - /* Next 2 are straps. */ - PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ - PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ - PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ - PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ - PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ - PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ - PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ - PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ - PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ - - /* Camera interface -- completely unused. */ - PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */ - PAD_CFG_GPI(GPIO_63, UP_20K, DEEP), /* GP_CAMERASB01 */ - PAD_CFG_GPI(GPIO_64, UP_20K, DEEP), /* GP_CAMERASB02 */ - PAD_CFG_GPI(GPIO_65, UP_20K, DEEP), /* GP_CAMERASB03 */ - PAD_CFG_GPI(GPIO_66, UP_20K, DEEP), /* GP_CAMERASB04 */ - PAD_CFG_GPI(GPIO_67, UP_20K, DEEP), /* GP_CAMERASB05 */ - PAD_CFG_GPI(GPIO_68, UP_20K, DEEP), /* GP_CAMERASB06 */ - PAD_CFG_GPI(GPIO_69, UP_20K, DEEP), /* GP_CAMERASB07 */ - PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ - PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ - PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ - PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ -}; - -const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ - /* I2C2 - TPM */ - PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ - PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ - /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ - PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ -}; - -const struct pad_config * __attribute__((weak)) -variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -/* GPIO settings before entering sleep. */ -static const struct pad_config sleep_gpio_table[] = { - PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ -}; - -const struct pad_config * __attribute__((weak)) -variant_sleep_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(sleep_gpio_table); - return sleep_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), - CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME), -}; - -const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/acpi/dptf.asl deleted file mode 100644 index 87d3fa3..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/acpi/dptf.asl +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 103 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Battery" -#define DPTF_TSR0_PASSIVE 120 -#define DPTF_TSR0_CRITICAL 125 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 45 -#define DPTF_TSR1_CRITICAL 75 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 90 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 30, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 2 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 12000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index 87c127c..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BASEBOARD_EC_H -#define BASEBOARD_EC_H - -#include <variant/gpio.h> -#include <ec/google/chromeec/ec_commands.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif diff --git a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index 1db7422..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BASEBOARD_GPIO_H -#define BASEBOARD_GPIO_H - -#include <soc/gpio.h> - -/* - * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 - * which is North community - */ -#define EC_SCI_GPI GPE0_DW1_11 - -/* EC SMI */ -#define EC_SMI_GPI GPIO_49 - -/* - * On lidopen/lidclose GPIO_22 from North Community gets toggled and - * is used in _PRW to wake up device from sleep. GPIO_22 maps to - * group GPIO_GPE_N_31_0 and the pad is configured as SCI with - * EDGE_SINGLE and INVERT. - */ -#define GPE_EC_WAKE GPE0_DW1_22 - -/* Write Protect and indication if EC is in RW code. */ -#define GPIO_PCH_WP GPIO_75 -#define GPIO_EC_IN_RW GPIO_41 -/* Determine if board is in final shipping mode. */ -#define GPIO_SHIP_MODE GPIO_10 - -/* Memory SKU GPIOs. */ -#define MEM_CONFIG3 GPIO_45 -#define MEM_CONFIG2 GPIO_38 -#define MEM_CONFIG1 GPIO_102 -#define MEM_CONFIG0 GPIO_101 - -/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */ -#define DMIC_CONFIG_PIN GPIO_17 - -#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index 65a32b3..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BASEBOARD_VARIANTS_H -#define BASEBOARD_VARIANTS_H - -#include <soc/gpio.h> -#include <soc/meminit.h> -#include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Return the board id for the current variant board. */ -uint8_t variant_board_id(void); - -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); -const struct pad_config *variant_sleep_gpio_table(size_t *num); - -/* Baseboard default swizzle. Can be reused if swizzle is same. */ -extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; -/* Return LPDDR4 configuration structure. */ -const struct lpddr4_cfg *variant_lpddr4_config(void); -/* Return memory SKU for the board. */ -size_t variant_memory_sku(void); - -/* Return ChromeOS gpio table and fill in number of entries. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); - -/* Seed the NHLT tables with the board specific information. */ -struct nhlt; -void variant_nhlt_oem_overrides(const char **oem_id, - const char **oem_table_id, uint32_t *oem_revision); -void variant_nhlt_init(struct nhlt *nhlt); - -#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/intel/leafhill/variants/baseboard/memory.c b/src/mainboard/intel/leafhill/variants/baseboard/memory.c deleted file mode 100644 index 50e93c7..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/memory.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <gpio.h> -#include <soc/meminit.h> -#include <variant/gpio.h> - -const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { - /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ - .phys[LP4_PHYS_CH0A] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 }, - }, - .phys[LP4_PHYS_CH0B] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 }, - }, - .phys[LP4_PHYS_CH1A] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 }, - }, - .phys[LP4_PHYS_CH1B] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 }, - }, -}; - -/* - * The strings in the part_num field aren't necessarily the exact part - * numbers used in all the designs. The reason is that the mosys userland - * tool uses these strings for dumping more information. Different speed bins - * could change in future systems, but the strings still need to match. - */ -static const struct lpddr4_sku skus[] = { - /* - * K4F6E304HB-MG - both logical channels While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate - * the deneisty as 8Gb per rank. - */ - [0] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "K4F6E304HB-MGCJ", - }, - /* K4F8E304HB-MG - both logical channels */ - [1] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "K4F8E304HB-MGCJ", - }, - /* - * MT53B512M32D2NP - both logical channels. While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate - * the deneisty as 8Gb per rank. - */ - [2] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "MT53B512M32D2NP", - }, - /* MT53B256M32D1NP - both logical channels */ - [3] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "MT53B256M32D1NP", - }, - /* - * H9HCNNNBPUMLHR - both logical channels. While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate the - * density as 8Gb per rank. - */ - [4] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "H9HCNNNBPUMLHR", - }, - /* H9HCNNN8KUMLHR - both logical channels */ - [5] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "H9HCNNN8KUMLHR", - }, -}; - -static const struct lpddr4_cfg lp4cfg = { - .skus = skus, - .num_skus = ARRAY_SIZE(skus), - .swizzle_config = &baseboard_lpddr4_swizzle, -}; - -const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void) -{ - return &lp4cfg; -} - -size_t __attribute__((weak)) variant_memory_sku(void) -{ - gpio_t pads[] = { - [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, - [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, - }; - - /* Need internal pullups enabled as only pulldown stuffing options - * exist. */ - return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); -} diff --git a/src/mainboard/intel/leafhill/variants/baseboard/nhlt.c b/src/mainboard/intel/leafhill/variants/baseboard/nhlt.c deleted file mode 100644 index d44d599..0000000 --- a/src/mainboard/intel/leafhill/variants/baseboard/nhlt.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <console/console.h> -#include <nhlt.h> -#include <soc/nhlt.h> -#include <gpio.h> -#include <baseboard/gpio.h> - -void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) -{ - /* 1-dmic configuration */ - if (!nhlt_soc_add_dmic_array(nhlt, 1)) - printk(BIOS_ERR, "Added 1CH DMIC array.\n"); - /* 2-dmic configuration */ - if (!nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Added 2CH DMIC array.\n"); - /* 4-dmic configuration */ - if (!nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Added 4CH DMIC array.\n"); - /* Dialog for Headset codec. - * Headset codec is bi-directional but uses the same configuration - * settings for render and capture endpoints. - */ - if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); - - /* MAXIM Smart Amps for left and right speakers. */ - if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) - printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); -} diff --git a/src/mainboard/intel/leafhill/variants/pyro/Makefile.inc b/src/mainboard/intel/leafhill/variants/pyro/Makefile.inc deleted file mode 100644 index fd45b94..0000000 --- a/src/mainboard/intel/leafhill/variants/pyro/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -romstage-y += memory.c diff --git a/src/mainboard/intel/leafhill/variants/pyro/devicetree.cb b/src/mainboard/intel/leafhill/variants/pyro/devicetree.cb deleted file mode 100644 index bc06bbb..0000000 --- a/src/mainboard/intel/leafhill/variants/pyro/devicetree.cb +++ /dev/null @@ -1,211 +0,0 @@ -chip soc/intel/apollolake - - device cpu_cluster 0 on - device lapic 0 on end - end - - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt - # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 50, - .fall_time_ns = 23, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 90, - .fall_time_ns = 164, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - - device domain 0 on - device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 - device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOMNTN2_HID, - .cid = PNP0C50_CID, - .desc = WCOM_TS_DESC, - .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), - .probed = 1, - }" - register "hid_desc_reg_offset" = "0x1" - device i2c 0xA on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 off end # - I2C 5 - device pci 17.2 off end # - I2C 6 - device pci 17.3 off end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 - device pci 19.1 off end # - SPI 1 - device pci 19.2 off end # - SPI 2 - device pci 1a.0 on end # - PWM - device pci 1b.0 on end # - SDCARD - device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device pci 1f.1 on end # - SMBUS - end -end diff --git a/src/mainboard/intel/leafhill/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/intel/leafhill/variants/pyro/include/variant/acpi/dptf.asl deleted file mode 100644 index f14999c..0000000 --- a/src/mainboard/intel/leafhill/variants/pyro/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 57 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Battery" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 65 -#define DPTF_TSR2_CRITICAL 80 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 500, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 550, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 1600, /* PowerLimitMinimum */ - 12000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 6000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/intel/leafhill/variants/pyro/include/variant/ec.h b/src/mainboard/intel/leafhill/variants/pyro/include/variant/ec.h deleted file mode 100644 index 586f106..0000000 --- a/src/mainboard/intel/leafhill/variants/pyro/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/intel/leafhill/variants/pyro/include/variant/gpio.h b/src/mainboard/intel/leafhill/variants/pyro/include/variant/gpio.h deleted file mode 100644 index 6d1ce5a..0000000 --- a/src/mainboard/intel/leafhill/variants/pyro/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <baseboard/gpio.h> - -#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/intel/leafhill/variants/pyro/memory.c b/src/mainboard/intel/leafhill/variants/pyro/memory.c deleted file mode 100644 index 71ee060..0000000 --- a/src/mainboard/intel/leafhill/variants/pyro/memory.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <gpio.h> -#include <soc/meminit.h> -#include <variant/gpio.h> - - -static const struct lpddr4_sku skus[] = { - /* - * K4F6E304HB-MGCJ - both logical channels While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate - * the deneisty as 8Gb per rank. - */ - [0] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "K4F6E304HB-MGCJ", - }, - /* K4F8E304HB-MGCJ - both logical channels */ - [1] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "K4F8E304HB-MGCJ", - }, - /* - * MT53B512M32D2NP-062WT:C - both logical channels. While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate - * the deneisty as 8Gb per rank. - */ - [2] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "MT53B512M32D2NP", - .disable_periodic_retraining = 1, - }, - /* MT53B256M32D1NP-062 WT:C - both logical channels */ - [3] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "MT53B256M32D1NP", - .disable_periodic_retraining = 1, - }, - /* - * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate the - * density as 8Gb per rank. - */ - [4] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "H9HCNNNBPUMLHR", - }, - /* H9HCNNN8KUMLHR-NLE - both logical channels */ - [5] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "H9HCNNN8KUMLHR", - }, - /* Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch */ - [0xe] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "K4F6E304HB-MGCH", - }, - /* Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch */ - [0xf] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 0, - .ch1_dual_rank = 0, - .part_num = "K4F8E304HB-MGCH", - }, -}; - -static const struct lpddr4_cfg lp4cfg = { - .skus = skus, - .num_skus = ARRAY_SIZE(skus), - .swizzle_config = &baseboard_lpddr4_swizzle, -}; - -const struct lpddr4_cfg *variant_lpddr4_config(void) -{ - return &lp4cfg; -} diff --git a/src/mainboard/intel/leafhill/variants/reef/include/variant/acpi/dptf.asl b/src/mainboard/intel/leafhill/variants/reef/include/variant/acpi/dptf.asl deleted file mode 100644 index f3ff04b..0000000 --- a/src/mainboard/intel/leafhill/variants/reef/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/intel/leafhill/variants/reef/include/variant/ec.h b/src/mainboard/intel/leafhill/variants/reef/include/variant/ec.h deleted file mode 100644 index 586f106..0000000 --- a/src/mainboard/intel/leafhill/variants/reef/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/intel/leafhill/variants/reef/include/variant/gpio.h b/src/mainboard/intel/leafhill/variants/reef/include/variant/gpio.h deleted file mode 100644 index 6d1ce5a..0000000 --- a/src/mainboard/intel/leafhill/variants/reef/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <baseboard/gpio.h> - -#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/intel/leafhill/variants/snappy/devicetree.cb b/src/mainboard/intel/leafhill/variants/snappy/devicetree.cb deleted file mode 100644 index e46483e..0000000 --- a/src/mainboard/intel/leafhill/variants/snappy/devicetree.cb +++ /dev/null @@ -1,223 +0,0 @@ -chip soc/intel/apollolake - - device cpu_cluster 0 on - device lapic 0 on end - end - - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt - # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 44, - .fall_time_ns = 22, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 40, - .fall_time_ns = 20, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 70, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 20, - .fall_time_ns = 164, - }" - - # digitizer at 400kHz - register "i2c[5]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - - device domain 0 on - device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 - device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - device i2c 10 on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOM50C1_HID, - .cid = PNP0C50_CID, - .desc = WCOM_DT_DESC, - .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), - }" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 - device pci 19.0 on end # - SPI 0 - device pci 19.1 on end # - SPI 1 - device pci 19.2 on end # - SPI 2 - device pci 1a.0 on end # - PWM - device pci 1b.0 on end # - SDCARD - device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device pci 1f.1 on end # - SMBUS - end -end diff --git a/src/mainboard/intel/leafhill/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/intel/leafhill/variants/snappy/include/variant/acpi/dptf.asl deleted file mode 100644 index a233c92..0000000 --- a/src/mainboard/intel/leafhill/variants/snappy/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 100 -#define DPTF_CPU_CRITICAL 105 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Battery" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 53 -#define DPTF_TSR1_CRITICAL 80 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 90 -#define DPTF_TSR2_CRITICAL 100 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 200, 80, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 150, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 4000, /* PowerLimitMinimum */ - 12000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/intel/leafhill/variants/snappy/include/variant/ec.h b/src/mainboard/intel/leafhill/variants/snappy/include/variant/ec.h deleted file mode 100644 index 586f106..0000000 --- a/src/mainboard/intel/leafhill/variants/snappy/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/intel/leafhill/variants/snappy/include/variant/gpio.h b/src/mainboard/intel/leafhill/variants/snappy/include/variant/gpio.h deleted file mode 100644 index 6d1ce5a..0000000 --- a/src/mainboard/intel/leafhill/variants/snappy/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <baseboard/gpio.h> - -#endif /* MAINBOARD_GPIO_H */

1 0

← Newer
1
...
59
60
61
62
63
64
65
...
86
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2017