coreboot-gerrit January 2017

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New patch to review for coreboot: Revert "spi: Get rid of SPI_ATOMIC_SEQUENCING"
by Ronald G. Minnich 09 Jan '17

09 Jan '17

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18075 -gerrit commit 6fd68813bf9ce1855f62d456fa018d2f5c10707b Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Jan 9 15:24:32 2017 -0800 Revert "spi: Get rid of SPI_ATOMIC_SEQUENCING" It broke the KGPE-D16 This reverts commit c2973d196d1224a1253478dc29d5f8fa004eaab8. Change-Id: Ib7c598c8a1bfc14bbeac0074c7c5c82e1c7e4c5e Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- src/drivers/spi/Kconfig | 10 ++++ src/drivers/spi/spi-generic.c | 99 -------------------------------- src/drivers/spi/spi_flash.c | 47 ++++++++++----- src/include/spi-generic.h | 62 +------------------- src/mainboard/google/purin/Kconfig | 1 + src/soc/broadcom/cygnus/spi.c | 1 - src/soc/imgtec/pistachio/Kconfig | 1 + src/soc/imgtec/pistachio/spi.c | 7 ++- src/soc/intel/baytrail/spi.c | 1 - src/soc/intel/braswell/spi.c | 1 - src/soc/intel/broadwell/spi.c | 1 - src/soc/intel/fsp_baytrail/spi.c | 1 - src/soc/intel/fsp_broadwell_de/spi.c | 1 - src/soc/mediatek/mt8173/Kconfig | 1 + src/soc/mediatek/mt8173/spi.c | 1 - src/soc/qualcomm/ipq40xx/Kconfig | 1 + src/soc/qualcomm/ipq806x/Kconfig | 1 + src/southbridge/amd/agesa/hudson/spi.c | 1 - src/southbridge/amd/cimx/sb800/spi.c | 1 - src/southbridge/amd/sb700/spi.c | 1 - src/southbridge/intel/common/spi.c | 1 - src/southbridge/intel/fsp_rangeley/spi.c | 1 - 22 files changed, 54 insertions(+), 188 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index c8d86ff..b55de58 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -61,6 +61,16 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS default n if COMMON_CBFS_SPI_WRAPPER default y +config SPI_ATOMIC_SEQUENCING + bool + default y if ARCH_X86 + default n if !ARCH_X86 + help + Select this option if the SPI controller uses "atomic sequencing." + Atomic sequencing is when the sequence of commands is pre-programmed + in the SPI controller. Hardware manages the transaction instead of + software. This is common on x86 platforms. + config SPI_FLASH_SMM bool "SPI flash driver support in SMM" default n diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 805e17a..4fcd04c 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <assert.h> #include <spi-generic.h> #include <string.h> @@ -33,55 +32,10 @@ void spi_release_bus(const struct spi_slave *slave) ctrlr->release_bus(slave); } -static int spi_xfer_single_op(const struct spi_slave *slave, - struct spi_op *op) -{ - const struct spi_ctrlr *ctrlr = slave->ctrlr; - int ret; - - if (!ctrlr || !ctrlr->xfer) - return -1; - - ret = ctrlr->xfer(slave, op->dout, op->bytesout, op->din, op->bytesin); - if (ret) - op->status = SPI_OP_FAILURE; - else - op->status = SPI_OP_SUCCESS; - - return ret; -} - -static int spi_xfer_vector_default(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - size_t i; - int ret; - - for (i = 0; i < count; i++) { - ret = spi_xfer_single_op(slave, &vectors[i]); - if (ret) - return ret; - } - - return 0; -} - -int spi_xfer_vector(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - const struct spi_ctrlr *ctrlr = slave->ctrlr; - - if (ctrlr && ctrlr->xfer_vector) - return ctrlr->xfer_vector(slave, vectors, count); - - return spi_xfer_vector_default(slave, vectors, count); -} - int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { const struct spi_ctrlr *ctrlr = slave->ctrlr; - if (ctrlr && ctrlr->xfer) return ctrlr->xfer(slave, dout, bytesout, din, bytesin); @@ -122,56 +76,3 @@ int __attribute__((weak)) spi_setup_slave(unsigned int bus, unsigned int cs, return 0; } - -static int spi_xfer_combine_two_vectors(const struct spi_slave *slave, - struct spi_op *v1, struct spi_op *v2) -{ - struct spi_op op = { - .dout = v1->dout, .bytesout = v1->bytesout, - .din = v2->din, .bytesin = v2->bytesin, - }; - int ret; - - /* - * Combine two vectors only if: - * v1 has non-NULL dout and NULL din and - * v2 has non-NULL din and NULL dout and - * - * In all other cases, do not combine the two vectors. - */ - if ((!v1->dout || v1->din) || (v2->dout || !v2->din)) - return -1; - - ret = spi_xfer_single_op(slave, &op); - v1->status = v2->status = op.status; - - return ret; -} - -/* - * Helper function to allow chipsets to combine two vectors if possible. This - * function can only handle upto 2 vectors. - * - * Two vectors are combined if first vector has a non-NULL dout and NULL din and - * second vector has a non-NULL din and NULL dout. Otherwise, each vector is - * operated upon one at a time. - * - * Returns 0 on success and non-zero on failure. - */ -int spi_xfer_two_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - int ret; - - assert (count <= 2); - - if (count == 2) { - ret = spi_xfer_combine_two_vectors(slave, &vectors[0], - &vectors[1]); - - if (!ret || (vectors[0].status != SPI_OP_NOT_EXECUTED)) - return ret; - } - - return spi_xfer_vector_default(slave, vectors, count); -} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index a0e3105..3b4272b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -32,30 +32,47 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } +/* + * If atomic sequencing is used, the cycle type is known to the SPI + * controller so that it can perform consecutive transfers and arbitrate + * automatically. Otherwise the SPI controller transfers whatever the + * user requests immediately, without regard to sequence. Atomic + * sequencing is commonly used on x86 platforms. + * + * SPI flash commands are simple two-step sequences. The command byte is + * always written first and may be followed by an address. Then data is + * either read or written. For atomic sequencing we'll pass everything into + * spi_xfer() at once and let the controller handle the details. Otherwise + * we will write all output bytes first and then read if necessary. + * + * FIXME: This really should be abstracted better, but that will + * require overhauling the entire SPI infrastructure. + */ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { int ret = 1; - /* - * SPI flash requires command-response kind of behavior. Thus, two - * separate SPI vectors are required -- first to transmit dout and other - * to receive in din. If some specialized SPI flash controllers - * (e.g. x86) can perform both command and response together, it should - * be handled at SPI flash controller driver level. - */ - struct spi_op vectors[] = { - [0] = { .dout = dout, .bytesout = bytes_out, - .din = NULL, .bytesin = 0, }, - [1] = { .dout = NULL, .bytesout = 0, - .din = din, .bytesin = bytes_in }, - }; if (spi_claim_bus(spi)) return ret; - if (spi_xfer_vector(spi, vectors, ARRAY_SIZE(vectors)) == 0) - ret = 0; +#if CONFIG_SPI_ATOMIC_SEQUENCING == 1 + if (spi_xfer(spi, dout, bytes_out, din, bytes_in) < 0) + goto done; +#else + if (dout && bytes_out) { + if (spi_xfer(spi, dout, bytes_out, NULL, 0) < 0) + goto done; + } + + if (din && bytes_in) { + if (spi_xfer(spi, NULL, 0, din, bytes_in) < 0) + goto done; + } +#endif + ret = 0; +done: spi_release_bus(spi); return ret; } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 7eb18a6..d28fefd 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -36,46 +36,20 @@ struct spi_slave { const struct spi_ctrlr *ctrlr; }; -/* Representation of SPI operation status. */ -enum spi_op_status { - SPI_OP_NOT_EXECUTED = 0, - SPI_OP_SUCCESS = 1, - SPI_OP_FAILURE = 2, -}; - -/* - * Representation of a SPI operation. - * - * dout: Pointer to data to send. - * bytesout: Count of data in bytes to send. - * din: Pointer to store received data. - * bytesin: Count of data in bytes to receive. - */ -struct spi_op { - const void *dout; - size_t bytesout; - void *din; - size_t bytesin; - enum spi_op_status status; -}; - /*----------------------------------------------------------------------- * Representation of a SPI contoller. * * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. + * xfer: SPI transfer * setup: Setup given SPI device bus. - * xfer: Perform one SPI transfer operation. - * xfer_vector: Vector of SPI transfer operations. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); - int (*setup)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); - int (*xfer_vector)(const struct spi_slave *slave, - struct spi_op vectors[], size_t count); + int (*setup)(const struct spi_slave *slave); }; /*----------------------------------------------------------------------- @@ -160,19 +134,6 @@ void spi_release_bus(const struct spi_slave *slave); int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); -/*----------------------------------------------------------------------- - * Vector of SPI transfer operations - * - * spi_xfer_vector() interface: - * slave: The SPI slave which will be sending/receiving the data. - * vectors: Array of SPI op structures. - * count: Number of SPI op vectors. - * - * Returns: 0 on success, not 0 on failure - */ -int spi_xfer_vector(const struct spi_slave *slave, - struct spi_op vectors[], size_t count); - unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len); /*----------------------------------------------------------------------- @@ -197,23 +158,4 @@ static inline int spi_w8r8(const struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } -/* - * Helper function to allow chipsets to combine two vectors if possible. It can - * only handle upto 2 vectors. - * - * This function is provided to support command-response kind of transactions - * expected by users like flash. Some special SPI flash controllers can handle - * such command-response operations in a single transaction. For these special - * controllers, separate command and response vectors can be combined into a - * single operation. - * - * Two vectors are combined if first vector has a non-NULL dout and NULL din and - * second vector has a non-NULL din and NULL dout. Otherwise, each vector is - * operated upon one at a time. - * - * Returns 0 on success and non-zero on failure. - */ -int spi_xfer_two_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count); - #endif /* _SPI_GENERIC_H_ */ diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index ca0909b..eabab2b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO # required for the reference board BCM958305K + select SPI_ATOMIC_SEQUENCING config CHROMEOS select VBOOT_VBNV_FLASH diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index f03d453..e597efc 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -279,7 +279,6 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 1ce488c..da33cc5 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -22,6 +22,7 @@ config CPU_IMGTEC_PISTACHIO select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL + select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_HARD_RESET select UART_OVERRIDE_REFCLK diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index 2b706f0..e956e46 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -22,6 +22,10 @@ #include <string.h> #include <timer.h> +#if !CONFIG_SPI_ATOMIC_SEQUENCING +#error "Unsupported SPI driver API" +#endif + /* Imgtec controller uses 16 bit packet length. */ #define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) @@ -492,7 +496,7 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout, } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) + size_t bytesout, void *din, size_t bytesin) { unsigned int in_sz, out_sz; int ret; @@ -537,7 +541,6 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; /* Set up communications parameters for a SPI slave. */ diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 639954b..0f7b0c6 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -612,7 +612,6 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 86b3351..2a0ddf8 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -596,7 +596,6 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 7a7eaf7..d2ae943 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -646,7 +646,6 @@ int spi_flash_protect(u32 start, u32 size) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index dee7440..997bd13 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -592,7 +592,6 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index a6b6f35..5848966 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -609,7 +609,6 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 7a6ad87..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -9,6 +9,7 @@ config SOC_MEDIATEK_MT8173 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL + select SPI_ATOMIC_SEQUENCING if SPI_FLASH select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select GENERIC_GPIO_LIB diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 415764a..53d5b8c 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -293,7 +293,6 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 05f29e4..f738622 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -7,6 +7,7 @@ config SOC_QC_IPQ40XX select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL + select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 32b61bc..7ba5df5 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,6 +7,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL + select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB if SOC_QC_IPQ806X diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 00f6b29..8a4adfb 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -167,7 +167,6 @@ int chipset_volatile_group_end(const struct spi_flash *flash) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 1e84743..edf192a 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -158,7 +158,6 @@ int chipset_volatile_group_end(const struct spi_flash *flash) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 5d56415..2e16ca8 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -120,7 +120,6 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index ee94937..093017e 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -659,7 +659,6 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 0bffeb5..8026698 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -724,7 +724,6 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

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Patch merged into coreboot/master: .gitignore: Add utility binaries
by gerrit＠coreboot.org 09 Jan '17

09 Jan '17

the following patch was just integrated into master: commit f2f4b78dd2c5a0b79e1ef239d605f92e1caeb55a Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Dec 29 12:02:26 2016 -0700 .gitignore: Add utility binaries Change-Id: Iad84eda9949a60bcbde092ad8f4d7cd0bcbdb942 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/17991 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17991 for details. -gerrit

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Patch set updated for coreboot: chromeec: Update Chrome EC submodule
by Martin Roth 09 Jan '17

09 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18023 -gerrit commit ebee883afbd39014274d507b05dbbb3db5e3b98d Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 2 19:49:11 2017 -0700 chromeec: Update Chrome EC submodule Update to Chromium TOT with bcffec7f (reef: Cleanup battery code) 292 commits between Oct 28, 2016 and Jan 2, 2017 Change-Id: I6bc356b9e458bebaa5839375ff40dd7e0d6ccff1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/chromeec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/chromeec b/3rdparty/chromeec index ea1a869..bcffec7 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit ea1a8699e96425806abdd532d04da254ae093f6e +Subproject commit bcffec7fdc50e959cb298d094d8af472777dba75

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Patch set updated for coreboot: amd/mct/ddr3: Free malloced resources in failure branches
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18074 -gerrit commit d44c4ee26e01425637fbe33c41be7b743024b481 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:54:24 2017 -0600 amd/mct/ddr3: Free malloced resources in failure branches Malloced resources were not freed in failure branches during S3 parameter save. Clean up Coverity warnings by freeing resources in failure branches. Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4013c2e..f69b6c4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -1123,13 +1123,16 @@ int8_t save_mct_information_to_nvram(void) set_option("allow_spd_nvram_cache_restore", &nvram); printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n"); + free(persistent_data); return 0; } /* Obtain CBFS file offset */ s3nv_offset = get_s3nv_file_offset(); - if (s3nv_offset == -1) + if (s3nv_offset == -1) { + free(persistent_data); return -1; + } /* Align flash pointer to nearest boundary */ s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1);

1 0

Patch set updated for coreboot: amd/mct/ddr3: Rework memory speed to clock value conversion logic
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18073 -gerrit commit 278ebfbfeaae8dda7b0b6e73bb20e6b01e2fc99c Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:27:09 2017 -0600 amd/mct/ddr3: Rework memory speed to clock value conversion logic The existing DRAM clock speed to configuration value logic contained an error resulting in a theoretical out of bounds read. While this would not be hit on real hardware, it was prudent to clean up the logic to avoid the associated Coverity warning. Found-by: Coverity Scan #1347353 Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 89e76eb..e93a7bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -256,11 +256,11 @@ static uint16_t fam15h_mhz_to_memclk_config(uint16_t freq) /* Compute the index value for the given frequency */ for (iter = 0; iter <= 0x16; iter++) { - if (fam15h_freq_tab[iter] == freq) + if (fam15h_freq_tab[iter] == freq) { + freq = iter; break; + } } - if (fam15h_freq_tab[iter] == freq) - freq = iter; if (freq == 0) freq = 0x4; @@ -274,11 +274,11 @@ static uint16_t fam10h_mhz_to_memclk_config(uint16_t freq) /* Compute the index value for the given frequency */ for (iter = 0; iter <= 0x6; iter++) { - if (fam10h_freq_tab[iter] == freq) + if (fam10h_freq_tab[iter] == freq) { + freq = iter; break; + } } - if (fam10h_freq_tab[iter] == freq) - freq = iter; if (freq == 0) freq = 0x3;

1 0

New patch to review for coreboot: amd/mct/ddr3: Free malloced resources in failure branches
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18074 -gerrit commit dd33e0e51a104f61c2b5d1ea7f7e68384882f279 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:54:24 2017 -0600 amd/mct/ddr3: Free malloced resources in failure branches Malloced resources were not freed in failure branches during S3 parameter save. Clean up Coverity warnings by freeing resources in failure branches. Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4013c2e..f69b6c4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -1123,13 +1123,16 @@ int8_t save_mct_information_to_nvram(void) set_option("allow_spd_nvram_cache_restore", &nvram); printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n"); + free(persistent_data); return 0; } /* Obtain CBFS file offset */ s3nv_offset = get_s3nv_file_offset(); - if (s3nv_offset == -1) + if (s3nv_offset == -1) { + free(persistent_data); return -1; + } /* Align flash pointer to nearest boundary */ s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1);

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New patch to review for coreboot: amd/mct/ddr3: Rework mmeory speed to clock value conversion logic
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18073 -gerrit commit ea2842a648c3cc2c24b631f8aa4c8ae17aeca427 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:27:09 2017 -0600 amd/mct/ddr3: Rework mmeory speed to clock value conversion logic The existing DRAM clock speed to configuration value logic contained an error resulting in a theoretical out of bounds read. While this would not be hit on real hardware, it was prudent to clean up the logic to avoid the associated Coverity warning. Found-by: Coverity Scan #1347353 Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 89e76eb..e93a7bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -256,11 +256,11 @@ static uint16_t fam15h_mhz_to_memclk_config(uint16_t freq) /* Compute the index value for the given frequency */ for (iter = 0; iter <= 0x16; iter++) { - if (fam15h_freq_tab[iter] == freq) + if (fam15h_freq_tab[iter] == freq) { + freq = iter; break; + } } - if (fam15h_freq_tab[iter] == freq) - freq = iter; if (freq == 0) freq = 0x4; @@ -274,11 +274,11 @@ static uint16_t fam10h_mhz_to_memclk_config(uint16_t freq) /* Compute the index value for the given frequency */ for (iter = 0; iter <= 0x6; iter++) { - if (fam10h_freq_tab[iter] == freq) + if (fam10h_freq_tab[iter] == freq) { + freq = iter; break; + } } - if (fam10h_freq_tab[iter] == freq) - freq = iter; if (freq == 0) freq = 0x3;

1 0

New patch to review for coreboot: amd/mct/ddr3: Correctly program maximum read latency
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18072 -gerrit commit b2506e740078661a54e78ccd6f8820dc65d75f90 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:19:37 2017 -0600 amd/mct/ddr3: Correctly program maximum read latency The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. Found-by: Coverity Scan #1347354 Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index fd8a8e7..984f604 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1484,8 +1484,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } } - /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0); + /* Calculate and program MaxRdLatency for both channels */ + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 0, 0); + Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 1, 0); if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);

1 0

New patch to review for coreboot: amd/mct/ddr3: Allow critical delay delta to go negative
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18071 -gerrit commit 431d8235e2c395ba7c2129ec52eb94bca79b3907 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 14:10:25 2017 -0600 amd/mct/ddr3: Allow critical delay delta to go negative The critical delay delta was incorrectly specified as an unsigned short. Use a signed short instead. Found-by: Coverity Scan #1347355 Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 958b382..89e76eb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3028,7 +3028,7 @@ void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, uint8_t lane; uint8_t dimm; uint16_t max_cdd_we_delta; - uint16_t cdd_trwtto_we_delta; + int16_t cdd_trwtto_we_delta; uint8_t receiver; uint8_t lane_count; uint8_t x4_present = 0;

1 0

Patch set updated for coreboot: amd/mct/ddr3: Correctly configure CsMux45
by Timothy Pearson 09 Jan '17

09 Jan '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18070 -gerrit commit abf01a36cc7069f5093267327d409f4606bdb61f Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jan 9 13:19:29 2017 -0600 amd/mct/ddr3: Correctly configure CsMux45 The existing logic to set up CsMux45 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Found-by: Coverity Scan #1347385 Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index 07bde27..48658f5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -43,7 +43,7 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, if ((((f2x80 & 0xf) == 0x7) || ((f2x80 & 0xf) == 0x9)) && ((f2x60 & 0x3) == 0x3)) cs_mux_45 = 1; - else if ((((f2x80 & 0xa) == 0x7) || ((f2x80 & 0xb) == 0x9)) + else if ((((f2x80 & 0xf) == 0xa) || ((f2x80 & 0xf) == 0xb)) && ((f2x60 & 0x3) > 0x1)) cs_mux_45 = 1; else

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coreboot-gerrit January 2017