the following patch was just integrated into master:
commit ec74f45e725c046423ecb6a7608678f22a8d7224
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Tue Jan 10 15:44:47 2017 +0100
drivers/net/rt8168: Add a macaddress cbfsfile using Kconfig
The default macaddress in rt8168.c can be changed with a cbfsfile
called macaddress. This patch makes it possible to add such a file
using Kconfig at build time.
This also changes the name of the cbfsfile from "macaddress" to
"rt8168-macaddress" to avoid confusion.
Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18088
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/18088 for details.
-gerrit
Keith Tzeng (keith.tzeng(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18227
-gerrit
commit f32f370a69e56a58959cebca7484da5835ae93cb
Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
Date: Wed Jan 25 16:20:26 2017 +0800
google/pyro: Disable Wacom touchscreen probed
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
src/mainboard/google/reef/variants/pyro/devicetree.cb | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 193fdd8..43e4c3d 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -171,7 +171,6 @@ chip soc/intel/apollolake
.cid = PNP0C50_CID,
.desc = WCOM_TS_DESC,
.irq = IRQ_LEVEL_LOW(GPIO_21_IRQ),
- .probed = 1,
}"
register "hid_desc_reg_offset" = "0x1"
device i2c 0xA on end
Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18242
-gerrit
commit 33992b5644cc49b97ba30bffbd4658139c597c36
Author: Iru Cai <mytbk920423(a)gmail.com>
Date: Thu Jan 26 20:33:29 2017 +0800
autoport: add missing parameter for pc_keyboard_init()
This fixes the build for the generated code for boards with PS/2
keyboard, since commit 448e386309c updated the pc_keyboard_init()
function.
Change-Id: I776b49b847985296eaca4af6d6e49ab5d6abbafe
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
util/autoport/ec_fixme.go | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go
index 1e9265a..f06d457 100644
--- a/util/autoport/ec_fixme.go
+++ b/util/autoport/ec_fixme.go
@@ -65,7 +65,7 @@ Method(_PTS,1)
if hasKeyboard {
si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n")
- MainboardInit += fmt.Sprintf("\tpc_keyboard_init();\n")
+ MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n")
MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h")
}
Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18206
-gerrit
commit e4a1395c59c64aa9f0d63a110cf86b4c49951399
Author: Nicola Corna <nicola(a)corna.info>
Date: Mon Jan 23 15:29:03 2017 +0100
sb/intel/common: Hook up me_cleaner
The me_cleaner option is available on multiple platforms:
* Sandy and Ivy Bridge (well tested by multiple users).
* Skylake and Braswell (tested).
* Haswell, Broadwell and Bay Trail (untested).
The untested platforms have been included anyways because all the
firmwares are very similar and Intel ME/TXE probably behaves in the
same way.
Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa
Signed-off-by: Nicola Corna <nicola(a)corna.info>
---
src/southbridge/intel/common/firmware/Kconfig | 28 ++++++++++++++++++++++
src/southbridge/intel/common/firmware/Makefile.inc | 5 ++++
2 files changed, 33 insertions(+)
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index c36b235..6f40a33 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -58,6 +58,34 @@ config ME_BIN_PATH
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
depends on HAVE_ME_BIN
+config USE_ME_CLEANER
+ bool "Strip down the Intel ME/TXE firmware"
+ depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_SANDYBRIDGE || \
+ NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \
+ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \
+ SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL)
+ help
+ Use me_cleaner to remove all the non-fundamental code from the Intel
+ ME/TXE firmware.
+ The resulting Intel ME/TXE firmware will have only the code
+ responsible for the very basic hardware initialization, leaving the
+ ME/TXE subsystem essentially in a disabled state.
+
+ Don't flash a modified ME/TXE firmware and a new coreboot image at the
+ same time, test them in two different steps.
+
+ WARNING: this tool isn't based on any official Intel documentation but
+ only on reverse engineering and trial & error.
+
+ See the project's page
+ https://github.com/corna/me_cleaner
+ or the wiki
+ https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
+ https://github.com/corna/me_cleaner/wiki/me_cleaner-status
+ for more info about this tool
+
+ If unsure, say N.
+
config HAVE_GBE_BIN
bool "Add gigabit ethernet firmware"
depends on HAVE_IFD_BIN
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
index 17e53b5..98a36d3 100644
--- a/src/southbridge/intel/common/firmware/Makefile.inc
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -58,6 +58,11 @@ ifeq ($(CONFIG_HAVE_ME_BIN),y)
$(obj)/coreboot.pre
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
endif
+ifeq ($(CONFIG_USE_ME_CLEANER),y)
+ printf " ME_CLEANER coreboot.pre\n"
+ util/me_cleaner/me_cleaner.py $(obj)/coreboot.pre > \
+ $(obj)/me_cleaner.log
+endif
ifeq ($(CONFIG_HAVE_GBE_BIN),y)
printf " IFDTOOL gbe.bin -> coreboot.pre\n"
$(objutil)/ifdtool/ifdtool \
Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14209
-gerrit
commit 73ef2ad0fbb4b9db99549dd9ce42c81796dfb499
Author: Iru Cai <mytbk920423(a)gmail.com>
Date: Thu Mar 31 23:13:09 2016 +0800
hp/2760p: reserve space in bootblock
The space started from 0x7ff700 is reserved for data needed by (maybe)
EC.
Change-Id: Iae7eb8a67fcce173500d91951ee71a3361475fc9
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
src/mainboard/hp/2760p/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig
index 440c1f6..295785f 100644
--- a/src/mainboard/hp/2760p/Kconfig
+++ b/src/mainboard/hp/2760p/Kconfig
@@ -62,4 +62,13 @@ config MAX_CPUS
config USBDEBUG_HCD_INDEX
int
default 1
+
+config ID_SECTION_OFFSET
+ hex
+ default 0x900
+
+config RESERVED_SPACE_BEFORE_RESET_VECTOR
+ hex
+ default 0xa00
+
endif
Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14208
-gerrit
commit 3dcca6a35ff88ff953d8e2cd74bc02ed1b71b47d
Author: Iru Cai <mytbk920423(a)gmail.com>
Date: Thu Mar 31 15:32:25 2016 +0800
[RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR
HP Elitebook 2760p (and some other HP laptops) stores some data which
may be used by EC in bootblock region. So some space needs to be
reserved before the reset vector.
Change-Id: I992d285a1a76883ff7a69445a0ff9efe62dbbd7f
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
src/arch/x86/Kconfig | 4 ++++
src/arch/x86/failover.ld | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 6280024..1daddd9 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -181,6 +181,10 @@ config ID_SECTION_OFFSET
hex
default 0x80
+config RESERVED_SPACE_BEFORE_RESET_VECTOR
+ hex
+ default 0xf0
+
# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK.
config C_ENV_BOOTBLOCK_SIZE
hex
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
index e9613d9..a434704 100644
--- a/src/arch/x86/failover.ld
+++ b/src/arch/x86/failover.ld
@@ -50,8 +50,8 @@ SECTIONS
* may cause the total size of a section to change when the start
* address gets applied.
*/
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
+ ROMLOC_MIN = 0xfffffff0 - CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR
+ - (_erom - _rom + 16) - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
/* Post-check proper SIPI vector. */
_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),