coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/google/snappy: Update WDT touchscreen device
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18240 -gerrit commit 34917bd1a6d7d56fe03d249aef15bc1c44c5b667 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 19:29:06 2017 -0800 mainboard/google/snappy: Update WDT touchscreen device Export PowerResource for WDT touchscreen device. BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Compiles successfully. Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/snappy/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index a8c1e74..42c6731 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -190,6 +190,8 @@ chip soc/intel/apollolake register "generic.probed" = "1" register "generic.pwr_mgmt_type" = "GPIO_EXPORT" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end

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Patch set updated for coreboot: mainboard/google/pryo: Update touchscreen device ACPI nodes
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18239 -gerrit commit 9be58307e6c03af4420e991b083c0e61143f4b25 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 19:15:49 2017 -0800 mainboard/google/pryo: Update touchscreen device ACPI nodes 1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 193fdd8..4713efe 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -172,6 +172,9 @@ chip soc/intel/apollolake .desc = WCOM_TS_DESC, .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), .probed = 1, + .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), + .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152), + .has_power_resource = 1, }" register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end @@ -181,14 +184,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18238 -gerrit commit 1555b67078af5e0f9087c4d12c9f5cf5945b7467 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 17:53:01 2017 -0800 i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI Linux kernel expects that power management with ACPI should always be handled using PowerResource. However, some kernel drivers (e.g. ELAN touchscreen) check to see if reset gpio is passed in by the BIOS to decide whether the device loses power in suspend. Thus, until the kernel has a better way for drivers to query if device lost power in suspend, we need to allow passing in of GPIOs via _CRS as well as exporting PowerResource to control power to the device. Update mainboards to export reset GPIO as well as PowerResource for ELAN touchscreen device. BUG=chrome-os-partner:62311,chrome-os-partner:60194 BRANCH=reef TEST=Verified that touchscreen works on power-on as well as after suspend-resume. Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 12 +++++------- src/drivers/i2c/generic/generic.c | 4 ++-- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 14 +++++--------- src/mainboard/google/reef/variants/snappy/devicetree.cb | 14 +++++--------- src/mainboard/intel/leafhill/devicetree.cb | 14 +++++--------- 5 files changed, 22 insertions(+), 36 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 19c6596..50a372d 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -19,11 +19,6 @@ #include <arch/acpi_device.h> #include <device/i2c.h> -enum power_mgmt_type { - POWER_RESOURCE = 1, - GPIO_EXPORT = 2, -}; - struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ @@ -47,8 +42,11 @@ struct drivers_i2c_generic_config { unsigned device_present_gpio; unsigned device_present_gpio_invert; - /* Power management type. */ - enum power_mgmt_type pwr_mgmt_type; + /* Do we need to export reset and enable GPIOs in _CRS? */ + bool export_gpio_to_crs; + + /* Does the device have a power resource? */ + bool has_power_resource; /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 4cf3e9e..35821dd 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -32,7 +32,7 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) unsigned reset_gpio = config->reset_gpio.pins[0]; unsigned enable_gpio = config->enable_gpio.pins[0]; - if (config->pwr_mgmt_type != POWER_RESOURCE) + if (!config->has_power_resource) return; if (!reset_gpio && !enable_gpio) @@ -72,7 +72,7 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) static bool i2c_generic_add_gpios_to_crs(struct drivers_i2c_generic_config *cfg) { - if (cfg->pwr_mgmt_type == GPIO_EXPORT) + if (cfg->export_gpio_to_crs) return true; return false; diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 7db4f15..c9bbca9 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -177,16 +177,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3 diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index e498533..a8c1e74 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -175,16 +175,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end chip drivers/i2c/hid diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 7db4f15..c9bbca9 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -177,16 +177,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: mainboard/google/pryo: Update touchscreen device ACPI nodes
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18239 -gerrit commit 023c258d998e78416d0bee021a7e33cb89f9ca42 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 19:15:49 2017 -0800 mainboard/google/pryo: Update touchscreen device ACPI nodes 1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 193fdd8..4713efe 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -172,6 +172,9 @@ chip soc/intel/apollolake .desc = WCOM_TS_DESC, .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), .probed = 1, + .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), + .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152), + .has_power_resource = 1, }" register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end @@ -181,14 +184,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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New patch to review for coreboot: mainboard/google/pryo: Update touchscreen device ACPI nodes
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18239 -gerrit commit dd552c0129707132f96adcc540f226dd63c9a86b Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 19:05:18 2017 -0800 mainboard/google/pryo: Update touchscreen device ACPI nodes 1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- 3rdparty/arm-trusted-firmware | 2 +- 3rdparty/chromeec | 2 +- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++-------- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 236c27d..bfd9251 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 236c27d21f52ad8f0a998e54774e3d8a4b59129d +Subproject commit bfd925139fdbc2e87979849907b34843aa326994 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index bcffec7..ea1a869 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit bcffec7fdc50e959cb298d094d8af472777dba75 +Subproject commit ea1a8699e96425806abdd532d04da254ae093f6e diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 193fdd8..4713efe 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -172,6 +172,9 @@ chip soc/intel/apollolake .desc = WCOM_TS_DESC, .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), .probed = 1, + .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), + .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152), + .has_power_resource = 1, }" register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end @@ -181,14 +184,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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New patch to review for coreboot: i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18238 -gerrit commit 43d8bc10f408ae89d15a3f9aff6766868e2ebcb4 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 17:53:01 2017 -0800 i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI Linux kernel expects that power management with ACPI should always be handled using PowerResource. However, some kernel drivers (e.g. ELAN touchscreen) check to see if reset gpio is passed in by the BIOS to decide whether the device loses power in suspend. Thus, until the kernel has a better way for drivers to query if device lost power in suspend, we need to allow passing in of GPIOs via _CRS as well as exporting PowerResource to control power to the device. Update reef to export reset GPIO as well as PowerResource for touchscreen device. BUG=chrome-os-partner:62311,chrome-os-partner:60194 BRANCH=reef TEST=Verified that touchscreen works on power-on as well as after suspend-resume. Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 12 +++++------- src/drivers/i2c/generic/generic.c | 4 ++-- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 14 +++++--------- 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 19c6596..50a372d 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -19,11 +19,6 @@ #include <arch/acpi_device.h> #include <device/i2c.h> -enum power_mgmt_type { - POWER_RESOURCE = 1, - GPIO_EXPORT = 2, -}; - struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ @@ -47,8 +42,11 @@ struct drivers_i2c_generic_config { unsigned device_present_gpio; unsigned device_present_gpio_invert; - /* Power management type. */ - enum power_mgmt_type pwr_mgmt_type; + /* Do we need to export reset and enable GPIOs in _CRS? */ + bool export_gpio_to_crs; + + /* Does the device have a power resource? */ + bool has_power_resource; /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 4cf3e9e..35821dd 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -32,7 +32,7 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) unsigned reset_gpio = config->reset_gpio.pins[0]; unsigned enable_gpio = config->enable_gpio.pins[0]; - if (config->pwr_mgmt_type != POWER_RESOURCE) + if (!config->has_power_resource) return; if (!reset_gpio && !enable_gpio) @@ -72,7 +72,7 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) static bool i2c_generic_add_gpios_to_crs(struct drivers_i2c_generic_config *cfg) { - if (cfg->pwr_mgmt_type == GPIO_EXPORT) + if (cfg->export_gpio_to_crs) return true; return false; diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 7db4f15..c9bbca9 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -177,16 +177,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: board_status/towiki.sh: Add socket LGA775
by Arthur Heymans 25 Jan '17

25 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18235 -gerrit commit ab1702c4883dbb1f8141e45ab72d1c4bb338fcc8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Jan 25 18:38:36 2017 +0100 board_status/towiki.sh: Add socket LGA775 Intel Core 2 is not further specified since not all chipset support quad cores, which could confuse users. Change-Id: I86c0a41743fe784f432347fa639d3c26604e058e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/board_status/to-wiki/towiki.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 2e458c6..8b2d1af 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -307,6 +307,9 @@ EOF INTEL_SOCKET_LGA771) cpu_nice="Intel Xeon™ 5000 series"; socket_nice="Socket LGA771";; + INTEL_SOCKET_LGA775) + cpu_nice="Intel® Core 2, Pentium 4/D"; + socket_nice="Socket LGA775";; INTEL_SOCKET_PGA370) cpu_nice="Intel® Pentium® III-800, Celeron®" socket_nice="Socket 370";;

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Patch set updated for coreboot: board_status/towiki.sh: Add socket LGA775
by Arthur Heymans 25 Jan '17

25 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18235 -gerrit commit 1b020ca3c4291c444fe1b46b7379a9a3e49bf6e1 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Jan 25 18:38:36 2017 +0100 board_status/towiki.sh: Add socket LGA775 Intel Core 2 is not further specified since not all chipset support quad cores, which could confuse users. Change-Id: I86c0a41743fe784f432347fa639d3c26604e058e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/board_status/to-wiki/towiki.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 2e458c6..66635c8 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -307,6 +307,9 @@ EOF INTEL_SOCKET_LGA771) cpu_nice="Intel Xeon™ 5000 series"; socket_nice="Socket LGA771";; + INTEL_SOCKT_LGA775) + cpu_nice="Intel® Core 2, Pentium 4/D"; + socket_nice="Socket LGA775";; INTEL_SOCKET_PGA370) cpu_nice="Intel® Pentium® III-800, Celeron®" socket_nice="Socket 370";;

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Patch merged into coreboot/master: mb/intel/d510mo: Add cmos.layout and cmos.default
by gerrit＠coreboot.org 25 Jan '17

25 Jan '17

the following patch was just integrated into master: commit dcad289841836f37ae8b885f59b80ecad690a22f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 17:40:18 2017 +0100 mb/intel/d510mo: Add cmos.layout and cmos.default Change-Id: I877d4470b697d6a6d4652ed1c60028cdcbe8df98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18143 for details. -gerrit

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New patch to review for coreboot: drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos value
by Martin Roth 25 Jan '17

25 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18236 -gerrit commit 32050a709e9c9431e17952bacfe663f85b12965c Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 25 11:00:18 2017 -0700 drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos value If cmos is invalid, it doesn't make sense to read the value before finding that out. Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/pc80/rtc/mc146818rtc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 0d36b00..a102917 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -251,14 +251,14 @@ enum cb_err get_option(void *dest, const char *name) return CB_CMOS_OPTION_NOT_FOUND; } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_ACCESS_ERROR; - } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_CHECKSUM_INVALID; } + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_ACCESS_ERROR; + } UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_SUCCESS; }

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coreboot-gerrit January 2017