Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18235
-gerrit
commit 9f3cc72ed8e69d682eb0101268f15408813f7d6b
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Wed Jan 25 18:38:36 2017 +0100
board_status/towiki.sh: Add socket LGA775
Intel Core 2 is not furter specified since not all chipset support
quad cores, which could confuse users.
Change-Id: I86c0a41743fe784f432347fa639d3c26604e058e
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
util/board_status/to-wiki/towiki.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh
index 2e458c6..66635c8 100755
--- a/util/board_status/to-wiki/towiki.sh
+++ b/util/board_status/to-wiki/towiki.sh
@@ -307,6 +307,9 @@ EOF
INTEL_SOCKET_LGA771)
cpu_nice="Intel Xeon™ 5000 series";
socket_nice="Socket LGA771";;
+ INTEL_SOCKT_LGA775)
+ cpu_nice="Intel® Core 2, Pentium 4/D";
+ socket_nice="Socket LGA775";;
INTEL_SOCKET_PGA370)
cpu_nice="Intel® Pentium® III-800, Celeron®"
socket_nice="Socket 370";;
the following patch was just integrated into master:
commit 2a0e998ec2d1625c214bf181189bd61ce425f0ed
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Sat Jan 14 17:32:20 2017 +0100
nb/intel/pineview: Make preallocated igd memory a cmos parameter
Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18142
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/18142 for details.
-gerrit
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18231
-gerrit
commit 47bb22dad8cb456912d112d078a28d2db3061b09
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Wed Jan 25 15:21:08 2017 +0100
Only add etc/ps2-keyboard-spinup when not updating an image
Without this motherboards that requires a non zero timeout for ps2
keyboards on SeaBIOS don't build when CONFIG_UPDATE_IMAGE is set.
An alternative way to achieve this file would be to include a cbfsfile
instead of calling cbfstool. That way the file gets updated/added both
both image update and regular build. A difficulty of that approach is
that it needs to convert a decimal to a binary in little endian
representation, which is not a trivial thing to do in a Makefile.
Change-Id: Icafba8d3e279a2e70e607abba81e3dbebfb55e4b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
Makefile.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Makefile.inc b/Makefile.inc
index 0c6b351..ee3449c 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -886,10 +886,12 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(
dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null
ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),)
ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0)
+ifneq ($(CONFIG_UPDATE_IMAGE),y)
@printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n"
$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup
endif
endif
+endif
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
@printf " UPDATE-FIT\n"
the following patch was just integrated into master:
commit 9bcc002f1e7958c7b4234ea804b5b2b4f675ea3a
Author: Nicola Corna <nicola(a)corna.info>
Date: Mon Jan 23 15:28:24 2017 +0100
util: Add me_cleaner
me_cleaner is a tool to strip down Intel ME/TXE images by removing all
the non-fundamental code, while keeping the ME/TXE image valid and
suitable for booting the system. The remaining code (ROMP and BUP
modules) is the one responsible for the very basic initialization of
the ME/TXE subsystem and can't be removed.
This tool exploits the fact that:
* Each ME/TXE partition is signed individually and it is possible to
remove both the partition and the signature.
* The ME/TXE modules are not signed directly, instead they are hashed
and the list of their hashes is hashed again and signed: this
means that modifying a module doesn't invalidate the signature,
but only the hash of that single module.
* The modules hashes are checked only when the corresponding module
needs to be executed.
* The system can boot after the execution of the first module (BUP,
inside the FTPR partition), even if the subsequent stages fail.
Currently me_cleaner works on every Intel platform with Intel ME or
Intel TXE with the following limitations:
* Doesn't work when Intel Boot Guard is set in Verified Boot mode.
* Doesn't fully work on Nehalem yet.
* On Skylake and later generations, since the partitions' internal
structure has changed, me_cleaner leaves intact the FTPR
partition, removing all the the other partitions.
This tool has been tested on multiple platforms and architectures by
different users, and seems to be stable. The reports are available
here:
https://github.com/corna/me_cleaner/issues/3
A more in-depth description of me_cleaner is available here:
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
Change-Id: I9013799e9adea0dea0775b9afe718de5fc4ca748
Signed-off-by: Nicola Corna <nicola(a)corna.info>
Reviewed-on: https://review.coreboot.org/18203
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/18203 for details.
-gerrit
Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18227
-gerrit
commit c032cb677aba4a2f81930528acd08aa219f96549
Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
Date: Wed Jan 25 16:20:26 2017 +0800
google/pyro: Disable Wacom touchscreen probed
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for kernel before init it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
src/mainboard/google/reef/variants/pyro/devicetree.cb | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 193fdd8..43e4c3d 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -171,7 +171,6 @@ chip soc/intel/apollolake
.cid = PNP0C50_CID,
.desc = WCOM_TS_DESC,
.irq = IRQ_LEVEL_LOW(GPIO_21_IRQ),
- .probed = 1,
}"
register "hid_desc_reg_offset" = "0x1"
device i2c 0xA on end
the following patch was just integrated into master:
commit b144a34c6031ef988d32946129920672d29d38a9
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Jan 25 14:21:12 2017 +0100
libpayload: fix build
When .xcompile doesn't already exist, building libpayload fails because
the CC variable (et al) remain empty since .xcompile is only included
after the variables coming from there are evaluated.
Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18228
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/18228 for details.
-gerrit
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18233
-gerrit
commit ec7979aefd630666e8d9e18bcbc5e0d39455262a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Jan 25 10:54:59 2017 -0600
mainboard/google/reef: disable touchscreen power in S3/S5 states
The touchscreen, if available, should never be a wake source.
Therefore, ensure the load switch is disabled for it whenever
a S3 or S5 sleep state is entered.
BUG=chrome-os-partner:61728,chrome-os-partner:62311
BRANCH=reef
TEST=Built. Suspend/resumed.
Change-Id: I720031ae28fc2a7a615085920c6522c2301a268f
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/reef/variants/baseboard/gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index 390ef0f..934703a 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -372,6 +372,7 @@ variant_early_gpio_table(size_t *num)
static const struct pad_config sleep_gpio_table[] = {
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+ PAD_CFG_GPO(GPIO_152, 0, DEEP), /* Disable touchscreen power. */
};
const struct pad_config * __attribute__((weak))
Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18227
-gerrit
commit e1d0a8e4c2c79ca72bb3624543306950aed27527
Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
Date: Wed Jan 25 16:20:26 2017 +0800
google/pyro: Disable Wacom touchscreen probed
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for kernel before init it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 193fdd8..076679c 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -171,7 +171,7 @@ chip soc/intel/apollolake
.cid = PNP0C50_CID,
.desc = WCOM_TS_DESC,
.irq = IRQ_LEVEL_LOW(GPIO_21_IRQ),
- .probed = 1,
+ .probed = 0,
}"
register "hid_desc_reg_offset" = "0x1"
device i2c 0xA on end
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18148
-gerrit
commit 2452f559081e1b8e996ebbe2fc4cd08839561609
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Sun Jan 15 14:24:56 2017 +0100
Allow to add a second bootblock at a 64K offset for BUC.TS
This allows to add a second bootblock at an offset of 64K in order for
it to be used if the BUC.TS bit, RCBA(0x3414)[BIT0], is set.
This method is often used to flash coreboot when the vendor BIOS only
write protects its bootblock at the bottom of flash (e.g. Lenovo
thinkpad X60 and T60), but can also be used to have a backup while
hacking on bootblock code.
TESTED on Thinkpad x60 and x200 (with with the line in romstage.c
RCBA32(0x3410) = 0x00100461 changed to RCBA32(0x3410) = 0x00100460).
Change-Id: I37e288e710edbe41651d09d2a6981a571df69bde
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
Makefile.inc | 16 ++++++++++++++++
src/southbridge/intel/common/Kconfig | 18 ++++++++++++++++++
src/southbridge/intel/i82801gx/Kconfig | 1 +
src/southbridge/intel/i82801ix/Kconfig | 1 +
4 files changed, 36 insertions(+)
diff --git a/Makefile.inc b/Makefile.inc
index c5ce30f..5b1dae7 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -844,6 +844,14 @@ ifeq ($(CONFIG_ARCH_X86),y)
-n bootblock \
-t bootblock \
-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes)
+ifeq ($(CONFIG_BUCTS_BOOTBLOCK),y)
+ $(CBFSTOOL) $@.tmp add \
+ -f $(objcbfs)/bootblock.bin \
+ -n bootblock_bucts \
+ -t bootblock \
+ -b -$(call int-add,$(call file-size,$(objcbfs)/bootblock.bin) \
+ $(CONFIG_BUC_TOP_SWAP_SIZE)) $(cbfs-autogen-attributes)
+endif # ifeq CONFIG_BUCTS_BOOTBLOCK
else # ifeq ($(CONFIG_ARCH_X86),y)
$(CBFSTOOL) $@.tmp write -u \
-r BOOTBLOCK \
@@ -869,6 +877,14 @@ $(obj)/coreboot.pre: $$(prebuilt-files) $(CBFSTOOL)
echo "Exiting." && \
false)
$(prebuild-files) true
+ifeq ($(CONFIG_BUCTS_BOOTBLOCK),y)
+ $(CBFSTOOL) $@.tmp add \
+ -f $(objcbfs)/bootblock.bin \
+ -n bootblock_bucts \
+ -t bootblock \
+ -b -$(call int-add,$(call file-size,$(objcbfs)/bootblock.bin) \
+ $(CONFIG_BUC_TOP_SWAP_SIZE)) $(cbfs-autogen-attributes)
+endif # ifeq CONFIG_BUCTS_BOOTBLOCK
mv $@.tmp $@
endif # ifneq ($(CONFIG_UPDATE_IMAGE),y)
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 7bc686d..a651c80 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -2,3 +2,21 @@ config SOUTHBRIDGE_INTEL_COMMON
def_bool n
config SOUTHBRIDGE_INTEL_COMMON_GPIO
def_bool n
+config HAVE_BUCTS
+ bool
+ default n
+config BUCTS_BOOTBLOCK
+ bool "Include a BUC.TS bootblock"
+ default n
+ depends on HAVE_BUCTS
+ help
+ Some vendor BIOS only write protect their bootblock.
+ Using the buc.ts register RCBA[0x3414], it is possible to have
+ the southbridge look for the bootblock at a 64K offset
+ instead of the usual top of flash, which might not be
+ write protected.
+ Select this to put a 'second' bootblock at a 64K offset.
+config BUC_TOP_SWAP_SIZE
+ hex
+ depends on BUCTS_BOOTBLOCK
+ default 0x10000
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index b2265c4..4eb2835 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select HAVE_SMI_HANDLER
select COMMON_FADT
select SOUTHBRIDGE_INTEL_COMMON_GPIO
+ select HAVE_BUCTS
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index e4d1f91..0928a8a 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -25,6 +25,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
select HAVE_USBDEBUG_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select HAVE_INTEL_FIRMWARE
+ select HAVE_BUCTS
if SOUTHBRIDGE_INTEL_I82801IX