coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: amd/amdht: Fix format security errors
by gerrit＠coreboot.org 26 Jan '17

26 Jan '17

the following patch was just integrated into master: commit f6776fa62c84ae516f84c99859d826f77d508079 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Fri Jan 20 14:49:35 2017 +0100 amd/amdht: Fix format security errors Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat -Wformat-security`, causing errors similar like the one below. ``` CC romstage/northbridge/amd/amdht/ht_wrapper.o src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify': src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security] printk(log_level, event_class_string_decodes[evtClass]); ^ […] ``` Fix that, by explicitly using a format string. TEST=Built and booted on ASUS KGPE-D16. [1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-str… "fprintf, error: format not a string literal and no format arguments [-Werror=format-security" [2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609. Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18208 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18208 for details. -gerrit

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Patch set updated for coreboot: amd/amdht: Fix format security errors
by Paul Menzel 26 Jan '17

26 Jan '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18208 -gerrit commit ae28b9505198160d90b36445c02033af2079c7e6 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Fri Jan 20 14:49:35 2017 +0100 amd/amdht: Fix format security errors Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat -Wformat-security`, causing errors similar like the one below. ``` CC romstage/northbridge/amd/amdht/ht_wrapper.o src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify': src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security] printk(log_level, event_class_string_decodes[evtClass]); ^ […] ``` Fix that, by explicitly using a format string. TEST=Built and booted on ASUS KGPE-D16. [1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-str… "fprintf, error: format not a string literal and no format arguments [-Werror=format-security" [2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609. Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/northbridge/amd/amdht/ht_wrapper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 8a25993..8babb47 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -121,7 +121,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_CLASS_WARNING: case HT_EVENT_CLASS_INFO: log_level = BIOS_DEBUG; - printk(log_level, event_class_string_decodes[evtClass]); + printk(log_level, "%s", event_class_string_decodes[evtClass]); break; default: log_level = BIOS_DEBUG; @@ -135,7 +135,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: case HT_EVENT_COH_FAMILY_FEUD: - printk(log_level, event_string_decode(event)); + printk(log_level, "%s", event_string_decode(event)); break; case HT_EVENT_COH_NODE_DISCOVERED: { @@ -152,11 +152,11 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_NCOH_LINK_EXCEED: case HT_EVENT_NCOH_BUS_MAX_EXCEED: case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(log_level, event_string_decode(event)); + printk(log_level, "%s", event_string_decode(event)); break; case HT_EVENT_NCOH_DEVICE_FAILED: { - printk(log_level, event_string_decode(event)); + printk(log_level, "%s", event_string_decode(event)); sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", evt->node, evt->link, evt->depth, evt->attemptedBUID); @@ -165,7 +165,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) } case HT_EVENT_NCOH_AUTO_DEPTH: { - printk(log_level, event_string_decode(event)); + printk(log_level, "%s", event_string_decode(event)); sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; printk(log_level, ": node %d link %d depth: %d", evt->node, evt->link, evt->depth); @@ -178,7 +178,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_HW_EVENTS: case HT_EVENT_HW_SYNCHFLOOD: case HT_EVENT_HW_HTCRC: - printk(log_level, event_string_decode(event)); + printk(log_level, "%s", event_string_decode(event)); break; default: printk(log_level, "HT_EVENT_UNKNOWN");

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Patch set updated for coreboot: hp/2760p: reserve space in bootblock
by Iru Cai 26 Jan '17

26 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14209 -gerrit commit 8b8704807d8331829fa6039da7f220a70c0df3d6 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Mar 31 23:13:09 2016 +0800 hp/2760p: reserve space in bootblock The space started from 0x7ff700 is reserved for data needed by (maybe) EC. Change-Id: Iae7eb8a67fcce173500d91951ee71a3361475fc9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/hp/2760p/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index 440c1f6..295785f 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -62,4 +62,13 @@ config MAX_CPUS config USBDEBUG_HCD_INDEX int default 1 + +config ID_SECTION_OFFSET + hex + default 0x900 + +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0xa00 + endif

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Patch set updated for coreboot: New port: HP Elitebook 2760p
by Iru Cai 26 Jan '17

26 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18241 -gerrit commit 0cc0cf42fd3a8736e2cb0e68964b2968e2365dc9 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Jan 26 14:51:47 2017 +0800 New port: HP Elitebook 2760p The code is generated by autoport. The flash chip is socketed beside the WLAN slot. The EHCI debug port is on right side of the laptop beside the RJ11 connector. Things that works: - memory: 0+8G (the DIMM under the keyboard) - Linux - native graphics init + SeaBIOS payload with SeaVGABIOS - all 3 USB ports Things that doesn't work: - keyboard (use a USB keyboard instead) - AC and battery status - wacom digitizer - fan control (fan always runs on full speed) Things that is not tested: - WLAN - WWAN - SD card reader - smart card reader - expresscard - cable modem (EC) blobs: This laptop uses SMSC KBC1126-NU as EC. It may need some blobs in the flash chip. - There may be some data needed by EC at 0x7ff700-0x7fff07, which needs to be copied from the factory firmware - The padding before 0x7a0000 in the original UEFI firmware (can be seen with UEFITool) may contain EC firmware (it has strings like `8051 Reset'), so now I set the CBFS size to 0x60000 Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/hp/2760p/Kconfig | 65 +++++ src/mainboard/hp/2760p/Kconfig.name | 2 + src/mainboard/hp/2760p/Makefile.inc | 3 + src/mainboard/hp/2760p/acpi/ec.asl | 7 + src/mainboard/hp/2760p/acpi/platform.asl | 10 + src/mainboard/hp/2760p/acpi/superio.asl | 1 + src/mainboard/hp/2760p/acpi_tables.c | 1 + src/mainboard/hp/2760p/board_info.txt | 6 + src/mainboard/hp/2760p/devicetree.cb | 111 ++++++++ src/mainboard/hp/2760p/dsdt.asl | 30 ++ src/mainboard/hp/2760p/early_southbridge.c | 69 +++++ src/mainboard/hp/2760p/gnvs.c | 19 ++ src/mainboard/hp/2760p/gpio.c | 433 +++++++++++++++++++++++++++++ src/mainboard/hp/2760p/hda_verb.c | 65 +++++ src/mainboard/hp/2760p/mainboard.c | 55 ++++ src/mainboard/hp/2760p/romstage.c | 1 + 16 files changed, 878 insertions(+) diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig new file mode 100644 index 0000000..440c1f6 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig @@ -0,0 +1,65 @@ +if BOARD_HP_2760P + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/2760p + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook 2760p" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x162a + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 +endif diff --git a/src/mainboard/hp/2760p/Kconfig.name b/src/mainboard/hp/2760p/Kconfig.name new file mode 100644 index 0000000..4a6a8e5 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_2760P + bool "HP EliteBook 2760p" diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc new file mode 100644 index 0000000..6064cea --- /dev/null +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/hp/2760p/acpi/ec.asl b/src/mainboard/hp/2760p/acpi/ec.asl new file mode 100644 index 0000000..aea3c58 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 22) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/platform.asl b/src/mainboard/hp/2760p/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/superio.asl b/src/mainboard/hp/2760p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/2760p/acpi_tables.c b/src/mainboard/hp/2760p/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/hp/2760p/board_info.txt b/src/mainboard/hp/2760p/board_info.txt new file mode 100644 index 0000000..ae1ca3b --- /dev/null +++ b/src/mainboard/hp/2760p/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: yes +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb new file mode 100644 index 0000000..95b1bd1 --- /dev/null +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000129" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x007c0281" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x21" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x162a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x162a + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x162a + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x162a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x162a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x162a + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x162a + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x162a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x162a + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x162a + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x162a + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x162a + end + end +end diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl new file mode 100644 index 0000000..3b7fb7e --- /dev/null +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/hp/2760p/early_southbridge.c b/src/mainboard/hp/2760p/early_southbridge.c new file mode 100644 index 0000000..4a454ab --- /dev/null +++ b/src/mainboard/hp/2760p/early_southbridge.c @@ -0,0 +1,69 @@ +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0201); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0101); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00fcfe01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x007c0281); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x82000000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x1ff81feb; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 0, 0, 4 }, + { 0, 0, 5 }, + { 1, 1, 5 }, + { 0, 0, 6 }, + { 1, 1, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/hp/2760p/gnvs.c b/src/mainboard/hp/2760p/gnvs.c new file mode 100644 index 0000000..37cd5c9 --- /dev/null +++ b/src/mainboard/hp/2760p/gnvs.c @@ -0,0 +1,19 @@ +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/2760p/gpio.c b/src/mainboard/hp/2760p/gpio.c new file mode 100644 index 0000000..0d8927d --- /dev/null +++ b/src/mainboard/hp/2760p/gpio.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c new file mode 100644 index 0000000..c60846e --- /dev/null +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -0,0 +1,65 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162a, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c162a), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a70130), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x40f000f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + + 0x00000001, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x1, 0x103c3066), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/2760p/mainboard.c b/src/mainboard/hp/2760p/mainboard.c new file mode 100644 index 0000000..5cf9f60 --- /dev/null +++ b/src/mainboard/hp/2760p/mainboard.c @@ -0,0 +1,55 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; + RCBA32(0x38c0) = 0x00000007; +#if 0 + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } +#endif + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/hp/2760p/romstage.c @@ -0,0 +1 @@ +/* dummy file */

1 0

Patch set updated for coreboot: [RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR
by Iru Cai 26 Jan '17

26 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14208 -gerrit commit 8ee8150a09904f19fffdabbdd415b7b43069f2c0 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Mar 31 15:32:25 2016 +0800 [RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR HP Elitebook 2760p (and some other HP laptops) stores some data which may be used by EC in bootblock region. So some space needs to be reserved before the reset vector. Change-Id: I992d285a1a76883ff7a69445a0ff9efe62dbbd7f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/failover.ld | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6280024..1daddd9 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -181,6 +181,10 @@ config ID_SECTION_OFFSET hex default 0x80 +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0xf0 + # 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index e9613d9..a434704 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -50,8 +50,8 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + ROMLOC_MIN = 0xfffffff0 - CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR + - (_erom - _rom + 16) - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); /* Post-check proper SIPI vector. */ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),

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Patch set updated for coreboot: soc/intel/skylake: Add include path for FSP UPD
by Naresh Solanki 26 Jan '17

26 Jan '17

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18234 -gerrit commit e38e6d13f6f39545eb236ec17060ed3e057adcca Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Jan 25 22:42:24 2017 +0530 soc/intel/skylake: Add include path for FSP UPD FSP binary comes along with FSP UPD header. The header file present in src/vendorcode/intel/fsp/fsp2_0/skykabylake may be not in sync with currently used fsp binary. Hence add include path for FSP UPD header to 3rdparty/blobs/mainboard/$(MAINBOARD)/fsp/ to be considered during build. Change-Id: Iaeae6a845e57a285a0737b0dff7c95bf20f56b12 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 4b6fcfc..743a4f3 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -109,6 +109,8 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD)/fsp/ + ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake

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Patch set updated for coreboot: soc/intel/skylake: Add include path for FSP UPD
by Naresh Solanki 26 Jan '17

26 Jan '17

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18234 -gerrit commit 69b5a9a26821df32b224dfacd3318170ccb56544 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Jan 25 22:42:24 2017 +0530 soc/intel/skylake: Add include path for FSP UPD FSP binary comes along with FSP UPD header. The header file present in src/vendorcode/intel/fsp/fsp2_0/skykabylake may be not in sync with currently used fsp binary. Hence use the config to specify path to FSP UPD header to be considered during build. Change-Id: Iaeae6a845e57a285a0737b0dff7c95bf20f56b12 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 4b6fcfc..743a4f3 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -109,6 +109,8 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD)/fsp/ + ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake

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Patch set updated for coreboot: mainboard/google/snappy: Update WDT touchscreen device
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18240 -gerrit commit 5ad377cd547cd67a6a0274aed79eeb45c6b74a25 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 19:29:06 2017 -0800 mainboard/google/snappy: Update WDT touchscreen device Export PowerResource for WDT touchscreen device. BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Compiles successfully. Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/snappy/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index ecbf156..4c7fe0a 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -189,6 +189,8 @@ chip soc/intel/apollolake register "generic.irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end

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Patch set updated for coreboot: mainboard/google/pryo: Update touchscreen device ACPI nodes
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18239 -gerrit commit bd83d694974e177b7b8b88e9cf027341eb5c81af Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 19:15:49 2017 -0800 mainboard/google/pryo: Update touchscreen device ACPI nodes 1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 193fdd8..4713efe 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -172,6 +172,9 @@ chip soc/intel/apollolake .desc = WCOM_TS_DESC, .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), .probed = 1, + .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), + .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152), + .has_power_resource = 1, }" register "hid_desc_reg_offset" = "0x1" device i2c 0xA on end @@ -181,14 +184,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI
by Furquan Shaikh 26 Jan '17

26 Jan '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18238 -gerrit commit 4e99486174ae12cdcda040b5b8290780c96dce33 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Jan 25 17:53:01 2017 -0800 i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPI Linux kernel expects that power management with ACPI should always be handled using PowerResource. However, some kernel drivers (e.g. ELAN touchscreen) check to see if reset gpio is passed in by the BIOS to decide whether the device loses power in suspend. Thus, until the kernel has a better way for drivers to query if device lost power in suspend, we need to allow passing in of GPIOs via _CRS as well as exporting PowerResource to control power to the device. Update mainboards to export reset GPIO as well as PowerResource for ELAN touchscreen device. BUG=chrome-os-partner:62311,chrome-os-partner:60194 BRANCH=reef TEST=Verified that touchscreen works on power-on as well as after suspend-resume. Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 12 +++++------- src/drivers/i2c/generic/generic.c | 4 ++-- .../google/reef/variants/baseboard/devicetree.cb | 14 +++++--------- src/mainboard/google/reef/variants/snappy/devicetree.cb | 15 +++++---------- src/mainboard/intel/leafhill/devicetree.cb | 14 +++++--------- 5 files changed, 22 insertions(+), 37 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 19c6596..50a372d 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -19,11 +19,6 @@ #include <arch/acpi_device.h> #include <device/i2c.h> -enum power_mgmt_type { - POWER_RESOURCE = 1, - GPIO_EXPORT = 2, -}; - struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ @@ -47,8 +42,11 @@ struct drivers_i2c_generic_config { unsigned device_present_gpio; unsigned device_present_gpio_invert; - /* Power management type. */ - enum power_mgmt_type pwr_mgmt_type; + /* Do we need to export reset and enable GPIOs in _CRS? */ + bool export_gpio_to_crs; + + /* Does the device have a power resource? */ + bool has_power_resource; /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 4cf3e9e..35821dd 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -32,7 +32,7 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) unsigned reset_gpio = config->reset_gpio.pins[0]; unsigned enable_gpio = config->enable_gpio.pins[0]; - if (config->pwr_mgmt_type != POWER_RESOURCE) + if (!config->has_power_resource) return; if (!reset_gpio && !enable_gpio) @@ -72,7 +72,7 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) static bool i2c_generic_add_gpios_to_crs(struct drivers_i2c_generic_config *cfg) { - if (cfg->pwr_mgmt_type == GPIO_EXPORT) + if (cfg->export_gpio_to_crs) return true; return false; diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 7db4f15..c9bbca9 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -177,16 +177,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3 diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index e498533..ecbf156 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -175,16 +175,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -192,7 +188,6 @@ chip soc/intel/apollolake register "generic.desc" = ""WDT Touchscreen"" register "generic.irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "generic.probed" = "1" - register "generic.pwr_mgmt_type" = "GPIO_EXPORT" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 7db4f15..c9bbca9 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -177,16 +177,12 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" - register "pwr_mgmt_type" = "GPIO_EXPORT" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - - chip drivers/generic/gpio_regulator - register "name" = ""vcc33"" - register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enabled_on_boot" = "1" - device generic 0 on end - end - + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "export_gpio_to_crs" = "1" + register "has_power_resource" = "1" device i2c 10 on end end end # - I2C 3

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coreboot-gerrit January 2017