coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Only add etc/ps2-keyboard-spinup when not updating an image
by Arthur Heymans 25 Jan '17

25 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18231 -gerrit commit c525de58753760e4c17dd87d2250993a5fbb6324 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Jan 25 15:21:08 2017 +0100 Only add etc/ps2-keyboard-spinup when not updating an image Without this motherboards that requires a non zero timeout for ps2 keyboards on SeaBIOS don't build when CONFIG_UPDATE_IMAGE is set. This is a workaround, since the proper way to do this would be not to call cbfstool in the Makefile, but to create the raw int file containing the timeout and have this file included in cbfs. This however requires to convert decimal to a little endian representation, for which there exist no simple solution in Makefile. Change-Id: Icafba8d3e279a2e70e607abba81e3dbebfb55e4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 0c6b351..ee3449c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -886,10 +886,12 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$( dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +ifneq ($(CONFIG_UPDATE_IMAGE),y) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif +endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n"

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Patch set updated for coreboot: libpayload/Makefile: include .xcompile before vars using it
by Martin Roth 25 Jan '17

25 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18230 -gerrit commit 22646d8c547d3b01a4214c0856dad6cf243113e7 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 25 09:09:23 2017 -0700 libpayload/Makefile: include .xcompile before vars using it coreinfo was broken because libpayload wasn't building correctly. The change to skip running xcompile on non-compile targets moved the include of .xcompile to below where the variables were getting set. commit 0ffef882: (build system: don't run xcompile or git for %clean/ %config targets") This patch corrects the order of those two pieces. Change-Id: I1550fd24ac7d50356a29847d232855d653093720 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/libpayload/Makefile | 52 ++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 34df485..41df1cc 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -93,32 +93,6 @@ include $(srck)/Makefile include $(HAVE_DOTCONFIG) -ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm -ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips -ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 - -ARCH-y := $(ARCHDIR-y) - -# If architecture folder name is different from xcompile architecture name, -# override here. -ARCH-$(CONFIG_LP_ARCH_ARM) := arm -ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 -ARCH-$(CONFIG_LP_ARCH_MIPS) := mips - -CC := $(CC_$(ARCH-y)) -AS := $(AS_$(ARCH-y)) -LD := $(LD_$(ARCH-y)) -NM := $(NM_$(ARCH-y)) -OBJCOPY := $(OBJCOPY_$(ARCH-y)) -OBJDUMP := $(OBJDUMP_$(ARCH-y)) -READELF := $(READELF_$(ARCH-y)) -STRIP := $(STRIP_$(ARCH-y)) -AR := $(AR_$(ARCH-y)) - -CFLAGS += $(CFLAGS_$(ARCH-y)) - # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists # 2. when make config (in any flavour) is run @@ -156,6 +130,32 @@ HOSTCC:=clang endif endif +ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm +ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 +ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 + +ARCH-y := $(ARCHDIR-y) + +# If architecture folder name is different from xcompile architecture name, +# override here. +ARCH-$(CONFIG_LP_ARCH_ARM) := arm +ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 +ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_MIPS) := mips + +CC := $(CC_$(ARCH-y)) +AS := $(AS_$(ARCH-y)) +LD := $(LD_$(ARCH-y)) +NM := $(NM_$(ARCH-y)) +OBJCOPY := $(OBJCOPY_$(ARCH-y)) +OBJDUMP := $(OBJDUMP_$(ARCH-y)) +READELF := $(READELF_$(ARCH-y)) +STRIP := $(STRIP_$(ARCH-y)) +AR := $(AR_$(ARCH-y)) + +CFLAGS += $(CFLAGS_$(ARCH-y)) + ifeq ($(CONFIG_LP_CCACHE),y) CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH))))) ifeq ($(CCACHE),)

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New patch to review for coreboot: libpayload/Makefile: include .xcompile before vars using it
by Martin Roth 25 Jan '17

25 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18230 -gerrit commit adfd79ceb71bea8f8f81513516705d851d67ea00 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 25 09:09:23 2017 -0700 libpayload/Makefile: include .xcompile before vars using it coreinfo was broken because libpayload wasn't building correctly. The change to skip running xcompile on non-compile targets moved the include of .xcompile to below where the variables were getting set. commit 0ffef882: (build system: don't run xcompile or git for %clean/ %config targets") This patch corrects the order of those two pieces. Change-Id: I1550fd24ac7d50356a29847d232855d653093720 --- payloads/libpayload/Makefile | 52 ++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 34df485..41df1cc 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -93,32 +93,6 @@ include $(srck)/Makefile include $(HAVE_DOTCONFIG) -ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm -ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips -ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 - -ARCH-y := $(ARCHDIR-y) - -# If architecture folder name is different from xcompile architecture name, -# override here. -ARCH-$(CONFIG_LP_ARCH_ARM) := arm -ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 -ARCH-$(CONFIG_LP_ARCH_MIPS) := mips - -CC := $(CC_$(ARCH-y)) -AS := $(AS_$(ARCH-y)) -LD := $(LD_$(ARCH-y)) -NM := $(NM_$(ARCH-y)) -OBJCOPY := $(OBJCOPY_$(ARCH-y)) -OBJDUMP := $(OBJDUMP_$(ARCH-y)) -READELF := $(READELF_$(ARCH-y)) -STRIP := $(STRIP_$(ARCH-y)) -AR := $(AR_$(ARCH-y)) - -CFLAGS += $(CFLAGS_$(ARCH-y)) - # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists # 2. when make config (in any flavour) is run @@ -156,6 +130,32 @@ HOSTCC:=clang endif endif +ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm +ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 +ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 + +ARCH-y := $(ARCHDIR-y) + +# If architecture folder name is different from xcompile architecture name, +# override here. +ARCH-$(CONFIG_LP_ARCH_ARM) := arm +ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 +ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_MIPS) := mips + +CC := $(CC_$(ARCH-y)) +AS := $(AS_$(ARCH-y)) +LD := $(LD_$(ARCH-y)) +NM := $(NM_$(ARCH-y)) +OBJCOPY := $(OBJCOPY_$(ARCH-y)) +OBJDUMP := $(OBJDUMP_$(ARCH-y)) +READELF := $(READELF_$(ARCH-y)) +STRIP := $(STRIP_$(ARCH-y)) +AR := $(AR_$(ARCH-y)) + +CFLAGS += $(CFLAGS_$(ARCH-y)) + ifeq ($(CONFIG_LP_CCACHE),y) CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH))))) ifeq ($(CCACHE),)

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Patch set updated for coreboot: google/pyro: Add USB2 phy setting override
by Kevin Chiu 25 Jan '17

25 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229 -gerrit commit d026d27a33915c28e6944641826ad50f9b012224 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 23:06:23 2017 +0800 google/pyro: Add USB2 phy setting override In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f7551d6..e8bd7fa 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -105,6 +105,22 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" + # Override USB2 PER PORT register (PORT 0) + register "usb2eye[0]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 1, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + + # Override USB2 PER PORT register (PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 2, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF

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Patch set updated for coreboot: google/pyro: Add USB2 phy setting override
by Kevin Chiu 25 Jan '17

25 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229 -gerrit commit 95140614340596153bcaf38bba5a525d0555d35a Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 23:06:23 2017 +0800 google/pyro: Add USB2 phy setting override In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f7551d6..47c5226 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -223,4 +223,20 @@ chip soc/intel/apollolake end device pci 1f.1 on end # - SMBUS end + + # (TYPE C PORT 0) + register "usb2eye[0]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 1, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + + # (TYPE C PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 2, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" end

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Patch merged into coreboot/master: google/pyro: Modify Wacom touchscreen IRQ type to level-triggered
by gerrit＠coreboot.org 25 Jan '17

25 Jan '17

the following patch was just integrated into master: commit 84361b1d37238ea03c4dd41ba54d6a74d52bd5c4 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Tue Jan 24 16:24:30 2017 +0800 google/pyro: Modify Wacom touchscreen IRQ type to level-triggered Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18217 for details. -gerrit

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Patch set updated for coreboot: google/pyro: Add USB2 phy setting override
by Kevin Chiu 25 Jan '17

25 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229 -gerrit commit c3768f0f432bc4de0d19fc68a7b5be179387703b Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 23:06:23 2017 +0800 google/pyro: Add USB2 phy setting override Override USB2 PHY register: port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f7551d6..47c5226 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -223,4 +223,20 @@ chip soc/intel/apollolake end device pci 1f.1 on end # - SMBUS end + + # (TYPE C PORT 0) + register "usb2eye[0]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 1, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + + # (TYPE C PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 2, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" end

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Patch set updated for coreboot: google/pyro: Add USB2 phy setting override
by Kevin Chiu 25 Jan '17

25 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229 -gerrit commit 346cf229b14020c05992856fdb9360afa97a00dc Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 23:06:23 2017 +0800 google/pyro: Add USB2 phy setting override Override USB2 PHY register: port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f7551d6..e61f8ec 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -223,4 +223,20 @@ chip soc/intel/apollolake end device pci 1f.1 on end # - SMBUS end + + # (TYPE C PORT 0) + register "usb2eye[0]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 1, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + + # (TYPE C PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 2, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" end

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New patch to review for coreboot: google/pyro: Add USB2 phy setting override
by Kevin Chiu 25 Jan '17

25 Jan '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18229 -gerrit commit 293c596f92ccc339fc6dd8fd14e10f74d0a38de7 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 23:06:23 2017 +0800 google/pyro: Add USB2 phy setting override Override USB2 PHY register: port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f7551d6..e61f8ec 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -223,4 +223,20 @@ chip soc/intel/apollolake end device pci 1f.1 on end # - SMBUS end + + # (TYPE C PORT 0) + register "usb2eye[0]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 1, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + + # (TYPE C PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 2, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" end

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New patch to review for coreboot: libpayload: fix build
by Patrick Georgi 25 Jan '17

25 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18228 -gerrit commit 344ad4a813e61793ff17df4ffd2e0549aacf11e4 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 25 14:21:12 2017 +0100 libpayload: fix build When .xcompile doesn't already exist, building libpayload fails because the CC variable (et al) remain empty since .xcompile is only included after the variables coming from there are evaluated. Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/Makefile | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 34df485..429bf05 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -107,18 +107,6 @@ ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 ARCH-$(CONFIG_LP_ARCH_MIPS) := mips -CC := $(CC_$(ARCH-y)) -AS := $(AS_$(ARCH-y)) -LD := $(LD_$(ARCH-y)) -NM := $(NM_$(ARCH-y)) -OBJCOPY := $(OBJCOPY_$(ARCH-y)) -OBJDUMP := $(OBJDUMP_$(ARCH-y)) -READELF := $(READELF_$(ARCH-y)) -STRIP := $(STRIP_$(ARCH-y)) -AR := $(AR_$(ARCH-y)) - -CFLAGS += $(CFLAGS_$(ARCH-y)) - # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists # 2. when make config (in any flavour) is run @@ -149,6 +137,18 @@ $(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell $(top)/../../util/xcompil -include .xcompile +CC := $(CC_$(ARCH-y)) +AS := $(AS_$(ARCH-y)) +LD := $(LD_$(ARCH-y)) +NM := $(NM_$(ARCH-y)) +OBJCOPY := $(OBJCOPY_$(ARCH-y)) +OBJDUMP := $(OBJDUMP_$(ARCH-y)) +READELF := $(READELF_$(ARCH-y)) +STRIP := $(STRIP_$(ARCH-y)) +AR := $(AR_$(ARCH-y)) + +CFLAGS += $(CFLAGS_$(ARCH-y)) + ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) CC:=clang -m32 @@ -304,12 +304,12 @@ clean-for-update: doxygen-clean clean-for-update-target clean: clean-for-update clean-target rm -f .ccwrap junit_config junit_config.old + rm -rf $(obj) clean-cscope: rm -f cscope.out -distclean: clean-cscope - rm -rf $(obj) +distclean: clean-cscope clean rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile junit.xml .PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy

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coreboot-gerrit January 2017