coreboot-gerrit January 2017

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Patch set updated for coreboot: SeaBIOS Kconfig: Update logging
by Martin Roth 27 Jan '17

27 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18210 -gerrit commit 225bdb507cf199e746bec074df3ff7364f3f404d Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 23 14:56:55 2017 -0700 SeaBIOS Kconfig: Update logging The SeaBIOS and coreboot log levels don't really align, so setting the SeaBIOS log level to the same as coreboot's isn't really what we want. - Update default log level to use the default SeaBIOS log level. - Update the current help text to match the new defaults. - Add help text for what is displayed at various levels. - Get rid of separate type & prompt lines. - Add comments for default seabios level & logging disabled Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/SeaBIOS/Kconfig | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 276f75d..ae09cd2 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -95,13 +95,32 @@ config PAYLOAD_VGABIOS_FILE default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" config SEABIOS_DEBUG_LEVEL - prompt "SeaBIOS debug level (verbosity)" - default DEFAULT_CONSOLE_LOGLEVEL - int + int "SeaBIOS debug level (verbosity)" + default -1 help - The higher the number, the more verbose SeaBIOS will be. The range is - not well defined but the typical values range from 0 to about 9 inclusive - where 0 disables all output. Set this value to -1 to use SeaBIOS' default. + The higher the number, the more verbose SeaBIOS will be. See the table + below for the current values corresponding to various items as of SeaBIOS + version 1.10.1. Set this value to -1 to use SeaBIOS' default. + + Output at various SeaBIOS log levels: + level 0 - Logging disabled + level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM + level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h + level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts + level 4 - bios tables, more optionrom + level 5 - Extra bootsplash, more XHCI + level 6 - ATA commands, extra optionrom + level 7 - extra ps2 commands, more OHCI & EHCI + level 8 - extra malloc info, more AHCI + level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS, + USB-HID commands, SDcard commands, Floppy commands + level 10 - interrupt 13h (Drives other than floppy) + level 20 - interrupt 10h (Display) + +comment "Using default SeaBIOS log level" + depends on SEABIOS_DEBUG_LEVEL = -1 + +comment "SeaBIOS logging disabled" + depends on SEABIOS_DEBUG_LEVEL = 0 - The default is to use coreboot's loglevel. endif

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Patch merged into coreboot/master: drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos value
by gerrit＠coreboot.org 26 Jan '17

26 Jan '17

the following patch was just integrated into master: commit 0e7a93fa65fcc7949c02ee9ac9a19af7351ee3f0 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 25 11:00:18 2017 -0700 drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos value If cmos is invalid, it doesn't make sense to read the value before finding that out. Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18236 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18236 for details. -gerrit

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New patch to review for coreboot: riscv: Suppress invalid coverity errors
by Martin Roth 26 Jan '17

26 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18247 -gerrit commit e34c69bb2fce96f8ea1dbca5099a3cb4467d70a9 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 26 15:37:10 2017 -0700 riscv: Suppress invalid coverity errors Coverity is detecting 'sp' as a variable which has not been initialized. This is obviously not correct, so this patch *TRIES* to mark it as false I'm not positive that this will work because the annotation needs to go on the line above the error, but this error is inside of a # define. Does the whole #define count as one line? Can it go on the line above the #define in the .h file? Does it have to precede every line where the #define is used? The documentation doesn't make this clear. Should suppress coverity issues: 1368525 & 1368527 uninit_use: Using uninitialized value sp. Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/arch/riscv/include/mcall.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 1e74ed3..cdd9bd3 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -70,6 +70,7 @@ typedef struct { } hls_t; #define MACHINE_STACK_TOP() ({ \ + /* coverity[uninit_use] : FALSE */ \ register uintptr_t sp asm ("sp"); \ (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })

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New patch to review for coreboot: util/nvramtool: Bail out on unaligned multi-byte entries
by Nico Huber 26 Jan '17

26 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18246 -gerrit commit 66d7a0167ea50722ef0fe03914f4710e187cb7fb Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Jan 26 23:22:46 2017 +0100 util/nvramtool: Bail out on unaligned multi-byte entries coreboot doesn't support CMOS options that are not byte aligned but span multiple bytes. So treat them as error. Change-Id: I2bcff62f153932e9c6646b4ce08e8da1c1532947 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/nvramtool/accessors/layout-bin.c | 6 ++++++ util/nvramtool/accessors/layout-text.c | 6 ++++++ util/nvramtool/layout.c | 3 +++ util/nvramtool/layout.h | 1 + 4 files changed, 16 insertions(+) diff --git a/util/nvramtool/accessors/layout-bin.c b/util/nvramtool/accessors/layout-bin.c index 34507c9..fa6344b 100644 --- a/util/nvramtool/accessors/layout-bin.c +++ b/util/nvramtool/accessors/layout-bin.c @@ -481,6 +481,12 @@ static void try_add_cmos_table_entry(cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index bea3b3e..b6cbc2e 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -695,6 +695,12 @@ static void try_add_layout_file_entry(const cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c index 241dd19..6fdb282 100644 --- a/util/nvramtool/layout.c +++ b/util/nvramtool/layout.c @@ -169,6 +169,9 @@ int add_cmos_entry(const cmos_entry_t * e, const cmos_entry_t ** conflict) if (e->length < 1) return LAYOUT_ENTRY_BAD_LENGTH; + if (e->bit % 8 && e->bit / 8 != (e->bit + e->length - 1) / 8) + return LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED; + if ((new_entry = (cmos_entry_item_t *) malloc(sizeof(*new_entry))) == NULL) out_of_memory(); diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index 8a39ab9..bde0603 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -40,6 +40,7 @@ #define LAYOUT_CHECKSUM_OVERLAPS_SUMMED_AREA (LAYOUT_RESULT_START + 7) #define LAYOUT_SUMMED_AREA_OUT_OF_RANGE (LAYOUT_RESULT_START + 8) #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) +#define LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED (LAYOUT_RESULT_START + 10) typedef enum { CMOS_ENTRY_ENUM = 'e',

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Patch set updated for coreboot: Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented
by Arthur Heymans 26 Jan '17

26 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18232 -gerrit commit 8b40113e4f037ff39dd966968dfd466fce666fed Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Jan 25 15:27:52 2017 +0100 Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented This also selects it by default on Haswell. This also removes the if RELOCATABLE_RAMSTAGE line since that is selected in the very same file. Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/Kconfig | 2 +- src/northbridge/intel/haswell/Kconfig | 1 + src/soc/intel/apollolake/Kconfig | 2 +- src/soc/intel/broadwell/Kconfig | 2 +- src/soc/intel/skylake/Kconfig | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 436964c..581c36b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -244,7 +244,7 @@ config RELOCATABLE_RAMSTAGE config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM depends on RELOCATABLE_RAMSTAGE - bool "Cache the relocated ramstage outside of cbmem." + bool default n help The relocated ramstage is saved in an area specified by the diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 4fc117d..51122f0 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_HASWELL select INTEL_DDI select INTEL_DP select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b37cde6..b4d909d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,7 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 01bcaf1..f17681b 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24c2e30..db6011e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -17,7 +17,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select COMMON_FADT

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Patch merged into coreboot/master: google/pyro: Add USB2 phy setting override
by gerrit＠coreboot.org 26 Jan '17

26 Jan '17

the following patch was just integrated into master: commit 011792415963e19dfe84da25cd3ab1f31bd55b34 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 23:06:23 2017 +0800 google/pyro: Add USB2 phy setting override In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18229 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18229 for details. -gerrit

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Patch merged into coreboot/master: google/pyro: Disable Wacom touchscreen probed
by gerrit＠coreboot.org 26 Jan '17

26 Jan '17

the following patch was just integrated into master: commit fe8a01b01aea9aaeae67e5d03c699eedc1fc611f Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Jan 25 16:20:26 2017 +0800 google/pyro: Disable Wacom touchscreen probed Wacom touchscreen is i2c hid device and it's the device that always exists. So no need to set "probed" property for it. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18227 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18227 for details. -gerrit

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New patch to review for coreboot: Makefile: Just error out if no .config exists
by Martin Roth 26 Jan '17

26 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18245 -gerrit commit 7caa691b49bc5d0e9146bcdba606478b55de6f11 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 26 10:51:43 2017 -0700 Makefile: Just error out if no .config exists Currently coreboot runs the 'config' command if no .config file exists. This isn't what anyone wants, and is particularly frustrating for tools that automate the build, where the build just hangs waiting for input. Instead, just show an error message and then exit the build. Change-Id: If9e0c2c26f8273814518589a2f94c5b00fc4cefe Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 2c87feb..2973030 100644 --- a/Makefile +++ b/Makefile @@ -123,8 +123,11 @@ endif ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc include $(TOPLEVEL)/payloads/Makefile.inc -real-all: config - +real-all: + @echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2 + @echo "Please specify a config file or run 'make menuconfig' to" >&2 + @echo "generate a new config file." >&2 + @exit 1 else include $(DOTCONFIG)

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New patch to review for coreboot: payloads/external: iPXE: Fix build on 32bit.
by Denis 'GNUtoo' Carikli 26 Jan '17

26 Jan '17

Denis 'GNUtoo' Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18244 -gerrit commit 0ffefa1ad96241fc590daffec0099c6c2468c625 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jan 11 21:56:34 2017 +0100 payloads/external: iPXE: Fix build on 32bit. Without that fix, when bugilding iPXE we have: [BUILD] bin/librm.o arch/x86/transitions/librm.S: Assembler messages: arch/x86/transitions/librm.S:1509: Warning: shift count out of range (32 is not between 0 and 31) arch/x86/transitions/librm.S:1511: Warning: .space repeat count is zero, ignored {standard input}: Error: 2 warnings, treating warnings as errors [...] payloads/external/iPXE/ipxe/ipxe.rom] Error 2 Change-Id: I0aed7d4b823dfdf447a54a42ad23185fee120122 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- payloads/external/iPXE/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index f45edfd..2e1e3da 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -57,7 +57,7 @@ endif build: config echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom NO_WERROR=1 cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h"

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Patch set updated for coreboot: SeaBIOS Kconfig: Update logging
by Martin Roth 26 Jan '17

26 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18210 -gerrit commit 6c3cbda90f0253daa04022ea0c830ce7301258c8 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 23 14:56:55 2017 -0700 SeaBIOS Kconfig: Update logging The SeaBIOS and coreboot log levels don't really align, so setting the SeaBIOS log level to the same as coreboot's isn't really what we want. Below log level 5, coreboot logs very little, so set the SeaBIOS log level to 0, then increase the default log slowly level from there. - Update default log levels. - Update the current help text to match the new defaults. - Add help text for what is displayed at various levels. - Get rid of separate type & prompt lines. Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/SeaBIOS/Kconfig | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 276f75d..ad3f5c3 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -95,13 +95,32 @@ config PAYLOAD_VGABIOS_FILE default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" config SEABIOS_DEBUG_LEVEL - prompt "SeaBIOS debug level (verbosity)" - default DEFAULT_CONSOLE_LOGLEVEL - int + int "SeaBIOS debug level (verbosity)" + default 2 if DEFAULT_CONSOLE_LOGLEVEL_8 || DEFAULT_CONSOLE_LOGLEVEL_7 + default 1 if DEFAULT_CONSOLE_LOGLEVEL_6 || DEFAULT_CONSOLE_LOGLEVEL_5 + default 0 help - The higher the number, the more verbose SeaBIOS will be. The range is - not well defined but the typical values range from 0 to about 9 inclusive - where 0 disables all output. Set this value to -1 to use SeaBIOS' default. + The higher the number, the more verbose SeaBIOS will be. See the table + below for the current values corresponding to various items as of SeaBIOS + version 1.10.1. Set this value to -1 to use SeaBIOS' default. + + Defaults to no output for coreboot log levels 4 (Warning) and below + Defaults to Basic output (1) for coreboot log levels 5 (Notice) & 6 (Info) + Defaults to SeaBIOS log level 2 for coreboot levels 7 (Debug) & 8 (Spew) + + Output at various SeaBIOS log levels: + level 0 - Logging disabled + level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM + level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h + level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts + level 4 - bios tables, more optionrom + level 5 - Extra bootsplash, more XHCI + level 6 - ATA commands, extra optionrom + level 7 - extra ps2 commands, more OHCI & EHCI + level 8 - extra malloc info, more AHCI + level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS, + USB-HID commands, SDcard commands, Floppy commands + level 10 - interrupt 13h (Drives other than floppy) + level 20 - interrupt 10h (Display) - The default is to use coreboot's loglevel. endif

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coreboot-gerrit January 2017