coreboot-gerrit January 2017

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Patch set updated for coreboot: mb/google/poppy:[WIP] Add OV camera
by Rizwan Qureshi 27 Jan '17

27 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18081 -gerrit commit 3efd9d27c9acfbaf6df44b2515cb8db7b33c5f6e Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jan 10 08:42:07 2017 +0530 mb/google/poppy:[WIP] Add OV camera Add OV camera support to poppy Change-Id: I5d8a1eb775029e949aeb3de26d8bae10a9d531b8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 2 + src/mainboard/google/poppy/devicetree.cb | 123 ++++++++++++++++++++++++++++++- 2 files changed, 124 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 262166c..bd98e83 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SKYLAKE + select DRIVERS_I2C_TPS68470 + select DRIVERS_I2C_OVXXXX config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 4283a34..81d28f7 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -196,7 +196,75 @@ chip soc/intel/skylake device pci 14.2 on end # Thermal Subsystem device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.2 on + chip drivers/i2c/tps68470 + # PMIC CLDB Buffer + register "cldb_buf" = "{ \ + 0x00, 0x02, 0x00, 0x50,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00\ + }" + device i2c 48 on end + end + chip drivers/i2c/ovXXXX + register "acpi_hid" = ""OVTID850"" + register "acpi_name" = ""CAM0"" + register "acpi_uid" = "0" + register "vcm_addr" = "0xc" + register "eeprom0_addr" = "0x50" + + # Camera SSDB Buffer + register "buf.ssdb.version" = "0x00" + register "buf.ssdb.sensor_card_sku" = "0x50" + + register "buf.ssdb.csi2_data_stream_interface" = "{ \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + }" + + register "buf.ssdb.bdf_value" = "0x00" + register "buf.ssdb.dphy_link_en_fuses" = "0x00" + register "buf.ssdb.lanes_clock_division" = "0x00" + register "buf.ssdb.link_used" = "0x00" + register "buf.ssdb.lanes_used" = "0x04" + register "buf.ssdb.csi_rx_dly_cnt_termen_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane3" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane3" = "0x00" + register "buf.ssdb.max_lane_speed" = "0x00" + register "buf.ssdb.sensor_calibration_file_index" = "0x00" + register "buf.ssdb.sensor_calibration_file_index_mbz" = "{0x00, 0x00, 0x00}" + register "buf.ssdb.rom_type" = "0x08" + register "buf.ssdb.vcm_type" = "0x03" + register "buf.ssdb.platform" = "0x09" + register "buf.ssdb.platform_sub" = "0x00" + register "buf.ssdb.flash_support" = "0x02" + register "buf.ssdb.privacy_led" = "0x01" + register "buf.ssdb.degree" = "0x00" + register "buf.ssdb.mipi_define" = "0x01" + register "buf.ssdb.mclk" = "0x016E3600" + register "buf.ssdb.control_logic_id" = "0x00" + register "buf.ssdb.mipi_data_format" = "0x00" + register "buf.ssdb.silicon_version" = "0x00" + register "buf.ssdb.customer_id" = "0x00" + + device i2c 20 on end + end + + end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -205,6 +273,59 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 + chip drivers/i2c/ovXXXX + register "acpi_hid" = ""INT3479"" + register "acpi_name" = ""CAM1"" + register "acpi_uid" = "0" + register "vcm_addr" = "0xc" + register "eeprom0_addr" = "0x50" + + # Camera SSDB Buffer + register "buf.ssdb.version" = "0x00" + register "buf.ssdb.sensor_card_sku" = "0x50" + + register "buf.ssdb.csi2_data_stream_interface" = "{ \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + }" + + register "buf.ssdb.bdf_value" = "0x00" + register "buf.ssdb.dphy_link_en_fuses" = "0x00" + register "buf.ssdb.lanes_clock_division" = "0x00" + register "buf.ssdb.link_used" = "0x01" + register "buf.ssdb.lanes_used" = "0x02" + register "buf.ssdb.csi_rx_dly_cnt_termen_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane3" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane3" = "0x00" + register "buf.ssdb.max_lane_speed" = "0x00" + register "buf.ssdb.sensor_calibration_file_index" = "0x00" + register "buf.ssdb.sensor_calibration_file_index_mbz" = "{0x00, 0x00, 0x00}" + register "buf.ssdb.rom_type" = "0x08" + register "buf.ssdb.vcm_type" = "0x03" + register "buf.ssdb.platform" = "0x09" + register "buf.ssdb.platform_sub" = "0x00" + register "buf.ssdb.flash_support" = "0x02" + register "buf.ssdb.privacy_led" = "0x01" + register "buf.ssdb.degree" = "0x00" + register "buf.ssdb.mipi_define" = "0x01" + register "buf.ssdb.mclk" = "0x016E3600" + register "buf.ssdb.control_logic_id" = "0x00" + register "buf.ssdb.mipi_data_format" = "0x00" + register "buf.ssdb.silicon_version" = "0x00" + register "buf.ssdb.customer_id" = "0x00" + + device i2c 6c on end + end + device pci 19.1 on end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on

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Patch set updated for coreboot: mb/google/poppy:[WIP] Add OV camera
by Rizwan Qureshi 27 Jan '17

27 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18081 -gerrit commit 9fd5d739b14d1333702aa5117203c5d8c8340e1f Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jan 10 08:42:07 2017 +0530 mb/google/poppy:[WIP] Add OV camera Add OV camera support to poppy Change-Id: I5d8a1eb775029e949aeb3de26d8bae10a9d531b8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 2 + src/mainboard/google/poppy/devicetree.cb | 123 ++++++++++++++++++++++++++++++- 2 files changed, 124 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 262166c..bd98e83 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SKYLAKE + select DRIVERS_I2C_TPS68470 + select DRIVERS_I2C_OVXXXX config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 4283a34..be9faa5 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -196,7 +196,75 @@ chip soc/intel/skylake device pci 14.2 on end # Thermal Subsystem device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.2 on + chip drivers/i2c/tps68470 + # PMIC CLDB Buffer + register "cldb_buf" = "{ \ + 0x00, 0x02, 0x00, 0x50,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00\ + }" + device i2c 48 on end + end + chip drivers/i2c/ovXXXX + register "acpi_hid" = ""OVTID850"" + register "acpi_name" = ""CAM0"" + register "acpi_uid" = "0" + register "vcm_addr" = "0xc" + register "eeprom0_addr" = "0x50" + + # Camera SSDB Buffer + register "buf.ssdb.version" = "0x00" + register "buf.ssdb.sensor_card_sku" = "0x50" + + register "buf.ssdb.csi2_data_stream_interface" = "{ \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + }" + + register "buf.ssdb.bdf_value" = "0x00" + register "buf.ssdb.dphy_link_en_fuses" = "0x00" + register "buf.ssdb.lanes_clock_division" = "0x00" + register "buf.ssdb.link_used" = "0x00" + register "buf.ssdb.lanes_used" = "0x04" + register "buf.ssdb.csi_rx_dly_cnt_termen_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane3" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane3" = "0x00" + register "buf.ssdb.max_lane_speed" = "0x00" + register "buf.ssdb.sensor_calibration_file_index" = "0x00" + register "buf.ssdb.sensor_calibration_file_index_mbz" = "{0x00, 0x00, 0x00}" + register "buf.ssdb.rom_type" = "0x08" + register "buf.ssdb.vcm_type" = "0x03" + register "buf.ssdb.platform" = "0x09" + register "buf.ssdb.platform_sub" = "0x00" + register "buf.ssdb.flash_support" = "0x02" + register "buf.ssdb.privacy_led" = "0x01" + register "buf.ssdb.degree" = "0x00" + register "buf.ssdb.mipi_define" = "0x01" + register "buf.ssdb.mclk" = "0x016E3600" + register "buf.ssdb.control_logic_id" = "0x00" + register "buf.ssdb.mipi_data_format" = "0x00" + register "buf.ssdb.silicon_version" = "0x00" + register "buf.ssdb.customer_id" = "0x00" + + device i2c 20 on end + end + + end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -205,6 +273,59 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 + chip drivers/i2c/ovXXXX + register "acpi_hid" = ""INT3479"" + register "acpi_name" = ""CAM1"" + register "acpi_uid" = "0" + register "vcm_addr" = "0xc" + register "eeprom0_addr" = "0x50" + + # Camera SSDB Buffer + register "buf.ssdb.version" = "0x00" + register "buf.ssdb.sensor_card_sku" = "0x50" + + register "buf.ssdb.csi2_data_stream_interface" = "{ \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + }" + + register "buf.ssdb.bdf_value" = "0x00" + register "buf.ssdb.dphy_link_en_fuses" = "0x00" + register "buf.ssdb.lanes_clock_division" = "0x00" + register "buf.ssdb.link_used" = "0x01" + register "buf.ssdb.lanes_used" = "0x02" + register "buf.ssdb.csi_rx_dly_cnt_termen_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane3" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane3" = "0x00" + register "buf.ssdb.max_lane_speed" = "0x00" + register "buf.ssdb.sensor_calibration_file_index" = "0x00" + register "buf.ssdb.sensor_calibration_file_index_mbz" = "{0x00, 0x00, 0x00}" + register "buf.ssdb.rom_type" = "0x08" + register "buf.ssdb.vcm_type" = "0x03" + register "buf.ssdb.platform" = "0x09" + register "buf.ssdb.platform_sub" = "0x00" + register "buf.ssdb.flash_support" = "0x02" + register "buf.ssdb.privacy_led" = "0x01" + register "buf.ssdb.degree" = "0x00" + register "buf.ssdb.mipi_define" = "0x01" + register "buf.ssdb.mclk" = "0x016E3600" + register "buf.ssdb.control_logic_id" = "0x00" + register "buf.ssdb.mipi_data_format" = "0x00" + register "buf.ssdb.silicon_version" = "0x00" + register "buf.ssdb.customer_id" = "0x00" + + device i2c 6c on end + end + device pci 19.1 on end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on

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New patch to review for coreboot: drivers/i2c/ovXXXX:[WIP] Add generic i2c driver for OV cameras
by Rizwan Qureshi 27 Jan '17

27 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18066 -gerrit commit 00da8147898b3f0d56615b7d61afc4e068aab200 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Jan 9 22:58:04 2017 +0530 drivers/i2c/ovXXXX:[WIP] Add generic i2c driver for OV cameras Add generic i2c driver for OV cameras Change-Id: I64afc42b898c866f81ed00bbca99e191f7d48c5a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/i2c/ovXXXX/Kconfig | 2 + src/drivers/i2c/ovXXXX/Makefile.inc | 1 + src/drivers/i2c/ovXXXX/chip.h | 55 ++++++++++++++++++ src/drivers/i2c/ovXXXX/ovXXXX.c | 112 ++++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+) diff --git a/src/drivers/i2c/ovXXXX/Kconfig b/src/drivers/i2c/ovXXXX/Kconfig new file mode 100644 index 0000000..a853428 --- /dev/null +++ b/src/drivers/i2c/ovXXXX/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_OVXXXX + bool diff --git a/src/drivers/i2c/ovXXXX/Makefile.inc b/src/drivers/i2c/ovXXXX/Makefile.inc new file mode 100644 index 0000000..70e2d16 --- /dev/null +++ b/src/drivers/i2c/ovXXXX/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_OVXXXX) += ovXXXX.c diff --git a/src/drivers/i2c/ovXXXX/chip.h b/src/drivers/i2c/ovXXXX/chip.h new file mode 100644 index 0000000..ec86bca --- /dev/null +++ b/src/drivers/i2c/ovXXXX/chip.h @@ -0,0 +1,55 @@ +#include <arch/acpi_device.h> + +#define MAX_SSDB_BUF 94 + +typedef union { + uint8_t ssdb_arr[MAX_SSDB_BUF]; + struct { + uint8_t version; + uint8_t sensor_card_sku; + uint8_t csi2_data_stream_interface[16]; + uint16_t bdf_value; + uint32_t dphy_link_en_fuses; + uint32_t lanes_clock_division; + uint8_t link_used; + uint8_t lanes_used; + uint32_t csi_rx_dly_cnt_termen_clane; + uint32_t csi_rx_dly_cnt_settle_clane; + uint32_t csi_rx_dly_cnt_termen_dlane0; + uint32_t csi_rx_dly_cnt_settle_dlane0; + uint32_t csi_rx_dly_cnt_termen_dlane1; + uint32_t csi_rx_dly_cnt_settle_dlane1; + uint32_t csi_rx_dly_cnt_termen_dlane2; + uint32_t csi_rx_dly_cnt_settle_dlane2; + uint32_t csi_rx_dly_cnt_termen_dlane3; + uint32_t csi_rx_dly_cnt_settle_dlane3; + uint32_t max_lane_speed; + uint8_t sensor_calibration_file_index; + uint8_t sensor_calibration_file_index_mbz[3]; + uint8_t rom_type; + uint8_t vcm_type; + uint8_t platform; + uint8_t platform_sub; + uint8_t flash_support; + uint8_t privacy_led; + uint8_t degree; /* Camera module rotation */ + uint8_t mipi_define; + uint32_t mclk; + uint8_t control_logic_id; + uint8_t mipi_data_format; + uint8_t silicon_version; + uint8_t customer_id; + }ssdb; +}__attribute__((packed))ovXXXX_ssdb; + +struct drivers_i2c_ovXXXX_config { + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + ovXXXX_ssdb buf; + uint8_t vcm_addr; + uint8_t eeprom0_addr; + const char acpi_hid[8]; + const char acpi_name[5]; + uint64_t acpi_uid; +}; diff --git a/src/drivers/i2c/ovXXXX/ovXXXX.c b/src/drivers/i2c/ovXXXX/ovXXXX.c new file mode 100644 index 0000000..cf9c6fb --- /dev/null +++ b/src/drivers/i2c/ovXXXX/ovXXXX.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static void ovXXXX_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_ovXXXX_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_i2c i2c_vcm = { + .address = config->vcm_addr, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->acpi_hid); + acpigen_write_name_integer("_UID", config->acpi_uid); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ +// acpigen_write_method("_CRS", 0) + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_i2c(&i2c_vcm); +/* + int i; + for (i = 0; i < 4; i++) { + struct acpi_i2c i2c_eeprom = { + .address = config->eeprom0_addr + i, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + acpi_device_write_i2c(&i2c_eeprom); + } +*/ + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + acpigen_write_method_serialized("SSDB",0); + acpigen_write_return_byte_buffer((uint8_t *)&config->buf, + MAX_SSDB_BUF); + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + +} + +static const char *ovXXXX_acpi_name(struct device *dev) +{ + struct drivers_i2c_ovXXXX_config *config = dev->chip_info; + return config->acpi_name; +} +#endif + +static struct device_operations ovXXXX_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &ovXXXX_acpi_name, + .acpi_fill_ssdt_generator = &ovXXXX_fill_ssdt, +#endif +}; + +static void ovXXXX_enable(struct device *dev) +{ + dev->ops = &ovXXXX_ops; +} + +struct chip_operations drivers_i2c_ovXXXX_ops = { + CHIP_NAME("OV CAMERA") + .enable_dev = &ovXXXX_enable +};

1 0

New patch to review for coreboot: drivers/i2c/tps68470:[WIP] Add TPS68470 PMIC SSDT generator
by Rizwan Qureshi 27 Jan '17

27 Jan '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18063 -gerrit commit cc4c8d5a1dc846b269ac33f21dffded50923e25d Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Jan 9 19:00:06 2017 +0530 drivers/i2c/tps68470:[WIP] Add TPS68470 PMIC SSDT generator Add TPS68470 PMIC SSDT generator Change-Id: Iaa1dba094a7f791d5b624e545b03b510a4306337 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/i2c/tps68470/Kconfig | 2 + src/drivers/i2c/tps68470/Makefile.inc | 1 + src/drivers/i2c/tps68470/chip.h | 11 ++++ src/drivers/i2c/tps68470/tps68470.c | 95 +++++++++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+) diff --git a/src/drivers/i2c/tps68470/Kconfig b/src/drivers/i2c/tps68470/Kconfig new file mode 100644 index 0000000..75d81dc --- /dev/null +++ b/src/drivers/i2c/tps68470/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_TPS68470 + bool diff --git a/src/drivers/i2c/tps68470/Makefile.inc b/src/drivers/i2c/tps68470/Makefile.inc new file mode 100644 index 0000000..3fa4412 --- /dev/null +++ b/src/drivers/i2c/tps68470/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_TPS68470) += tps68470.c diff --git a/src/drivers/i2c/tps68470/chip.h b/src/drivers/i2c/tps68470/chip.h new file mode 100644 index 0000000..5b511d2 --- /dev/null +++ b/src/drivers/i2c/tps68470/chip.h @@ -0,0 +1,11 @@ +#include <arch/acpi_device.h> + +#define TPS68470_MAX_CLDB_BUF 32 + +struct drivers_i2c_tps68470_config { + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + + uint8_t cldb_buf[TPS68470_MAX_CLDB_BUF]; +}; diff --git a/src/drivers/i2c/tps68470/tps68470.c b/src/drivers/i2c/tps68470/tps68470.c new file mode 100644 index 0000000..1c0eab3 --- /dev/null +++ b/src/drivers/i2c/tps68470/tps68470.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define TPS68470_ACPI_NAME "PMIC" + +static void tps68470_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_tps68470_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + //struct acpi_dp *dp = NULL; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", "INT3472"); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + acpigen_write_method_serialized("CLDB",0); + acpigen_write_return_byte_buffer(config->cldb_buf, + TPS68470_MAX_CLDB_BUF); + + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + +} + +static const char *tps68470_acpi_name(struct device *dev) +{ + return TPS68470_ACPI_NAME; +} +#endif + +static struct device_operations tps68470_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &tps68470_acpi_name, + .acpi_fill_ssdt_generator = &tps68470_fill_ssdt, +#endif +}; + +static void tps68470_enable(struct device *dev) +{ + dev->ops = &tps68470_ops; +} + +struct chip_operations drivers_i2c_tps68470_ops = { + CHIP_NAME("TPS 68470 PMIC") + .enable_dev = &tps68470_enable +};

1 0

New patch to review for coreboot: google/jecht: Fix LED for guado/rikku variants
by Matt DeVillier 27 Jan '17

27 Jan '17

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18249 -gerrit commit 7b8dd5275f8fd7e39cfd78518370ceb075fe1dda Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Jan 26 10:58:15 2017 -0600 google/jecht: Fix LED for guado/rikku variants When guado/rikku/tidus were rolled into jecht, an error was made in set_power_led() as guado/rikku set the polarity differently than tidus. Fix the power LED for guado/rikku by setting the polarity correctly. Test: boot guado/rikku and observe proper function of power LED under S0, S3, and S5 power states. Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/jecht/led.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 50cf32e..286b65e 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -19,10 +19,18 @@ void set_power_led(int state) { + int polarity; + + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) { + polarity = state == LED_OFF ? 0x00 : 0x01; + } else { + polarity = state == LED_BLINK ? 0x01 : 0x00; + } + it8772f_gpio_led(IT8772F_GPIO_DEV, 1, /* set */ 0x01, /* select */ - state == LED_OFF ? 0x00 : 0x01, /* polarity */ + polarity, /* polarity */ state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ 0x01, /* output */ state == LED_BLINK ? 0x00 : 0x01, /* I/O function */

1 0

Patch set updated for coreboot: Add Baytrail ChromeOS devices using variant scheme
by Matt DeVillier 27 Jan '17

27 Jan '17

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18164 -gerrit commit 11755374b606bae0045c749aad68ac58d1f0bf17 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jan 16 17:32:38 2017 -0600 Add Baytrail ChromeOS devices using variant scheme Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty, heli, kip, orco, quawks, squawks, sumo, swanky, and winky using their common reference board (rambi) as a base. Chromium sources used: firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...] firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...] firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...] firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...] firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...] firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...] firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*] firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.] firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data] firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data] firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...] firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table] firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...] The same basic cleanup/changes are made here as with the initial BYT variant commit: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) - Micron 2GB SPD file for kip with updated values renamed to distinguish from same file used by other boards Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/rambi/Kconfig | 52 +++++ src/mainboard/google/rambi/Kconfig.name | 52 +++++ src/mainboard/google/rambi/Makefile.inc | 1 + .../google/rambi/acpi/touchscreen_elan.asl | 53 +++++ .../google/rambi/acpi/touchscreen_wdt.asl | 53 +++++ src/mainboard/google/rambi/mainboard.c | 2 +- src/mainboard/google/rambi/romstage.c | 8 +- .../spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex | 32 +++ .../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 ++ .../rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex | 32 +++ .../rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex | 32 +++ .../spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex | 16 ++ src/mainboard/google/rambi/spd/empty.spd.hex | 16 ++ .../spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex | 16 ++ .../micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex | 32 +++ .../spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex | 17 ++ .../google/rambi/variants/banjo/Makefile.inc | 45 ++++ .../google/rambi/variants/banjo/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/banjo/gpio.c | 229 ++++++++++++++++++++ .../variants/banjo/include/variant/acpi/dptf.asl | 41 ++++ .../banjo/include/variant/acpi/mainboard.asl | 17 ++ .../rambi/variants/banjo/include/variant/onboard.h | 33 +++ .../rambi/variants/banjo/include/variant/variant.h | 35 ++++ .../google/rambi/variants/candy/Makefile.inc | 58 ++++++ .../google/rambi/variants/candy/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/candy/gpio.c | 229 ++++++++++++++++++++ .../variants/candy/include/variant/acpi/dptf.asl | 41 ++++ .../candy/include/variant/acpi/mainboard.asl | 19 ++ .../rambi/variants/candy/include/variant/onboard.h | 39 ++++ .../rambi/variants/candy/include/variant/variant.h | 42 ++++ .../google/rambi/variants/clapper/Makefile.inc | 45 ++++ .../google/rambi/variants/clapper/devicetree.cb | 89 ++++++++ src/mainboard/google/rambi/variants/clapper/gpio.c | 230 ++++++++++++++++++++ .../variants/clapper/include/variant/acpi/dptf.asl | 29 +++ .../clapper/include/variant/acpi/mainboard.asl | 19 ++ .../variants/clapper/include/variant/onboard.h | 39 ++++ .../variants/clapper/include/variant/variant.h | 35 ++++ .../enguarde/include/variant/acpi/mainboard.asl | 2 - .../variants/enguarde/include/variant/onboard.h | 2 - .../google/rambi/variants/glimmer/Makefile.inc | 55 +++++ .../google/rambi/variants/glimmer/devicetree.cb | 98 +++++++++ src/mainboard/google/rambi/variants/glimmer/gpio.c | 231 +++++++++++++++++++++ .../variants/glimmer/include/variant/acpi/dptf.asl | 42 ++++ .../glimmer/include/variant/acpi/mainboard.asl | 19 ++ .../variants/glimmer/include/variant/onboard.h | 39 ++++ .../variants/glimmer/include/variant/variant.h | 42 ++++ .../google/rambi/variants/gnawty/Makefile.inc | 49 +++++ .../google/rambi/variants/gnawty/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/gnawty/gpio.c | 229 ++++++++++++++++++++ .../variants/gnawty/include/variant/acpi/dptf.asl | 41 ++++ .../gnawty/include/variant/acpi/mainboard.asl | 16 ++ .../variants/gnawty/include/variant/onboard.h | 39 ++++ .../variants/gnawty/include/variant/variant.h | 37 ++++ .../google/rambi/variants/heli/Makefile.inc | 55 +++++ .../google/rambi/variants/heli/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/heli/gpio.c | 228 ++++++++++++++++++++ .../variants/heli/include/variant/acpi/dptf.asl | 41 ++++ .../heli/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/heli/include/variant/onboard.h | 33 +++ .../rambi/variants/heli/include/variant/variant.h | 36 ++++ .../google/rambi/variants/kip/Makefile.inc | 49 +++++ .../google/rambi/variants/kip/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/kip/gpio.c | 230 ++++++++++++++++++++ .../variants/kip/include/variant/acpi/dptf.asl | 41 ++++ .../kip/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/kip/include/variant/onboard.h | 34 +++ .../rambi/variants/kip/include/variant/variant.h | 37 ++++ .../google/rambi/variants/orco/Makefile.inc | 49 +++++ .../google/rambi/variants/orco/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/orco/gpio.c | 229 ++++++++++++++++++++ .../variants/orco/include/variant/acpi/dptf.asl | 42 ++++ .../orco/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/orco/include/variant/onboard.h | 33 +++ .../rambi/variants/orco/include/variant/variant.h | 37 ++++ .../google/rambi/variants/quawks/Makefile.inc | 49 +++++ .../google/rambi/variants/quawks/devicetree.cb | 98 +++++++++ src/mainboard/google/rambi/variants/quawks/gpio.c | 230 ++++++++++++++++++++ .../variants/quawks/include/variant/acpi/dptf.asl | 41 ++++ .../quawks/include/variant/acpi/mainboard.asl | 16 ++ .../variants/quawks/include/variant/onboard.h | 34 +++ .../variants/quawks/include/variant/variant.h | 37 ++++ .../google/rambi/variants/squawks/Makefile.inc | 49 +++++ .../google/rambi/variants/squawks/devicetree.cb | 98 +++++++++ src/mainboard/google/rambi/variants/squawks/gpio.c | 230 ++++++++++++++++++++ .../variants/squawks/include/variant/acpi/dptf.asl | 41 ++++ .../squawks/include/variant/acpi/mainboard.asl | 16 ++ .../variants/squawks/include/variant/onboard.h | 34 +++ .../variants/squawks/include/variant/variant.h | 37 ++++ .../google/rambi/variants/sumo/Makefile.inc | 49 +++++ .../google/rambi/variants/sumo/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/sumo/gpio.c | 228 ++++++++++++++++++++ .../variants/sumo/include/variant/acpi/dptf.asl | 42 ++++ .../sumo/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/sumo/include/variant/onboard.h | 47 +++++ .../rambi/variants/sumo/include/variant/variant.h | 37 ++++ src/mainboard/google/rambi/variants/sumo/lan.c | 191 +++++++++++++++++ .../google/rambi/variants/swanky/Makefile.inc | 41 ++++ .../google/rambi/variants/swanky/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/swanky/gpio.c | 229 ++++++++++++++++++++ .../variants/swanky/include/variant/acpi/dptf.asl | 41 ++++ .../swanky/include/variant/acpi/mainboard.asl | 16 ++ .../variants/swanky/include/variant/onboard.h | 33 +++ .../variants/swanky/include/variant/variant.h | 33 +++ .../google/rambi/variants/winky/Makefile.inc | 45 ++++ .../google/rambi/variants/winky/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/winky/gpio.c | 228 ++++++++++++++++++++ .../variants/winky/include/variant/acpi/dptf.asl | 42 ++++ .../winky/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/winky/include/variant/onboard.h | 34 +++ .../rambi/variants/winky/include/variant/variant.h | 35 ++++ 111 files changed, 7259 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index a2bdc43..128e609 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -26,28 +26,80 @@ config MAINBOARD_DIR config VARIANT_DIR string + default "banjo" if BOARD_GOOGLE_BANJO + default "candy" if BOARD_GOOGLE_CANDY + default "clapper" if BOARD_GOOGLE_CLAPPER default "enguarde" if BOARD_GOOGLE_ENGUARDE + default "glimmer" if BOARD_GOOGLE_GLIMMER + default "gnawty" if BOARD_GOOGLE_GNAWTY + default "heli" if BOARD_GOOGLE_HELI + default "kip" if BOARD_GOOGLE_KIP default "ninja" if BOARD_GOOGLE_NINJA + default "orco" if BOARD_GOOGLE_ORCO + default "quawks" if BOARD_GOOGLE_QUAWKS default "rambi" if BOARD_GOOGLE_RAMBI + default "squawks" if BOARD_GOOGLE_SQUAWKS + default "sumo" if BOARD_GOOGLE_SUMO + default "swanky" if BOARD_GOOGLE_SWANKY + default "winky" if BOARD_GOOGLE_WINKY config MAINBOARD_PART_NUMBER string + default "Banjo" if BOARD_GOOGLE_BANJO + default "Candy" if BOARD_GOOGLE_CANDY + default "Clapper" if BOARD_GOOGLE_CLAPPER default "Enguarde" if BOARD_GOOGLE_ENGUARDE + default "Glimmer" if BOARD_GOOGLE_GLIMMER + default "Gnawty" if BOARD_GOOGLE_GNAWTY + default "Heli" if BOARD_GOOGLE_HELI + default "Kip" if BOARD_GOOGLE_KIP default "Ninja" if BOARD_GOOGLE_NINJA + default "Orco" if BOARD_GOOGLE_ORCO + default "Quawks" if BOARD_GOOGLE_QUAWKS default "Rambi" if BOARD_GOOGLE_RAMBI + default "Squawks" if BOARD_GOOGLE_SQUAWKS + default "Sumo" if BOARD_GOOGLE_SUMO + default "Swanky" if BOARD_GOOGLE_SWANKY + default "Winky" if BOARD_GOOGLE_WINKY config GBB_HWID string depends on CHROMEOS + default "BANJO TEST A-A 8843" if BOARD_GOOGLE_BANJO + default "CANDY TEST A-A 3347" if BOARD_GOOGLE_CANDY + default "CLAPPER TEST A-A 7705" if BOARD_GOOGLE_CLAPPER default "ENGUARDE TEST A-A 0128" if BOARD_GOOGLE_ENGUARDE + default "GLIMMER TEST 8028" if BOARD_GOOGLE_GLIMMER + default "GNAWTY TEST A-A 3347" if BOARD_GOOGLE_GNAWTY + default "HELI TEST A-A 7705" if BOARD_GOOGLE_HELI + default "KIP TEST A-A 0128" if BOARD_GOOGLE_KIP default "NINJA TEST A-A 0653" if BOARD_GOOGLE_NINJA + default "ORCO TEST 8028" if BOARD_GOOGLE_ORCO + default "QUAWKS TEST A-A 3347" if BOARD_GOOGLE_QUAWKS default "RAMBI TEST A-A 0128" if BOARD_GOOGLE_RAMBI + default "SQUAWKS TEST A-A 7705" if BOARD_GOOGLE_SQUAWKS + default "SUMO TEST A-A 8843" if BOARD_GOOGLE_SUMO + default "SWANKY TEST A-A 0653" if BOARD_GOOGLE_SWANKY + default "WINKY TEST 0128" if BOARD_GOOGLE_WINKY config DEVICETREE string + default "variants/banjo/devicetree.cb" if BOARD_GOOGLE_BANJO + default "variants/candy/devicetree.cb" if BOARD_GOOGLE_CANDY + default "variants/clapper/devicetree.cb" if BOARD_GOOGLE_CLAPPER default "variants/enguarde/devicetree.cb" if BOARD_GOOGLE_ENGUARDE + default "variants/glimmer/devicetree.cb" if BOARD_GOOGLE_GLIMMER + default "variants/gnawty/devicetree.cb" if BOARD_GOOGLE_GNAWTY + default "variants/heli/devicetree.cb" if BOARD_GOOGLE_HELI + default "variants/kip/devicetree.cb" if BOARD_GOOGLE_KIP default "variants/ninja/devicetree.cb" if BOARD_GOOGLE_NINJA + default "variants/orco/devicetree.cb" if BOARD_GOOGLE_ORCO + default "variants/quawks/devicetree.cb" if BOARD_GOOGLE_QUAWKS default "variants/rambi/devicetree.cb" if BOARD_GOOGLE_RAMBI + default "variants/squawks/devicetree.cb" if BOARD_GOOGLE_SQUAWKS + default "variants/sumo/devicetree.cb" if BOARD_GOOGLE_SUMO + default "variants/swanky/devicetree.cb" if BOARD_GOOGLE_SWANKY + default "variants/winky/devicetree.cb" if BOARD_GOOGLE_WINKY config EC_GOOGLE_CHROMEEC_BOARDNAME string diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name index 0305bc4..12cc3ff 100644 --- a/src/mainboard/google/rambi/Kconfig.name +++ b/src/mainboard/google/rambi/Kconfig.name @@ -1,11 +1,63 @@ +config BOARD_GOOGLE_BANJO + bool "Banjo" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_CANDY + bool "Candy" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_CLAPPER + bool "Clapper" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_ENGUARDE bool "Enguarde" select BOARD_GOOGLE_BASEBOARD_RAMBI +config BOARD_GOOGLE_GLIMMER + bool "Glimmer" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_GNAWTY + bool "Gnawty" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_HELI + bool "Heli" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_KIP + bool "Kip" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_NINJA bool "Ninja" select BOARD_GOOGLE_BASEBOARD_RAMBI +config BOARD_GOOGLE_ORCO + bool "Orco" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_QUAWKS + bool "Quawks" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_SQUAWKS + bool "Squawks" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_RAMBI bool "Rambi" select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_SUMO + bool "Sumo" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_SWANKY + bool "Swanky" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_WINKY + bool "Winky" + select BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index b08002d..7c0fb35 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -24,6 +24,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c +ramstage-$(CONFIG_BOARD_GOOGLE_SUMO) += variants/$(VARIANT_DIR)/lan.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/rambi/acpi/touchscreen_elan.asl b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl new file mode 100644 index 0000000..ac0763d --- /dev/null +++ b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C6) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "ELAN Touchscreen") + Name (_UID, 1) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl new file mode 100644 index 0000000..0b5c100 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C6) +{ + Device (WTSA) + { + Name (_HID, "WDHT0001") + Name (_DDN, "WDT Touchscreen") + Name (_UID, 6) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index eaf3079..acd4ffe 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -129,7 +129,7 @@ static int int15_handler(void) static void mainboard_init(device_t dev) { mainboard_ec_init(); -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO) lan_init(); #endif } diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 152d5e6..d8ba001 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -32,11 +32,15 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) ssus_disable_internal_pull(GPIO_SSUS_37_PAD); ssus_disable_internal_pull(GPIO_SSUS_38_PAD); ssus_disable_internal_pull(GPIO_SSUS_39_PAD); - +#ifdef GPIO_SSUS_40_PAD + ssus_disable_internal_pull(GPIO_SSUS_40_PAD); +#endif ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); - +#ifdef GPIO_SSUS_40_PAD + ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3); +#endif printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); if (ram_id >= total_spds) diff --git a/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex b/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex new file mode 100644 index 0000000..19fa083 --- /dev/null +++ b/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 40 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 07 92 01 +00 00 00 00 00 00 CC FB +48 54 54 43 34 47 36 33 +43 46 52 2D 50 42 41 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..ae17756 --- /dev/null +++ b/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4B 34 42 34 47 31 36 34 +36 51 2D 48 59 4B 30 20 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex b/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex new file mode 100644 index 0000000..fc27f6b --- /dev/null +++ b/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex b/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex new file mode 100644 index 0000000..6e3eab3 --- /dev/null +++ b/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex @@ -0,0 +1,16 @@ +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/rambi/spd/empty.spd.hex b/src/mainboard/google/rambi/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/rambi/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex new file mode 100644 index 0000000..0e8c1bd --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex @@ -0,0 +1,16 @@ +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 22 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 96 77 +48 4D 54 34 32 35 53 36 4D 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex new file mode 100644 index 0000000..b8815c8 --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex @@ -0,0 +1,32 @@ +92 13 0b 03 04 19 02 02 +03 11 01 08 09 00 fe 02 +69 78 69 30 69 11 10 79 +20 08 3c 3c 01 18 83 05 +00 00 ca 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 ec b8 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 39 50 +31 20 50 32 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex new file mode 100644 index 0000000..91133b4 --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex @@ -0,0 +1,32 @@ +92 13 0b 03 04 19 02 02 +03 11 01 08 09 00 fe 02 +69 78 69 30 69 11 10 79 +20 08 3c 3c 01 18 83 05 +00 00 ca 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 45 1d +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 39 50 +31 20 50 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex new file mode 100644 index 0000000..841291b --- /dev/null +++ b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646E-BYK0 +92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F +4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc new file mode 100644 index 0000000..e925263 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b101 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb new file mode 100644 index 0000000..e380920 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Banjo board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x0" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c new file mode 100644 index 0000000..bfb2c9a --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_NC, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_NC, /* S0-SC033 - SD3_CLK */ + GPIO_NC, /* S0-SC034 - SD3_D0 */ + GPIO_NC, /* S0-SC035 - SD3_D1 */ + GPIO_NC, /* S0-SC036 - SD3_D2 */ + GPIO_NC, /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_NC, /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_NC, /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - I2C_4_SDA */ + GPIO_NC, /* S0-SC087 - I2C_4_SCL */ + GPIO_NC, /* S0-SC088 - I2C_5_SDA */ + GPIO_NC, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..4276b1c --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 46 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 44 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..5a46bdc --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h new file mode 100644 index 0000000..38410e1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h new file mode 100644 index 0000000..afb1dff --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b101 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +*/ + +static const uint32_t dual_channel_config = + (1 << 1) | (1 << 3) | (1 << 5) ; + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc new file mode 100644 index 0000000..0a53d84 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b0010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b0011 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b0100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz +# 0b0111 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz +# 0b1000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz +# 0b1001 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz +# 0b1010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b1011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb new file mode 100644 index 0000000..5cbb974 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Candy board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c new file mode 100644 index 0000000..3cbfbaf --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - NC */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_INPUT_PD_20K, /* S540 - RAM_ID3 */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..8dd0885 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 85 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 53 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 70 +#define DPTF_TSR2_CRITICAL 80 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..33d3209 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Elan touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_elan.asl> diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h new file mode 100644 index 0000000..9a69821 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h new file mode 100644 index 0000000..0c58cee --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[3:0] are on GPIO_SSUS[40:37] + * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0111 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz + * 0b1000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b1001 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz + * 0b1010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b1011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 +#define GPIO_SSUS_40_PAD 52 + +#endif diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc new file mode 100644 index 0000000..1a01c8a --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb new file mode 100644 index 0000000..a95ddd1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -0,0 +1,89 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Clapper board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "5" # 400ms + register "gpu_pipea_power_on_delay" = "2000" # 200ms + register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c new file mode 100644 index 0000000..385b406 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_FUNC2, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ + GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ + GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_FUNC0, /* S537 - RAM_ID0 */ + GPIO_FUNC0, /* S538 - RAM_ID1 */ + GPIO_FUNC0, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..53dd09c --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 40 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 35 +#define DPTF_TSR2_CRITICAL 70 + +#undef DPTF_ENABLE_CHARGER diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..5a1db34 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Amtel touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_amtel.asl> diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h new file mode 100644 index 0000000..016f657 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h new file mode 100644 index 0000000..38b156c --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl index 772b4ba..3cdd5c0 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl @@ -12,7 +12,5 @@ * GNU General Public License for more details. */ -#include <variant/onboard.h> - /* Elan trackpad */ #include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h index 1477794..2a1045d 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h @@ -31,6 +31,4 @@ #define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) #define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) -#define BOARD_ALS_I2C_ADDR 0x44 - #endif diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc new file mode 100644 index 0000000..341f6d3 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz +# 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb new file mode 100644 index 0000000..bf01cd9 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb @@ -0,0 +1,98 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Glimmer board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c new file mode 100644 index 0000000..8cfe90e --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT (NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + /* TODO(shawnn): Change to normal input once our old boards + * are no longer in use. */ + GPIO_FUNC(0, PULL_DOWN, 20K), /* S540 - RAM_ID3 */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..6e2630b --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Power_Bottom" +#define DPTF_TSR0_PASSIVE 75 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_RAM_bottom" +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 75 +#define DPTF_TSR2_CRITICAL 80 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x8ca, "mA", 0 }, /* 2.25A (MAX) */ + Package () { 0, 0, 0, 0, 32, 0x7d0, "mA", 0 }, /* 2.0A */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..5a1db34 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Amtel touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_amtel.asl> diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h new file mode 100644 index 0000000..121da36 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h new file mode 100644 index 0000000..0ea42c5 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz + * 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | + (1 << 4) | (1 << 6) | (1 << 7); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 +#define GPIO_SSUS_40_PAD 52 + +#endif diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc new file mode 100644 index 0000000..05fbc69 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b111 - 4GiB total - 2 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb new file mode 100644 index 0000000..bb6fcad --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Gnawty board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c new file mode 100644 index 0000000..e79dc5a --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..1df96fa --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 70 +#define DPTF_TSR1_CRITICAL 85 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 44 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h new file mode 100644 index 0000000..86ca488 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h new file mode 100644 index 0000000..f81a0dd --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b111 - 4GiB total - 2 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz +*/ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) ; + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc new file mode 100644 index 0000000..d76a127 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# RAM_ID Vendor Vendor_PN Freq Size Total_size channel +# 0b0011 Hynix H5TC4G63AFR-PBA 1600MHZ 4Gb 2GB single-channel +# 0b0100 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 2GB single-channel +# 0b0101 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 2GB single-channel +# 0b0110 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 4GB dual-channel +# 0b0111 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 4GB dual-channel +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += empty # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA # 0b0011 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA # 0b0100 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b0101 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA # 0b0110 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b0111 +SPD_SOURCES += empty # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += empty # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb new file mode 100644 index 0000000..d9b27e6 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Heli board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c new file mode 100644 index 0000000..2a61c55 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_NC, /* S0-SC058 - SIM_DET_C (NC)*/ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L (NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_NC, /* S0-SC072 - TOUCH_INT_L_DX (NC) */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# (NC) */ + GPIO_NC, /* S503 - LTE_WAKE_L# (NC) */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_NC, /* S535 - LTE_DISABLE_L (NC) */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_INPUT, /* S540 - RAM_ID3 */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..adc796d --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 52 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h new file mode 100644 index 0000000..f4ffed5 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h new file mode 100644 index 0000000..d25b9c9 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[3:0] are on GPIO_SSUS[40:37] + * RAM_ID Vendor Vendor_PN Freq Size Total_size channel + * 0b0011 Hynix H5TC4G63AFR-PBA 1600MHZ 4Gb 2GB single-channel + * 0b0100 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 2GB single-channel + * 0b0101 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 2GB single-channel + * 0b0110 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 4GB dual-channel + * 0b0111 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 4GB dual-channel + */ + +static const uint32_t dual_channel_config = + (1 << 6) | (1 << 7); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 +#define GPIO_SSUS_40_PAD 52 + +#endif diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc new file mode 100644 index 0000000..06bd0e7 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125a +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125a +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb new file mode 100644 index 0000000..f4e0a91 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Kip board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..e88ac7d --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 58 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 58 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 57 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h new file mode 100644 index 0000000..4bb37be --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h new file mode 100644 index 0000000..7f058d7 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc new file mode 100644 index 0000000..1f9706e --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb new file mode 100644 index 0000000..8291794 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Orco board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c new file mode 100644 index 0000000..f2bbe8a --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT (NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - I2C_4_SDA */ + GPIO_NC, /* S0-SC087 - I2C_4_SCL */ + GPIO_NC, /* S0-SC088 - I2C_5_SDA */ + GPIO_NC, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# - INT */ + GPIO_NC, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..3530d7b --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h new file mode 100644 index 0000000..b4a6c6e --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h new file mode 100644 index 0000000..ab81162 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc new file mode 100644 index 0000000..48956a1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb new file mode 100644 index 0000000..cc5146d --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb @@ -0,0 +1,98 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Quawks board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..7e36946 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 52 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 51 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 51 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6A4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */ + Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */ + Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */ + Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */ +}) diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h new file mode 100644 index 0000000..4bb37be --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h new file mode 100644 index 0000000..2b80bf4 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc new file mode 100644 index 0000000..48956a1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb new file mode 100644 index 0000000..400a551 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -0,0 +1,98 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Squawks board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..b17f980 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 53 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 80 +#define DPTF_TSR1_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 53 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x7d0, "mA", 0 }, /* 2.0A */ + Package () { 0, 0, 0, 0, 24, 0x6a4, "mA", 0 }, /* 1.7A */ + Package () { 0, 0, 0, 0, 16, 0x578, "mA", 0 }, /* 1.4A */ + Package () { 0, 0, 0, 0, 8, 0x3e8, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 0, 0x258, "mA", 0 }, /* 0.6A */ +}) diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h new file mode 100644 index 0000000..4bb37be --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h new file mode 100644 index 0000000..2b80bf4 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc new file mode 100644 index 0000000..b2552d3 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb new file mode 100644 index 0000000..89e2f2b --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Sumo board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c new file mode 100644 index 0000000..0856c29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_FUNC2, /* S0_NC07 - DDI1_DDCDATA */ + GPIO_FUNC2, /* S0_NC08 - DDI1_DDCCLK */ + GPIO_NC, /* S0_NC09 - NC */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_NC, /* S0_SC001 - NC */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE0# */ + GPIO_NC, /* S0-SC004 - NC# */ + GPIO_FUNC1, /* S0-SC005 - PCIE_CLKREQ_WLAN# */ + GPIO_FUNC1, /* S0-SC006 - PCIE_CLKREQ_LAN# */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_FUNC1, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_FUNC1, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_NC, /* S0-SC055 - NC */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - NC */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_NC, /* S0-SC076 - NC */ + GPIO_NC, /* S0-SC077 - NC */ + GPIO_NC, /* S0-SC078 - NC */ + GPIO_NC, /* S0-SC079 - NC */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - NC */ + GPIO_NC, /* S0-SC087 - NC */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_NC, /* S501 - NC */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_INPUT, /* S508 - SOC_RECOVER- */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..3530d7b --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..e7f06ee --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* WDT touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_wdt.asl> diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h new file mode 100644 index 0000000..1fb268a --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +#ifndef __ACPI__ +void lan_init(void); +#endif + +/* defines for programming the MAC address */ +#define SUMO_NIC_VENDOR_ID 0x10EC +#define SUMO_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define SUMO_NIC_LED_MODE 0x00 + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x2c + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +/* Disable PS2 keyboard */ +#undef SIO_EC_ENABLE_PS2K + +#endif diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h new file mode 100644 index 0000000..8d2113c --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c new file mode 100644 index 0000000..07fe3d9 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <variant/onboard.h> + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(SUMO_NIC_VENDOR_ID, + SUMO_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((SUMO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc new file mode 100644 index 0000000..1458ebb --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb new file mode 100644 index 0000000..5e78a10 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Swanky board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c new file mode 100644 index 0000000..a713549 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_INPUT, /* S541 - PANEL_ID */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..e9b78a8 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h new file mode 100644 index 0000000..f4ffed5 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h new file mode 100644 index 0000000..483983b --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc new file mode 100644 index 0000000..962f30c --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb +# 0b001 - 4GiB total - 2 x Samsung_2Gib_K4B4G1646Q-HYK0 +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb +# 0b101 - 2GiB total - 1 x Samsung_2Gib_K4B4G1646Q-HYK0 +SPD_SOURCES = HT_micron_HTTC4G63CFR-PBA_x16_4Gb +SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0 +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += HT_micron_HTTC4G63CFR-PBA_x16_4Gb +SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb new file mode 100644 index 0000000..6d52b89 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Winky board + register "usb2_comp_bg" = "0x4680" + register "usb2_per_port_lane0" = "0x0004C209" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x0004B209" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c new file mode 100644 index 0000000..2242f98 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_NC, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - NC */ + GPIO_NC, /* S0-SC087 - NC */ + GPIO_NC, /* S0-SC088 - NC */ + GPIO_NC, /* S0-SC089 - NC */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# - INT */ + GPIO_NC, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..3530d7b --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..94d9491 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Amtel trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_amtel.asl> diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h new file mode 100644 index 0000000..9771179 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x4b + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h new file mode 100644 index 0000000..6bf5569 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif

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Patch set updated for coreboot: mainboards/hp: Add HP Elitebook 2760p
by Iru Cai 27 Jan '17

27 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18241 -gerrit commit 662e1bb76750199f1800f8c1de329949bb009156 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Jan 26 14:51:47 2017 +0800 mainboards/hp: Add HP Elitebook 2760p The code is generated by autoport. The flash chip is socketed beside the WLAN slot. The EHCI debug port is on right side of the laptop beside the RJ11 connector. Things that work: - memory: 0+8G, 4G+8G - Linux (Linux Mint 18.1 with Linux 4.4) - native graphics init + SeaBIOS payload with SeaVGABIOS - all 3 USB ports - WLAN - S3 suspend and resume Things that don't work: - keyboard (use a USB keyboard instead) - AC and battery status - wacom digitizer - fan control (fan always runs on full speed) Things that are not tested: - WWAN - SD card reader - smart card reader - expresscard - cable modem (EC) blobs: This laptop uses SMSC KBC1126-NU as EC. It may need some blobs in the flash chip. - There may be some data needed by EC at 0x7ff700-0x7fff07, which needs to be copied from the factory firmware. - Range 0x780000-0x79ffff of the flash chip may contain EC firmware (it has strings like `8051 Reset', and modifying it can brick the machine), so now I set the CBFS size to 0x60000. Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/hp/2760p/Kconfig | 70 +++++ src/mainboard/hp/2760p/Kconfig.name | 2 + src/mainboard/hp/2760p/Makefile.inc | 2 + src/mainboard/hp/2760p/acpi/ec.asl | 7 + src/mainboard/hp/2760p/acpi/platform.asl | 10 + src/mainboard/hp/2760p/acpi/superio.asl | 1 + src/mainboard/hp/2760p/acpi_tables.c | 1 + src/mainboard/hp/2760p/board_info.txt | 6 + src/mainboard/hp/2760p/devicetree.cb | 111 ++++++++ src/mainboard/hp/2760p/dsdt.asl | 30 +++ src/mainboard/hp/2760p/gnvs.c | 19 ++ src/mainboard/hp/2760p/gpio.c | 433 +++++++++++++++++++++++++++++++ src/mainboard/hp/2760p/hda_verb.c | 65 +++++ src/mainboard/hp/2760p/mainboard.c | 25 ++ src/mainboard/hp/2760p/romstage.c | 66 +++++ 15 files changed, 848 insertions(+) diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig new file mode 100644 index 0000000..a228572 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig @@ -0,0 +1,70 @@ +if BOARD_HP_2760P + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/2760p + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook 2760p" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x162a + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0x8f0 + +endif diff --git a/src/mainboard/hp/2760p/Kconfig.name b/src/mainboard/hp/2760p/Kconfig.name new file mode 100644 index 0000000..4a6a8e5 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_2760P + bool "HP EliteBook 2760p" diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc new file mode 100644 index 0000000..c55eebe --- /dev/null +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/hp/2760p/acpi/ec.asl b/src/mainboard/hp/2760p/acpi/ec.asl new file mode 100644 index 0000000..aea3c58 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 22) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/platform.asl b/src/mainboard/hp/2760p/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/superio.asl b/src/mainboard/hp/2760p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/2760p/acpi_tables.c b/src/mainboard/hp/2760p/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/hp/2760p/board_info.txt b/src/mainboard/hp/2760p/board_info.txt new file mode 100644 index 0000000..ae1ca3b --- /dev/null +++ b/src/mainboard/hp/2760p/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: yes +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb new file mode 100644 index 0000000..34acfaf --- /dev/null +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000129" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x007c0281" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x21" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x162a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x162a + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x162a + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x162a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x162a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x162a + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x162a + end + device pci 1c.3 on # WLAN + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x162a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x162a + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x162a + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x162a + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x162a + end + end +end diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl new file mode 100644 index 0000000..3b7fb7e --- /dev/null +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/hp/2760p/gnvs.c b/src/mainboard/hp/2760p/gnvs.c new file mode 100644 index 0000000..37cd5c9 --- /dev/null +++ b/src/mainboard/hp/2760p/gnvs.c @@ -0,0 +1,19 @@ +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/2760p/gpio.c b/src/mainboard/hp/2760p/gpio.c new file mode 100644 index 0000000..65bff4e --- /dev/null +++ b/src/mainboard/hp/2760p/gpio.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c new file mode 100644 index 0000000..c60846e --- /dev/null +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -0,0 +1,65 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162a, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c162a), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a70130), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x40f000f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + + 0x00000001, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x1, 0x103c3066), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/2760p/mainboard.c b/src/mainboard/hp/2760p/mainboard.c new file mode 100644 index 0000000..5809af5 --- /dev/null +++ b/src/mainboard/hp/2760p/mainboard.c @@ -0,0 +1,25 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; + RCBA32(0x38c0) = 0x00000007; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c new file mode 100644 index 0000000..b94596a --- /dev/null +++ b/src/mainboard/hp/2760p/romstage.c @@ -0,0 +1,66 @@ +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0201); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0101); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00fcfe01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x007c0281); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x82000000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x1ff01feb; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 0, 0, 4 }, + { 0, 0, 5 }, + { 1, 1, 5 }, + { 0, 0, 6 }, + { 1, 1, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +}

1 0

Patch set updated for coreboot: [RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR
by Iru Cai 27 Jan '17

27 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14208 -gerrit commit 061bad5b78a6ef80ddc91c27344e0e95d85ad68a Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Mar 31 15:32:25 2016 +0800 [RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR HP Elitebook 2760p (and some other HP laptops) stores some data which may be used by EC in bootblock region. So some space needs to be reserved before the reset vector. Change-Id: I992d285a1a76883ff7a69445a0ff9efe62dbbd7f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/failover.ld | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6280024..1daddd9 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -181,6 +181,10 @@ config ID_SECTION_OFFSET hex default 0x80 +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0xf0 + # 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index e9613d9..a434704 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -50,8 +50,8 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + ROMLOC_MIN = 0xfffffff0 - CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR + - (_erom - _rom + 16) - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); /* Post-check proper SIPI vector. */ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),

1 0

Patch merged into coreboot/master: board_status/to-wiki: Update bucketize script
by gerrit＠coreboot.org 27 Jan '17

27 Jan '17

the following patch was just integrated into master: commit 27f3ce6337b293cfc7be0eb8592feb411cf2cc5f Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 24 21:13:18 2017 -0700 board_status/to-wiki: Update bucketize script - Fix TODO: restrict $1 to allowed values. - Specifically exclude 'oem' board status directories. - Exclude any directory that doesn't follow the date format to keep the script from breaking again in the future if something it doesn't recognize is pushed. Just ignore it for the wiki. - Fix shellcheck warnings. Change-Id: I2864f09f5f1b1f5ec626d06e4849830400ef5814 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18225 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18225 for details. -gerrit

1 0

Patch set updated for coreboot: hp/2760p: reserve space in bootblock
by Iru Cai 27 Jan '17

27 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14209 -gerrit commit a2b07cd8e18a5b601c00b6b0a056c97890f48810 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Mar 31 23:13:09 2016 +0800 hp/2760p: reserve space in bootblock The space from 0x7ff700 to 0x7fff07 is reserved for data needed by (maybe) EC. The default ID_SECTION_OFFSET is enough so it doesn't need to be changed. Change-Id: Iae7eb8a67fcce173500d91951ee71a3361475fc9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/hp/2760p/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index 440c1f6..20ed531 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -62,4 +62,9 @@ config MAX_CPUS config USBDEBUG_HCD_INDEX int default 1 + +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0x900 + endif

1 0

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coreboot-gerrit January 2017