coreboot-gerrit January 2017

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Patch set updated for coreboot: msrtool: add support for printing string values
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18257 -gerrit commit 652f7e57f6be46f6fe8615248da6e0783ee7ff0f Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:19:33 2017 +0100 msrtool: add support for printing string values The VIA CPUs allow setting the CPUID vendor, which is best read as a character string. Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/msrtool.h | 4 +++- util/msrtool/msrutils.c | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 6565fff..7e85dc0 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -45,7 +45,8 @@ enum { PRESENT_BIN, PRESENT_OCT, PRESENT_HEX, - PRESENT_HEXDEC + PRESENT_HEXDEC, + PRESENT_STR, } PresentTypes; struct msr { @@ -162,6 +163,7 @@ struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); /* msrutils.c */ void hexprint(FILE *f, const struct msr val, const uint8_t bits); +void strprint(FILE *f, const struct msr val, const uint8_t bits); int msr_eq(const struct msr a, const struct msr b); struct msr msr_shl(const struct msr a, const uint8_t bits); struct msr msr_shr(const struct msr a, const uint8_t bits); diff --git a/util/msrtool/msrutils.c b/util/msrtool/msrutils.c index 57a271d..471ed29 100644 --- a/util/msrtool/msrutils.c +++ b/util/msrtool/msrutils.c @@ -65,6 +65,9 @@ static void print_bitval(FILE *f, const struct msrbits *mb, const struct msr val hexprint(f, val, mb->size); fprintf(f, " %d", val.lo); break; + case PRESENT_STR: + strprint(f, val, mb->size); + break; } if (mbv->text) fprintf(f, ": %s", mbv->text); @@ -106,6 +109,25 @@ void hexprint(FILE *f, const struct msr val, const uint8_t bits) { fprintf(f, "0x%08x%08x", val.hi, val.lo); } +void strprint(FILE *f, const struct msr val, const uint8_t bits) { + if (bits >= 64) + fputc(val.hi, f); + if (bits >= 56) + fputc(val.hi >> 8, f); + if (bits >= 48) + fputc(val.hi >> 16, f); + if (bits >= 40) + fputc(val.hi >> 24, f); + if (bits >= 32) + fputc(val.lo, f); + if (bits >= 24) + fputc(val.lo >> 8, f); + if (bits >= 16) + fputc(val.lo >> 16, f); + if (bits >= 8) + fputc(val.lo >> 24, f); +} + int msr_eq(const struct msr a, const struct msr b) { return a.hi == b.hi && a.lo == b.lo; }

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Patch set updated for coreboot: mstrool: only use intel targets for actual intel CPUs
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18256 -gerrit commit c08ecefeccfa48cb55f3d4edca673c190ba76076 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:19:24 2017 +0100 mstrool: only use intel targets for actual intel CPUs VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite Pentium III. Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/intel_atom.c | 5 +++-- util/msrtool/intel_core1.c | 4 +++- util/msrtool/intel_core2_early.c | 4 +++- util/msrtool/intel_core2_later.c | 4 +++- util/msrtool/intel_nehalem.c | 3 ++- util/msrtool/intel_pentium3.c | 3 ++- util/msrtool/intel_pentium3_early.c | 3 ++- util/msrtool/intel_pentium4_early.c | 4 +++- util/msrtool/intel_pentium4_later.c | 3 ++- 9 files changed, 23 insertions(+), 10 deletions(-) diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index c055f4c..2d89c9c 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -16,8 +16,9 @@ #include "msrtool.h" int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) { - return (0x6 == id->family) && - (0x1c == id->model); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0x1c == id->model)); } const struct msrdef intel_atom_msrs[] = { diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c index ef2b660..039a2f8 100644 --- a/util/msrtool/intel_core1.c +++ b/util/msrtool/intel_core1.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_core1_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && (0xe == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0xe == id->model)); } const struct msrdef intel_core1_msrs[] = { diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c index a9b742f..1072624 100644 --- a/util/msrtool/intel_core2_early.c +++ b/util/msrtool/intel_core2_early.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && (0xf == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0xf == id->model)); } const struct msrdef intel_core2_early_msrs[] = { diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 3cb28c6..ad353eb 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_core2_later_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family)&(0x17 == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0x17 == id->model)); } const struct msrdef intel_core2_later_msrs[] = { diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index c133653..679efb5 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_nehalem_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && ( (0x1a == id->model) || (0x1e == id->model) || (0x1f == id->model) || diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c index 456963f..6b12428 100644 --- a/util/msrtool/intel_pentium3.c +++ b/util/msrtool/intel_pentium3.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_pentium3_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && ( (0xa == id->model) || (0xb == id->model) )); diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c index 925b24f..afdc62e 100644 --- a/util/msrtool/intel_pentium3_early.c +++ b/util/msrtool/intel_pentium3_early.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_pentium3_early_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && ( (0x7 == id->model) || (0x8 == id->model) )); diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c index 537d9e3..649be04 100644 --- a/util/msrtool/intel_pentium4_early.c +++ b/util/msrtool/intel_pentium4_early.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_pentium4_early_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0xf == id->family) && (0x2 == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0xf == id->family) && + (0x2 == id->model)); } const struct msrdef intel_pentium4_early_msrs[] = { diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c index cc85f65..5444161 100644 --- a/util/msrtool/intel_pentium4_later.c +++ b/util/msrtool/intel_pentium4_later.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_pentium4_later_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0xf == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0xf == id->family) && ( (0x3 == id->model) || (0x4 == id->model) ));

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Patch set updated for coreboot: msrtool: use a bit more clever cpuid vendor match
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18255 -gerrit commit ddfe24d1f7f0e2c7785ca1fc3e2082e2ed073f0f Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:19:21 2017 +0100 msrtool: use a bit more clever cpuid vendor match Not everyting non-intel is AMD. Change-Id: I06d6fbaa0b4f2c9e61d9b3b4aeeb349a91aa090e Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/msrtool.h | 4 ++-- util/msrtool/sys.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index fe7f0f0..6565fff 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -94,8 +94,8 @@ struct msrdef { #define MAX_CORES 8 typedef enum { - VENDOR_INTEL = 1, - VENDOR_AMD = 2, + VENDOR_INTEL = 0x756e6547, + VENDOR_AMD = 0x68747541, } vendor_t; struct cpuid_t { diff --git a/util/msrtool/sys.c b/util/msrtool/sys.c index 3e50f49..7ff1131 100644 --- a/util/msrtool/sys.c +++ b/util/msrtool/sys.c @@ -36,7 +36,7 @@ struct cpuid_t *cpuid(void) { asm ("cpuid" : "=b" (outebx) : "a" (0) : "%ecx", "%edx"); #endif - id.vendor = (outebx == 0x756e6547) ? VENDOR_INTEL : VENDOR_AMD; + id.vendor = outebx; /* Then, identificate CPU itself */ #if defined(__DARWIN__) && !defined(__LP64__)

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New patch to review for coreboot: msrtool: add VIA C7
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18258 -gerrit commit 1f0bdd4af142bb3732e2be6901683fe656a34289 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:20:04 2017 +0100 msrtool: add VIA C7 Change-Id: I67c4f579f898a709dde3fab6bab1474a721da770 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/Makefile.in | 2 +- util/msrtool/msrtool.c | 1 + util/msrtool/msrtool.h | 5 + util/msrtool/via_c7.c | 475 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 482 insertions(+), 1 deletion(-) diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in index 708515f..76b6a4b 100644 --- a/util/msrtool/Makefile.in +++ b/util/msrtool/Makefile.in @@ -22,7 +22,7 @@ PREFIX = @PREFIX@ CFLAGS = @CFLAGS@ -fno-pic LDFLAGS = @LDFLAGS@ -TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o +TARGETS = geodegx2.o geodelx.o cs5536.o k8.o via_c7.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o SYSTEMS = linux.o darwin.o freebsd.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 4060ba3..4f7c0ee 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -40,6 +40,7 @@ static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, { "K8", "AMD K8 Family", k8_probe, k8_msrs }, + { "via_c7", "VIA Esther processor, C7", via_c7_probe, via_c7_msrs }, { "intel_pentium3_early", "Intel Pentium III family", intel_pentium3_early_probe, intel_pentium3_early_msrs }, { "intel_pentium3", "Intel Pentium III Xeon Processor, Intel Pentium III Processor", intel_pentium3_probe, intel_pentium3_msrs }, { "intel_core1", "Intel Core Duo, Intel Core Solo processors", intel_core1_probe, intel_core1_msrs }, diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 7e85dc0..8559980 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -97,6 +97,7 @@ struct msrdef { typedef enum { VENDOR_INTEL = 0x756e6547, VENDOR_AMD = 0x68747541, + VENDOR_CENTAUR = 0x746e6543, } vendor_t; struct cpuid_t { @@ -216,6 +217,10 @@ extern const struct msrdef cs5536_msrs[]; extern int k8_probe(const struct targetdef *t, const struct cpuid_t *id); extern const struct msrdef k8_msrs[]; +/* via_c7.c */ +extern int via_c7_probe(const struct targetdef *t, const struct cpuid_t *id); +extern const struct msrdef via_c7_msrs[]; + /* intel_pentium3_early.c */ extern int intel_pentium3_early_probe(const struct targetdef *t, const struct cpuid_t *id); extern const struct msrdef intel_pentium3_early_msrs[]; diff --git a/util/msrtool/via_c7.c b/util/msrtool/via_c7.c new file mode 100644 index 0000000..83668e9 --- /dev/null +++ b/util/msrtool/via_c7.c @@ -0,0 +1,475 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * Copyright (C) 2017 Lubomir Rintel <lkundrak(a)v3.sk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msrtool.h" + +int via_c7_probe(const struct targetdef *target, const struct cpuid_t *id) { + return ((VENDOR_CENTAUR == id->vendor) && + (0x6 == id->family) && ( + (0xa == id->model) || /* C7 A */ + (0xd == id->model) || /* C7 D */ + (0xf == id->model) /* Nano */ + )); +} + +const struct msrdef via_c7_msrs[] = { + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[15:8] > 0 */ + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + "Performance Event Select Register 0", { + { 63, 32, RESERVED }, + { 31, 8, "CMASK", "R/W", PRESENT_HEX, { + /* When CMASK is not zero, the corresponding performance + * counter 0 increments each cycle if the event count + * is greater than or equal to the CMASK. + */ + { BITVAL_EOT } + }}, + { 23, 1, "INV", "R/W", PRESENT_BIN, { + { MSR1(0), "CMASK using as is" }, + { MSR1(1), "CMASK inerting" }, + { BITVAL_EOT } + }}, + { 22, 1, "EN", "R/W", PRESENT_BIN, { + { MSR1(0), "No commence counting" }, + { MSR1(1), "Commence counting" }, + { BITVAL_EOT } + }}, + { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "INT", "R/W", PRESENT_BIN, { + { MSR1(0), "Interrupt on counter overflow is disabled" }, + { MSR1(1), "Interrupt on counter overflow is enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "PC", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled pin control" }, + { MSR1(1), "Enabled pin control" }, + { BITVAL_EOT } + }}, + { 18, 1, "Edge", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled edge detection" }, + { MSR1(1), "Enabled edge detection" }, + { BITVAL_EOT } + }}, + { 17, 1, "OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is ring 0" }, + { BITVAL_EOT } + }}, + { 16, 1, "USR", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is not ring 0" }, + { BITVAL_EOT } + }}, + { 15, 8, "UMask", "R/W", PRESENT_HEX, { + /* Qualifies the microarchitectural condition + * to detect on the selected event logic. */ + { BITVAL_EOT } + }}, + { 7, 8, "Event Select", "R/W", PRESENT_HEX, { + /* Selects a performance event logic unit. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[15:8] > 0 */ + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + "Performance Event Select Register 1", { + { 63, 32, RESERVED }, + { 31, 8, "CMASK", "R/W", PRESENT_HEX, { + /* When CMASK is not zero, the corresponding performance + * counter 1 increments each cycle if the event count + * is greater than or equal to the CMASK. + */ + { BITVAL_EOT } + }}, + { 23, 1, "INV", "R/W", PRESENT_BIN, { + { MSR1(0), "CMASK using as is" }, + { MSR1(1), "CMASK inerting" }, + { BITVAL_EOT } + }}, + { 22, 1, "EN", "R/W", PRESENT_BIN, { + { MSR1(0), "No commence counting" }, + { MSR1(1), "Commence counting" }, + { BITVAL_EOT } + }}, + { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "INT", "R/W", PRESENT_BIN, { + { MSR1(0), "Interrupt on counter overflow is disabled" }, + { MSR1(1), "Interrupt on counter overflow is enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "PC", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled pin control" }, + { MSR1(1), "Enabled pin control" }, + { BITVAL_EOT } + }}, + { 18, 1, "Edge", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled edge detection" }, + { MSR1(1), "Enabled edge detection" }, + { BITVAL_EOT } + }}, + { 17, 1, "OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is ring 0" }, + { BITVAL_EOT } + }}, + { 16, 1, "USR", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is not ring 0" }, + { BITVAL_EOT } + }}, + { 15, 8, "UMask", "R/W", PRESENT_HEX, { + /* Qualifies the microarchitectural condition + * to detect on the selected event logic. */ + { BITVAL_EOT } + }}, + { 7, 8, "Event Select", "R/W", PRESENT_HEX, { + /* Selects a performance event logic unit. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { 63, 8, "Lowest Supported Clock Ratio", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 55, 8, "Lowest Supported Voltage", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 47, 8, "Highest Supported Clock Ratio", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 8, "Highest Supported Voltage", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 8, "Lowest Clock Ratio", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 2, "Performance Control MSR Transition", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 18, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 17, 1, "Voltage Transition in progress", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 16, 1, "Clock Ratio Transition in progress", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 15, 8, "Current Clock Ratio", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 8, "16*x + 700 = Current voltage in mV", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { 63, 48, RESERVED }, + { 15, 8, "Desired Clock Ratio", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 8, "16*x + 700 = Desired voltage in mV", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { 63, 59, RESERVED }, + { 15, 8, "allows selection of the on-demand clock modulation duty cycle", "R/W", PRESENT_BIN, { + { MSR1(0), "Reserved" }, + { MSR1(1), "12.5%" }, + { MSR1(2), "25.0%" }, + { MSR1(3), "37.5%" }, + { MSR1(4), "50.0%" }, + { MSR1(5), "62.5%" }, + { MSR1(6), "75.0%" }, + { MSR1(7), "87.5%" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { 63, 62, RESERVED }, + { 1, 1, "Enables APIC LVT interrupt on a low-to-high temp transition", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 0, 1, "Enables APIC LVT interrupt on a high-to-low temp transition", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { 63, 62, RESERVED }, + { 1, 1, "TCC assert detect", "R/O", PRESENT_BIN, { + { MSR1(0), "TCC not asserted" }, + { MSR1(1), "TCC asserted" }, + { BITVAL_EOT } + }}, + { 0, 1, "TCC trigger detect (Sticky bit, only cleared upon reset)", "R/O", PRESENT_BIN, { + { MSR1(0), "TCC not triggered" }, + { MSR1(1), "TCC triggered" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { 63, 47, RESERVED }, + { 16, 1, "Thermal Monitor enable", "R/W", PRESENT_HEX, { + { MSR1(0), "Thermal Monitor 1 enabled" }, + { MSR1(1), "Thermal Monitor 2 enabled" }, + { BITVAL_EOT } + }}, + { 15, 8, "Thermal Monitor 2 performance state clock ratio", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 8, "Thermal Monitor 2 performance state volatege", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + { 63, 43, RESERVED }, + { 20, 1, "PowerSaver lock", "R/W", PRESENT_BIN, { + { MSR1(0), "Bit 16 can be set and cleared." }, + { MSR1(1), "Bit 16 can only be cleared upon reset." }, + { BITVAL_EOT } + }}, + { 19, 3, RESERVED }, + { 16, 1, "Enhanced PowerSaver enable", "R/W", PRESENT_BIN, { + { MSR1(0), "Performance state changes disabled" }, + { MSR1(1), "Performance state changes enabled" }, + { BITVAL_EOT } + }}, + { 15, 5, RESERVED }, + { 10, 1, "PBE enable", "R/W", PRESENT_BIN, { + { MSR1(0), "FERR# legacy mode" }, + { MSR1(1), "Enables break events for APIC via FERR#" }, + { BITVAL_EOT } + }}, + { 9, 6, RESERVED }, + { 3, 1, "Thermal Monitor 2 enable", "R/W", PRESENT_BIN, { + { MSR1(0), "On-die clock throttling enabled" }, + { MSR1(1), "Thermal Monitor 1 or 2 enabled" }, + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x1107, MSRTYPE_RDWR, MSR2(0,0), "FCR", + "Feature Control Register", { + { 63, 55, RESERVED }, + { 8, 1, "Disables L2 Cache", "R/W", PRESENT_BIN, { + { MSR1(0), "L2 Cache enabled" }, + { MSR1(1), "L2 Cache disabled" }, + { BITVAL_EOT } + }}, + { 7, 6, RESERVED }, + { 1, 1, "Enables CPUID reporting CMPXCHG8B", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled CPUID reporting CMPXCHG8B" }, + { MSR1(1), "Enabled CPUID reporting CMPXCHG8B" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x1108, MSRTYPE_RDWR, MSR2(0,0), "FCR2", + "Feature Control Register 2", { + { 63, 32, "Last 4 characters of Alternate Vendor ID string", "R/W", PRESENT_STR, { + { BITVAL_EOT } + }}, + { 31, 17, RESERVED }, + { 14, 1, "Use the Alternate Vendor ID string", "R/W", PRESENT_BIN, { + { MSR1(0), "The CPUID instruction vendor ID is CentaurHauls" }, + { MSR1(1), "The CPUID instruction returns the alternate Vendor ID" }, + { BITVAL_EOT } + }}, + { 13, 2, RESERVED }, + { 11, 4, "Family ID", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 4, "Model ID", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 3, 4, RESERVED }, + { BITS_EOT } + }}, + {0x1109, MSRTYPE_WRONLY, MSR2(0,0), "FCR3", + "Feature Control Register 3", { + { 63, 32, "First 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { + { BITVAL_EOT } + }}, + { 31, 32, "Middle 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1152, MSRTYPE_RDONLY, MSR2(0,0), "FUSES", "Fuses", { + { BITS_EOT } + }}, + {0x1153, MSRTYPE_RDONLY, MSR2(0,0), "BRAND", + "BRAND_1 XOR BRAND_2, (00b = C7-M, 01b = C7, 10b = Eden, 11b = Reserved)", { + { 63, 42, RESERVED }, + { 21, 2, "BRAND_1", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 2, "BRAND_2", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 17, 18, RESERVED }, + { BITS_EOT } + }}, + {0x1160, MSRTYPE_RDWR, MSR2(0,0), "UNK0", "", { + { BITS_EOT } + }}, + {0x1161, MSRTYPE_RDWR, MSR2(0,0), "UNK1", "", { + { BITS_EOT } + }}, + {0x1164, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_LOW", "(FUSES[6:4] * 5 + 65)", { + { BITS_EOT } + }}, + {0x1165, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_HI", "(FUSES[6:4] * 5 + 65) + 5", { + { BITS_EOT } + }}, + {0x1166, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_OVERSTRESS", "", { + { BITS_EOT } + }}, + {0x1167, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_USER_TRIP", "", { + { BITS_EOT } + }}, + {0x1168, MSRTYPE_RDWR, MSR2(0,0), "UNK2", "", { + { BITS_EOT } + }}, + {0x116a, MSRTYPE_RDWR, MSR2(0,0), "UNK3", "", { + { BITS_EOT } + }}, + {0x116b, MSRTYPE_RDWR, MSR2(0,0), "UNK4", "", { + { BITS_EOT } + }}, + { MSR_EOT } +};

1 0

New patch to review for coreboot: msrtool: add support for printing string values
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18257 -gerrit commit 0c1b46f062cd826bbe38d0ed0a202ee534c32e30 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:19:33 2017 +0100 msrtool: add support for printing string values The VIA CPUs allow setting the CPUID vendor, which is best read as a character string. Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/msrtool.h | 4 +++- util/msrtool/msrutils.c | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 6565fff..7e85dc0 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -45,7 +45,8 @@ enum { PRESENT_BIN, PRESENT_OCT, PRESENT_HEX, - PRESENT_HEXDEC + PRESENT_HEXDEC, + PRESENT_STR, } PresentTypes; struct msr { @@ -162,6 +163,7 @@ struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); /* msrutils.c */ void hexprint(FILE *f, const struct msr val, const uint8_t bits); +void strprint(FILE *f, const struct msr val, const uint8_t bits); int msr_eq(const struct msr a, const struct msr b); struct msr msr_shl(const struct msr a, const uint8_t bits); struct msr msr_shr(const struct msr a, const uint8_t bits); diff --git a/util/msrtool/msrutils.c b/util/msrtool/msrutils.c index 57a271d..471ed29 100644 --- a/util/msrtool/msrutils.c +++ b/util/msrtool/msrutils.c @@ -65,6 +65,9 @@ static void print_bitval(FILE *f, const struct msrbits *mb, const struct msr val hexprint(f, val, mb->size); fprintf(f, " %d", val.lo); break; + case PRESENT_STR: + strprint(f, val, mb->size); + break; } if (mbv->text) fprintf(f, ": %s", mbv->text); @@ -106,6 +109,25 @@ void hexprint(FILE *f, const struct msr val, const uint8_t bits) { fprintf(f, "0x%08x%08x", val.hi, val.lo); } +void strprint(FILE *f, const struct msr val, const uint8_t bits) { + if (bits >= 64) + fputc(val.hi, f); + if (bits >= 56) + fputc(val.hi >> 8, f); + if (bits >= 48) + fputc(val.hi >> 16, f); + if (bits >= 40) + fputc(val.hi >> 24, f); + if (bits >= 32) + fputc(val.lo, f); + if (bits >= 24) + fputc(val.lo >> 8, f); + if (bits >= 16) + fputc(val.lo >> 16, f); + if (bits >= 8) + fputc(val.lo >> 24, f); +} + int msr_eq(const struct msr a, const struct msr b) { return a.hi == b.hi && a.lo == b.lo; }

1 0

New patch to review for coreboot: mstrool: only use intel targets for actual intel CPUs
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18256 -gerrit commit b1a9f4fd8333b54260bf141faa4dac24be427935 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:19:24 2017 +0100 mstrool: only use intel targets for actual intel CPUs VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite Pentium III. Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/intel_atom.c | 5 +++-- util/msrtool/intel_core1.c | 4 +++- util/msrtool/intel_core2_early.c | 4 +++- util/msrtool/intel_core2_later.c | 4 +++- util/msrtool/intel_nehalem.c | 3 ++- util/msrtool/intel_pentium3.c | 3 ++- util/msrtool/intel_pentium3_early.c | 3 ++- util/msrtool/intel_pentium4_early.c | 4 +++- util/msrtool/intel_pentium4_later.c | 3 ++- 9 files changed, 23 insertions(+), 10 deletions(-) diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index c055f4c..2d89c9c 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -16,8 +16,9 @@ #include "msrtool.h" int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) { - return (0x6 == id->family) && - (0x1c == id->model); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0x1c == id->model)); } const struct msrdef intel_atom_msrs[] = { diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c index ef2b660..039a2f8 100644 --- a/util/msrtool/intel_core1.c +++ b/util/msrtool/intel_core1.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_core1_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && (0xe == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0xe == id->model)); } const struct msrdef intel_core1_msrs[] = { diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c index a9b742f..1072624 100644 --- a/util/msrtool/intel_core2_early.c +++ b/util/msrtool/intel_core2_early.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && (0xf == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0xf == id->model)); } const struct msrdef intel_core2_early_msrs[] = { diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 3cb28c6..ad353eb 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_core2_later_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family)&(0x17 == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && + (0x17 == id->model)); } const struct msrdef intel_core2_later_msrs[] = { diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index c133653..679efb5 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_nehalem_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && ( (0x1a == id->model) || (0x1e == id->model) || (0x1f == id->model) || diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c index 456963f..6b12428 100644 --- a/util/msrtool/intel_pentium3.c +++ b/util/msrtool/intel_pentium3.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_pentium3_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && ( (0xa == id->model) || (0xb == id->model) )); diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c index 925b24f..afdc62e 100644 --- a/util/msrtool/intel_pentium3_early.c +++ b/util/msrtool/intel_pentium3_early.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_pentium3_early_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0x6 == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0x6 == id->family) && ( (0x7 == id->model) || (0x8 == id->model) )); diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c index 537d9e3..649be04 100644 --- a/util/msrtool/intel_pentium4_early.c +++ b/util/msrtool/intel_pentium4_early.c @@ -16,7 +16,9 @@ #include "msrtool.h" int intel_pentium4_early_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0xf == id->family) && (0x2 == id->model)); + return ((VENDOR_INTEL == id->vendor) && + (0xf == id->family) && + (0x2 == id->model)); } const struct msrdef intel_pentium4_early_msrs[] = { diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c index cc85f65..5444161 100644 --- a/util/msrtool/intel_pentium4_later.c +++ b/util/msrtool/intel_pentium4_later.c @@ -16,7 +16,8 @@ #include "msrtool.h" int intel_pentium4_later_probe(const struct targetdef *target, const struct cpuid_t *id) { - return ((0xf == id->family) && ( + return ((VENDOR_INTEL == id->vendor) && + (0xf == id->family) && ( (0x3 == id->model) || (0x4 == id->model) ));

1 0

New patch to review for coreboot: msrtool: use a bit more clever cpuid vendor match
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18255 -gerrit commit 8a4d9964378ccae662166e0526af6a10ac608bb2 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:19:21 2017 +0100 msrtool: use a bit more clever cpuid vendor match Not everyting non-intel is AMD. Change-Id: I06d6fbaa0b4f2c9e61d9b3b4aeeb349a91aa090e Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/msrtool.h | 4 ++-- util/msrtool/sys.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index fe7f0f0..6565fff 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -94,8 +94,8 @@ struct msrdef { #define MAX_CORES 8 typedef enum { - VENDOR_INTEL = 1, - VENDOR_AMD = 2, + VENDOR_INTEL = 0x756e6547, + VENDOR_AMD = 0x68747541, } vendor_t; struct cpuid_t { diff --git a/util/msrtool/sys.c b/util/msrtool/sys.c index cb300d9..f80d067 100644 --- a/util/msrtool/sys.c +++ b/util/msrtool/sys.c @@ -36,7 +36,7 @@ struct cpuid_t *cpuid(void) { asm ("cpuid" : "=b" (outebx) : "a" (0) : "%ecx", "%edx"); #endif - id.vendor = (outebx == 0x756e6547) ? VENDOR_INTEL : VENDOR_AMD; + id.vendor = outebx; /* Then, identificate CPU itself */ #if defined(__DARWIN__) && !defined(__LP64__)

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New patch to review for coreboot: device/dram: use global DIMM_SPD_SIZE Kconfig variable
by Patrick Georgi 28 Jan '17

28 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18254 -gerrit commit 1fcf72bf578e1990c1e1057ea6cbe9d5ee1c7eee Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 13:12:09 2017 +0100 device/dram: use global DIMM_SPD_SIZE Kconfig variable Also make sure that no board changes behaviour because of that by adding a static assert. TEST=abuild over all builds still succeeds (where it doesn't if DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the device/dram code). Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/dram/spd_cache.c | 10 ++++++---- src/mainboard/amd/db-ft3b-lc/Kconfig | 4 ++++ src/mainboard/bap/ode_e20XX/Kconfig | 4 ++++ src/mainboard/bap/ode_e21XX/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo2/Kconfig | 4 ++++ src/mainboard/pcengines/apu1/Kconfig | 4 ++++ src/mainboard/pcengines/apu2/Kconfig | 4 ++++ 8 files changed, 34 insertions(+), 4 deletions(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index c7dd97d..3bdd9c1 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -25,11 +25,13 @@ #define SPD_CRC_HI 127 #define SPD_CRC_LO 126 +_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); + int read_spd_from_cbfs(u8 *buf, int idx) { const char *spd_file; size_t spd_file_len = 0; - size_t min_len = (idx + 1) * SPD_SIZE; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); @@ -40,9 +42,9 @@ int read_spd_from_cbfs(u8 *buf, int idx) if (!spd_file || spd_file_len < min_len) return -1; - memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); - u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) || (buf[SPD_CRC_LO] != (crc & 0xff)) @@ -53,7 +55,7 @@ int read_spd_from_cbfs(u8 *buf, int idx) buf[SPD_CRC_HI] = crc >> 8; u16 i; printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { if((i % 16) == 0x00) printk(BIOS_WARNING, "\n%02x: ", i); printk(BIOS_WARNING, "%02x ", buf[i]); diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index ace741d..7bf3c86 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -53,4 +53,8 @@ config HUDSON_LEGACY_FREE bool default y +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_AMD_DB_FT3B_LC diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ad1c3de..ee26772 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -80,4 +80,8 @@ config BAP_E20_DDR3_1066 endchoice +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index b356749..60a59ac 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -74,4 +74,8 @@ config BAP_E21_DDR3_1333 endchoice +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_ODE_E21XX diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 0c78f79..8109019 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -70,4 +70,8 @@ config SB800_AHCI_ROM bool default n +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_GIZMOSPHERE_GIZMO diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 55beca6..349f827 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -61,4 +61,8 @@ config HUDSON_LEGACY_FREE bool default y +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_GIZMOSPHERE_GIZMO2 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3099d14..f882b78 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -116,4 +116,8 @@ endchoice config UART_D_RS485 bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 0acf416..de42721 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -88,4 +88,8 @@ config APU2_PINMUX_UART_D endchoice +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_PCENGINES_APU2

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Patch set updated for coreboot: mb/lenovo/t400: Implement hybrid graphic in romstage
by Arthur Heymans 28 Jan '17

28 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18010 -gerrit commit d26c1b4cbdc5878dd3b0bf83354c95d4da5fe6d8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 2 16:16:45 2017 +0100 mb/lenovo/t400: Implement hybrid graphic in romstage The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work for t400/t500. Replace it with a custom romstage implementation. Tested on Lenovo T500 with dual graphics: * Intel Native GFX init * AMD VBios * GNU Linux 4.8.13 * SeaBios as payload * Integrated is working (24 W) ** Seems to always run at 100% * Discrete is working (44 W) ** Seems to always run at 100% * Switchable is working (34 W) ** Both GPUs are enabled, with Intel being connected to the panel ** DRI_PRIME allows to use AMD GPU ** ACPI doesn't seem to work (no vgaswitcheroo) Depends on Change-Id: I03578d358f31b605f300a67f5b078eff834e070c Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Depends on Change-Id: Ia3c1516c54c28bbe5a127153912c9682e975bea2 Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/Kconfig | 1 - src/mainboard/lenovo/t400/Makefile.inc | 1 + src/mainboard/lenovo/t400/cmos.layout | 1 + src/mainboard/lenovo/t400/hybrid_graphics.c | 87 +++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/romstage.c | 11 +++- 5 files changed, 98 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f21f672..150199e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b382efb..c02a70b 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -15,3 +15,4 @@ ramstage-y += dock.c ramstage-y += cstates.c +romstage-y += hybrid_graphics.c diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..cf31453 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -142,6 +142,7 @@ enumerations 11 12 352M 12 0 Integrated Only 12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/hybrid_graphics.c b/src/mainboard/lenovo/t400/hybrid_graphics.c new file mode 100644 index 0000000..0c2b02a --- /dev/null +++ b/src/mainboard/lenovo/t400/hybrid_graphics.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/gm45/gm45.h> +#include <console/console.h> +#include <option.h> + +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define MUX_GPIO 22 +#define BCL_CTL_GPIO 19 +#define GFX_PWR_EN_GPIO 49 + +#define HYBRID_DETECT_GPIO 21 + +void hybrid_graphics_init(sysinfo_t *sysinfo); + +static bool hybrid_graphics_installed(void) +{ + if (get_gpio(HYBRID_DETECT_GPIO)) + return false; + else + return true; +} + +void hybrid_graphics_init(sysinfo_t *sysinfo) +{ + /* Set default mode */ + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + + if (hybrid_graphics_installed()) { + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available.\n"); + } else { + printk(BIOS_DEBUG, "Hybrid graphics not installed.\n"); + return; + } + + /* Select appropriate hybrid graphics device */ + switch (hybrid_graphics_mode) { + case HYBRID_GRAPHICS_DISCRETE_ONLY: + printk(BIOS_DEBUG, "Activating Discrete Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_HIGH); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_HIGH); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + break; + case HYBRID_GRAPHICS_SWITCHABLE: + printk(BIOS_DEBUG, "Activating Switchable.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 1; + break; + case HYBRID_GRAPHICS_INTEGRATED_ONLY: + default: + printk(BIOS_DEBUG, "Activating Integrated Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_LOW); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + break; + + } +} diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 013d22c..5a666cd 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -36,6 +36,8 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +void hybrid_graphics_init(sysinfo_t *sysinfo); + static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -101,8 +103,6 @@ void mainboard_romstage_entry(unsigned long bist) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); @@ -112,6 +112,13 @@ void mainboard_romstage_entry(unsigned long bist) deven |= 2; pci_write_config32(MCH_DEV, D0F0_DEVEN, deven); + /* Configure graphic GPIOs. + * Make sure there's a little delay between + * setup_pch_gpios() and this call ! */ + sysinfo.enable_igd = 1; + sysinfo.enable_peg = 0; + hybrid_graphics_init(&sysinfo); + raminit(&sysinfo, s3resume); init_pm(&sysinfo, 0);

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New patch to review for coreboot: apollolake: remove NHLT DMIC-1ch configuration
by Sathyanarayana Nujella 28 Jan '17

28 Jan '17

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18252 -gerrit commit b2e36fbb4010765350516ea5463960e3b4a61ae2 Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Fri Jan 27 14:51:59 2017 -0800 apollolake: remove NHLT DMIC-1ch configuration Apollolake boards should use DMIC-4ch configuration in Kernel side and use CaptureChannelMap in userspace to distinguish boards with different number of DMIC's. So, NHLT DMIC-1ch endpoint configuration will not be required and hence removed. BUG=chrome-os-partner:60827 TEST=Verify internal mic capture Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/Kconfig | 1 - .../google/reef/variants/baseboard/nhlt.c | 3 -- src/soc/intel/apollolake/Kconfig | 7 ----- src/soc/intel/apollolake/Makefile.inc | 5 ---- src/soc/intel/apollolake/nhlt.c | 35 ---------------------- 5 files changed, 51 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 1ef2e88..c9f1590 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -99,7 +99,6 @@ config UART_FOR_CONSOLE config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." - select NHLT_DMIC_1CH_16B select NHLT_DMIC_2CH_16B select NHLT_DMIC_4CH_16B select NHLT_DA7219 diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index d44d599..f6b1362 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -22,9 +22,6 @@ void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) { - /* 1-dmic configuration */ - if (!nhlt_soc_add_dmic_array(nhlt, 1)) - printk(BIOS_ERR, "Added 1CH DMIC array.\n"); /* 2-dmic configuration */ if (!nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b37cde6..9391ccf 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -217,13 +217,6 @@ config HEAP_SIZE hex default 0x8000 -config NHLT_DMIC_1CH_16B - bool - depends on ACPI_NHLT - default n - help - Include DSP firmware settings for 1 channel 16B DMIC array. - config NHLT_DMIC_2CH_16B bool depends on ACPI_NHLT diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5a65f43..3eb5a04 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -140,16 +140,11 @@ endif # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs -DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin -cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B) -$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B) -$(DMIC_1CH_48KHZ_16B)-type := raw - cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-type := raw diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index b43a34e..2ac7908 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -18,38 +18,6 @@ #include <nhlt.h> #include <soc/nhlt.h> -static const struct nhlt_format_config dmic_1ch_formats[] = { - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 1, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .settings_file = "dmic-1ch-48khz-16b.bin", - }, -}; - -static const struct nhlt_dmic_array_config dmic_1ch_mic_config = { - .tdm_config = { - .config_type = NHLT_TDM_MIC_ARRAY, - }, - .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED, -}; - -static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = { - { - .link = NHLT_LINK_PDM, - .device = NHLT_PDM_DEV, - .direction = NHLT_DIR_CAPTURE, - .vid = NHLT_VID, - .did = NHLT_DID_DMIC, - .cfg = &dmic_1ch_mic_config, - .cfg_size = sizeof(dmic_1ch_mic_config), - .formats = dmic_1ch_formats, - .num_formats = ARRAY_SIZE(dmic_1ch_formats), - }, -}; - static const struct nhlt_format_config dmic_2ch_formats[] = { /* 48 KHz 16-bits per sample. */ { @@ -183,9 +151,6 @@ static const struct nhlt_endp_descriptor max98357_descriptors[] = { int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) { switch (num_channels) { - case 1: - return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors, - ARRAY_SIZE(dmic_1ch_descriptors)); case 2: return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, ARRAY_SIZE(dmic_2ch_descriptors));

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coreboot-gerrit January 2017