coreboot-gerrit January 2017

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Patch set updated for coreboot: sb/intel/common: Hook up me_cleaner
by Nicola Corna 29 Jan '17

29 Jan '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18206 -gerrit commit 3618b27a3a2248d126c5d767b47244dd3a670319 Author: Nicola Corna <nicola(a)corna.info> Date: Mon Jan 23 15:29:03 2017 +0100 sb/intel/common: Hook up me_cleaner The me_cleaner option is available on multiple platforms: * Sandy and Ivy Bridge (well tested by multiple users). * Skylake and Braswell (tested). * Haswell, Broadwell and Bay Trail (untested). The untested platforms have been included anyways because all the firmwares are very similar and Intel ME/TXE probably behaves in the same way. Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/southbridge/intel/common/firmware/Kconfig | 31 ++++++++++++++++++++++ src/southbridge/intel/common/firmware/Makefile.inc | 5 ++++ 2 files changed, 36 insertions(+) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index c36b235..af26b2d 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -58,6 +58,37 @@ config ME_BIN_PATH default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" depends on HAVE_ME_BIN +config USE_ME_CLEANER + bool "Strip down the Intel ME/TXE firmware" + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_SANDYBRIDGE || \ + NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ + SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) + help + Use me_cleaner to remove all the non-fundamental code from the Intel + ME/TXE firmware. + The resulting Intel ME/TXE firmware will have only the code + responsible for the very basic hardware initialization, leaving the + ME/TXE subsystem essentially in a disabled state. + + Don't flash a modified ME/TXE firmware and a new coreboot image at the + same time, test them in two different steps. + + WARNING: this tool isn't based on any official Intel documentation but + only on reverse engineering and trial & error. + + See the project's page + https://github.com/corna/me_cleaner + or the wiki + https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F + https://github.com/corna/me_cleaner/wiki/me_cleaner-status + for more info about this tool + + If unsure, say N. + +comment "Please test the modified ME/TXE firmware and coreboot in two steps" + depends on USE_ME_CLEANER + config HAVE_GBE_BIN bool "Add gigabit ethernet firmware" depends on HAVE_IFD_BIN diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 17e53b5..98a36d3 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -58,6 +58,11 @@ ifeq ($(CONFIG_HAVE_ME_BIN),y) $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif +ifeq ($(CONFIG_USE_ME_CLEANER),y) + printf " ME_CLEANER coreboot.pre\n" + util/me_cleaner/me_cleaner.py $(obj)/coreboot.pre > \ + $(obj)/me_cleaner.log +endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) printf " IFDTOOL gbe.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \

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Patch set updated for coreboot: mb/lenovo/t400: Implement hybrid graphic in romstage
by Patrick Rudolph 29 Jan '17

29 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18010 -gerrit commit 29867964c8663c3d0d5db43e662104716e24ac94 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 2 16:16:45 2017 +0100 mb/lenovo/t400: Implement hybrid graphic in romstage The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work for t400/t500. Replace it with a custom romstage implementation. Tested on Lenovo T500 with dual graphics: * Intel Native GFX init * AMD VBios * GNU Linux 4.8.13 * SeaBios as payload * Discrete is working (44 W) * Integrated is working (24 W) * Switchable is working (34 W) ** Both GPUs are enabled, with Intel being connected to the panel ** DRI_PRIME allows to use AMD GPU ** ACPI doesn't seem to work (no vgaswitcheroo) Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/Kconfig | 1 - src/mainboard/lenovo/t400/Makefile.inc | 1 + src/mainboard/lenovo/t400/cmos.layout | 1 + src/mainboard/lenovo/t400/hybrid_graphics.c | 89 +++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/romstage.c | 10 +++- 5 files changed, 99 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f21f672..150199e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b382efb..c02a70b 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -15,3 +15,4 @@ ramstage-y += dock.c ramstage-y += cstates.c +romstage-y += hybrid_graphics.c diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..cf31453 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -142,6 +142,7 @@ enumerations 11 12 352M 12 0 Integrated Only 12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/hybrid_graphics.c b/src/mainboard/lenovo/t400/hybrid_graphics.c new file mode 100644 index 0000000..dea986e --- /dev/null +++ b/src/mainboard/lenovo/t400/hybrid_graphics.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/gm45/gm45.h> +#include <console/console.h> +#include <option.h> + +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define MUX_GPIO 22 +#define BCL_CTL_GPIO 19 +#define GFX_PWR_EN_GPIO 49 + +#define HYBRID_DETECT_GPIO 21 + +void hybrid_graphics_init(sysinfo_t *sysinfo); + +static bool hybrid_graphics_installed(void) +{ + if (get_gpio(HYBRID_DETECT_GPIO)) + return false; + else + return true; +} + +void hybrid_graphics_init(sysinfo_t *sysinfo) +{ + /* Set default mode */ + uint8_t hybrid_graphics_mode = 0xff; + + if (hybrid_graphics_installed()) { + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available: "); + } else + printk(BIOS_DEBUG, "Hybrid graphics not installed.\n"); + + /* Select appropriate hybrid graphics device */ + switch (hybrid_graphics_mode) { + case HYBRID_GRAPHICS_INTEGRATED_ONLY: + printk(BIOS_DEBUG, "Activating Integrated Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_LOW); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + break; + case HYBRID_GRAPHICS_DISCRETE_ONLY: + printk(BIOS_DEBUG, "Activating Discrete Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_HIGH); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_HIGH); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + break; + case HYBRID_GRAPHICS_SWITCHABLE: + printk(BIOS_DEBUG, "Activating Switchable (both GPUs).\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 1; + break; + default: + /* The display is not connected to a mux or switchable. */ + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + break; + } +} diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index d110d4f..2a3a770 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -36,6 +36,8 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +void hybrid_graphics_init(sysinfo_t *sysinfo); + static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -101,9 +103,13 @@ void mainboard_romstage_entry(unsigned long bist) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); + + /* Configure graphic GPIOs. + * Make sure there's a little delay between + * setup_pch_gpios() and this call ! */ + hybrid_graphics_init(&sysinfo); + raminit(&sysinfo, s3resume); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);

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Patch set updated for coreboot: nb/intel/gm45/igd: Hide IGD while disabling
by Patrick Rudolph 29 Jan '17

29 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18194 -gerrit commit 6608f52a89001a82293a37af051d0fa5ff608ce4 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:43:52 2017 +0100 nb/intel/gm45/igd: Hide IGD while disabling Hide the IGD to make sure ramstage doesn't detect it. Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/gm45/igd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 74572ca..1164339 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -127,6 +127,11 @@ static void disable_igd(const sysinfo_t *const sysinfo) MCHBAR16(0x119e) = (MCHBAR16(0x119e) & ~(7 << 13)) | (4 << 13); MCHBAR16(0x119e) |= (1 << 12); } + + /* Hide IGD. */ + u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN); + deven &= ~(3 << 3); + pci_write_config32(mch_dev, D0F0_DEVEN, deven); } void init_igd(const sysinfo_t *const sysinfo)

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Patch set updated for coreboot: x86/acpi: Add VFCT table
by Patrick Rudolph 29 Jan '17

29 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18192 -gerrit commit 480bf0acf8f980062304ac0a29dad68faae7003e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 20:04:23 2016 +0200 x86/acpi: Add VFCT table Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 --- src/arch/x86/acpi.c | 25 ++++++++++++++++ src/arch/x86/include/arch/acpi.h | 29 ++++++++++++++++++ src/device/pci_device.c | 3 ++ src/device/pci_rom.c | 65 ++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 7 +++++ 5 files changed, 129 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 53c4135..703bfa1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -589,6 +589,31 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)) +{ + acpi_header_t *header = &(vfct->header); + unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + + memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + + /* Fill out header fields. */ + memcpy(header->signature, "VFCT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(struct acpi_vfct); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_vfct(device, vfct, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)vfct; + header->checksum = acpi_checksum((void *)vfct, header->length); +} + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6854573..9dfbe2f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -220,6 +220,30 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; +/* VFCT image header */ +struct acpi_vfct_image_hdr { + u32 PCIBus; + u32 PCIDevice; + u32 PCIFunction; + u16 VendorID; + u16 DeviceID; + u16 SSVID; + u16 SSID; + u32 Revision; + u32 ImageLength; + u8 VbiosContent; // dummy - copy VBIOS here +} __attribute__ ((packed)); + +/* VFCT (VBIOS Fetch Table) */ +struct acpi_vfct { + struct acpi_table_header header; + u8 TableUUID[16]; + u32 VBIOSImageOffset; + u32 Lib1ImageOffset; + u32 Reserved[4]; + struct acpi_vfct_image_hdr image_hdr; +} __attribute__ ((packed)); + typedef struct acpi_ivrs_info { } __attribute__ ((packed)) acpi_ivrs_info_t; @@ -601,6 +625,11 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, + struct acpi_vfct *vfct_struct, unsigned long current)); + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 06294d0..b2e3c9a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -735,6 +735,9 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = pci_rom_write_acpi_tables, +#endif .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 8366fea..20621d3 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -169,3 +169,68 @@ struct rom_header *pci_rom_load(struct device *dev, pci_ram_image_start += rom_size; return (struct rom_header *) (pci_ram_image_start-rom_size); } + +/* ACPI */ +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static unsigned long +pci_rom_acpi_fill_vfct(struct device *device, + struct acpi_vfct *vfct_struct, + unsigned long current) +{ + struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + struct rom_header *rom; + + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + + rom = pci_rom_probe(device); + if (!rom) { + printk(BIOS_ERR, "pci_rom_acpi_fill_vfct failed\n"); + return current; + } + + header->DeviceID = device->device; + header->VendorID = device->vendor; + header->PCIBus = device->bus->secondary; + header->PCIFunction = PCI_FUNC(device->path.pci.devfn); + header->PCIDevice = PCI_SLOT(device->path.pci.devfn); + header->ImageLength = rom->size * 512; + memcpy((void *)&header->VbiosContent, rom, header->ImageLength); + + current += header->ImageLength; + return current; +} + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_vfct *vfct; + struct rom_header *rom; + + /* Only handle VGA devices */ + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + return current; + + /* Only handle enabled devices */ + if (!device->enabled) + return current; + + /* Probe for option rom */ + rom = pci_rom_probe(device); + if (!rom) + return current; + + /* AMD/ATI uses VFCT */ + if (device->vendor == PCI_VENDOR_ID_ATI) { + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + vfct = (struct acpi_vfct *)current; + acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } + + return current; +} +#endif diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 2fb2f7a..3f09778 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,6 +2,7 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) @@ -35,6 +36,12 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); + u32 map_oprom_vendev(u32 vendev); #endif

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Patch set updated for coreboot: [WIP] mainboards/hp: Add HP Elitebook 2760p
by Iru Cai 29 Jan '17

29 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18241 -gerrit commit a72852127a87e7713eb0185b4061b39bc8264250 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Jan 26 14:51:47 2017 +0800 [WIP] mainboards/hp: Add HP Elitebook 2760p The code is generated by autoport. The flash chip is socketed beside the WLAN slot. The EHCI debug port is on right side of the laptop beside the RJ11 connector. Things that work: - memory: 0+8G, 4G+8G - Linux (Linux Mint 18.1 with Linux 4.4) - native graphics init + SeaBIOS payload with SeaVGABIOS - all 3 USB ports - WLAN - S3 suspend and resume - internal flashing after IFD is unlocked and coreboot is flashed Things that don't work: - keyboard (use a USB keyboard instead) - AC and battery status - wacom digitizer - fan control (fan always runs on full speed) Things that are not tested: - WWAN - SD card reader - smart card reader - expresscard - cable modem (EC) blobs: This laptop uses SMSC KBC1126-NU as EC. It may need some blobs in the flash chip. - There may be some data needed by EC at 0x7ff700-0x7fff07, which needs to be copied from the factory firmware. - Range 0x780000-0x78fb8f of the flash chip may contain EC firmware (it has strings like `8051 Reset', and modifying it can brick the machine), so now I set the default CBFS size to 0x70000. Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/hp/2760p/Kconfig | 74 ++++++ src/mainboard/hp/2760p/Kconfig.name | 2 + src/mainboard/hp/2760p/Makefile.inc | 2 + src/mainboard/hp/2760p/acpi/ec.asl | 7 + src/mainboard/hp/2760p/acpi/platform.asl | 10 + src/mainboard/hp/2760p/acpi/superio.asl | 1 + src/mainboard/hp/2760p/acpi_tables.c | 1 + src/mainboard/hp/2760p/board_info.txt | 6 + src/mainboard/hp/2760p/devicetree.cb | 111 ++++++++ src/mainboard/hp/2760p/dsdt.asl | 30 +++ src/mainboard/hp/2760p/gnvs.c | 19 ++ src/mainboard/hp/2760p/gpio.c | 433 +++++++++++++++++++++++++++++++ src/mainboard/hp/2760p/hda_verb.c | 65 +++++ src/mainboard/hp/2760p/mainboard.c | 25 ++ src/mainboard/hp/2760p/romstage.c | 66 +++++ 15 files changed, 852 insertions(+) diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig new file mode 100644 index 0000000..75f7933 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig @@ -0,0 +1,74 @@ +if BOARD_HP_2760P + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/2760p + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook 2760p" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x162a + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config CBFS_SIZE + hex + default 0x70000 + +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0x8f0 + +endif diff --git a/src/mainboard/hp/2760p/Kconfig.name b/src/mainboard/hp/2760p/Kconfig.name new file mode 100644 index 0000000..4a6a8e5 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_2760P + bool "HP EliteBook 2760p" diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc new file mode 100644 index 0000000..c55eebe --- /dev/null +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/hp/2760p/acpi/ec.asl b/src/mainboard/hp/2760p/acpi/ec.asl new file mode 100644 index 0000000..aea3c58 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 22) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/platform.asl b/src/mainboard/hp/2760p/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/superio.asl b/src/mainboard/hp/2760p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/2760p/acpi_tables.c b/src/mainboard/hp/2760p/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/hp/2760p/board_info.txt b/src/mainboard/hp/2760p/board_info.txt new file mode 100644 index 0000000..ae1ca3b --- /dev/null +++ b/src/mainboard/hp/2760p/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: yes +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb new file mode 100644 index 0000000..34acfaf --- /dev/null +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000129" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x007c0281" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x21" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x162a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x162a + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x162a + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x162a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x162a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x162a + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x162a + end + device pci 1c.3 on # WLAN + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x162a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x162a + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x162a + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x162a + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x162a + end + end +end diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl new file mode 100644 index 0000000..3b7fb7e --- /dev/null +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/hp/2760p/gnvs.c b/src/mainboard/hp/2760p/gnvs.c new file mode 100644 index 0000000..37cd5c9 --- /dev/null +++ b/src/mainboard/hp/2760p/gnvs.c @@ -0,0 +1,19 @@ +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/2760p/gpio.c b/src/mainboard/hp/2760p/gpio.c new file mode 100644 index 0000000..65bff4e --- /dev/null +++ b/src/mainboard/hp/2760p/gpio.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c new file mode 100644 index 0000000..c60846e --- /dev/null +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -0,0 +1,65 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162a, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c162a), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a70130), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x40f000f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + + 0x00000001, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x1, 0x103c3066), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/2760p/mainboard.c b/src/mainboard/hp/2760p/mainboard.c new file mode 100644 index 0000000..5809af5 --- /dev/null +++ b/src/mainboard/hp/2760p/mainboard.c @@ -0,0 +1,25 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; + RCBA32(0x38c0) = 0x00000007; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c new file mode 100644 index 0000000..71f0b4d --- /dev/null +++ b/src/mainboard/hp/2760p/romstage.c @@ -0,0 +1,66 @@ +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0201); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0101); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00fcfe01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x007c0281); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x82000000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x1ff01feb; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 0, 0, 4 }, + { 0, 0, 5 }, + { 1, 1, 5 }, + { 0, 0, 6 }, + { 1, 1, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +}

1 0

Patch set updated for coreboot: [WIP] mainboards/hp: Add HP Elitebook 2760p
by Iru Cai 29 Jan '17

29 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18241 -gerrit commit fe7321057e0bec1b990482aefdd5504e7494cb3f Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Jan 26 14:51:47 2017 +0800 [WIP] mainboards/hp: Add HP Elitebook 2760p The code is generated by autoport. The flash chip is socketed beside the WLAN slot. The EHCI debug port is on right side of the laptop beside the RJ11 connector. Things that work: - memory: 0+8G, 4G+8G - Linux (Linux Mint 18.1 with Linux 4.4) - native graphics init + SeaBIOS payload with SeaVGABIOS - all 3 USB ports - WLAN - S3 suspend and resume - internal flashing after IFD is unlocked and coreboot is flashed Things that don't work: - keyboard (use a USB keyboard instead) - AC and battery status - wacom digitizer - fan control (fan always runs on full speed) Things that are not tested: - WWAN - SD card reader - smart card reader - expresscard - cable modem (EC) blobs: This laptop uses SMSC KBC1126-NU as EC. It may need some blobs in the flash chip. - There may be some data needed by EC at 0x7ff700-0x7fff07, which needs to be copied from the factory firmware. - Range 0x780000-0x78fb8f of the flash chip may contain EC firmware (it has strings like `8051 Reset', and modifying it can brick the machine), so now I set the default CBFS size to 0x70000. Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/hp/2760p/Kconfig | 74 ++++++ src/mainboard/hp/2760p/Kconfig.name | 2 + src/mainboard/hp/2760p/Makefile.inc | 2 + src/mainboard/hp/2760p/acpi/ec.asl | 7 + src/mainboard/hp/2760p/acpi/platform.asl | 10 + src/mainboard/hp/2760p/acpi/superio.asl | 1 + src/mainboard/hp/2760p/acpi_tables.c | 1 + src/mainboard/hp/2760p/board_info.txt | 6 + src/mainboard/hp/2760p/devicetree.cb | 111 ++++++++ src/mainboard/hp/2760p/dsdt.asl | 30 +++ src/mainboard/hp/2760p/gnvs.c | 19 ++ src/mainboard/hp/2760p/gpio.c | 433 +++++++++++++++++++++++++++++++ src/mainboard/hp/2760p/hda_verb.c | 65 +++++ src/mainboard/hp/2760p/mainboard.c | 25 ++ src/mainboard/hp/2760p/romstage.c | 66 +++++ 15 files changed, 852 insertions(+) diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig new file mode 100644 index 0000000..46d920d --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig @@ -0,0 +1,74 @@ +if BOARD_HP_2760P + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/2760p + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook 2760p" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x162a + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config CBFS_SIZE + hex + default 0x7000 + +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0x8f0 + +endif diff --git a/src/mainboard/hp/2760p/Kconfig.name b/src/mainboard/hp/2760p/Kconfig.name new file mode 100644 index 0000000..4a6a8e5 --- /dev/null +++ b/src/mainboard/hp/2760p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_2760P + bool "HP EliteBook 2760p" diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc new file mode 100644 index 0000000..c55eebe --- /dev/null +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/hp/2760p/acpi/ec.asl b/src/mainboard/hp/2760p/acpi/ec.asl new file mode 100644 index 0000000..aea3c58 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 22) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/platform.asl b/src/mainboard/hp/2760p/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/hp/2760p/acpi/superio.asl b/src/mainboard/hp/2760p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/2760p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/2760p/acpi_tables.c b/src/mainboard/hp/2760p/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/hp/2760p/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/hp/2760p/board_info.txt b/src/mainboard/hp/2760p/board_info.txt new file mode 100644 index 0000000..ae1ca3b --- /dev/null +++ b/src/mainboard/hp/2760p/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: yes +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb new file mode 100644 index 0000000..34acfaf --- /dev/null +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000129" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x007c0281" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x21" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x162a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x162a + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x162a + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x162a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x162a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x162a + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x162a + end + device pci 1c.3 on # WLAN + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x162a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x162a + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x162a + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x162a + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x162a + end + end +end diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl new file mode 100644 index 0000000..3b7fb7e --- /dev/null +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/hp/2760p/gnvs.c b/src/mainboard/hp/2760p/gnvs.c new file mode 100644 index 0000000..37cd5c9 --- /dev/null +++ b/src/mainboard/hp/2760p/gnvs.c @@ -0,0 +1,19 @@ +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/2760p/gpio.c b/src/mainboard/hp/2760p/gpio.c new file mode 100644 index 0000000..65bff4e --- /dev/null +++ b/src/mainboard/hp/2760p/gpio.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c new file mode 100644 index 0000000..c60846e --- /dev/null +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -0,0 +1,65 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162a, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c162a), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a70130), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x40f000f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + + 0x00000001, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x1, 0x103c3066), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/2760p/mainboard.c b/src/mainboard/hp/2760p/mainboard.c new file mode 100644 index 0000000..5809af5 --- /dev/null +++ b/src/mainboard/hp/2760p/mainboard.c @@ -0,0 +1,25 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; + RCBA32(0x38c0) = 0x00000007; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c new file mode 100644 index 0000000..71f0b4d --- /dev/null +++ b/src/mainboard/hp/2760p/romstage.c @@ -0,0 +1,66 @@ +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0201); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0101); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00fcfe01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x007c0281); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x82000000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x1ff01feb; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 0, 0, 4 }, + { 0, 0, 5 }, + { 1, 1, 5 }, + { 0, 0, 6 }, + { 1, 1, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +}

1 0

Patch set updated for coreboot: [RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR
by Iru Cai 29 Jan '17

29 Jan '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14208 -gerrit commit fd9ed5335c3fefdcd0934562cebc2312d27e3c6f Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Mar 31 15:32:25 2016 +0800 [RFC] add CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR HP Elitebook 2760p (and some other HP laptops) stores some data which may be used by EC in bootblock region. So some space needs to be reserved before the reset vector. Change-Id: I992d285a1a76883ff7a69445a0ff9efe62dbbd7f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/failover.ld | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6280024..1daddd9 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -181,6 +181,10 @@ config ID_SECTION_OFFSET hex default 0x80 +config RESERVED_SPACE_BEFORE_RESET_VECTOR + hex + default 0xf0 + # 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index e9613d9..a434704 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -50,8 +50,8 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + ROMLOC_MIN = 0xfffffff0 - CONFIG_RESERVED_SPACE_BEFORE_RESET_VECTOR + - (_erom - _rom + 16) - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); /* Post-check proper SIPI vector. */ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),

1 0

Patch merged into coreboot/master: autoport: add missing parameter for pc_keyboard_init()
by gerrit＠coreboot.org 29 Jan '17

29 Jan '17

the following patch was just integrated into master: commit 8bf53a9f4e70760622c0a2e94185bc881bca14d9 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Thu Jan 26 20:33:29 2017 +0800 autoport: add missing parameter for pc_keyboard_init() This fixes the build for the generated code for boards with PS/2 keyboard, since commit 448e386309c updated the pc_keyboard_init() function. Change-Id: I776b49b847985296eaca4af6d6e49ab5d6abbafe Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/18242 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18242 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: Set IOSSTATE for trackpad I2C GPIOs
by gerrit＠coreboot.org 29 Jan '17

29 Jan '17

the following patch was just integrated into master: commit f224e836c0236621b52ea7d3c1118d2053df3537 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Fri Jan 27 11:37:30 2017 -0800 mainboard/google/reef: Set IOSSTATE for trackpad I2C GPIOs I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during standby states S3/S0ix. This causes leakage of power. To reduce the leakage, we have to pull these lines high during S3/S0ix. This is done by programming the IOSSTATE to HIz. Also note that we are using the internal pull ups to keep at SOC at 1.8V and the I2C lines are not floating. BUG=chrome-os-partner:62428,chrome-os-partner:61651 TEST=Enter S3/S0ix. Measure trackpad power. It should be less than 4mW. Also I2c lines should be pulled high in S3/S0ix. Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Reviewed-on: https://review.coreboot.org/18251 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18251 for details. -gerrit

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Patch set updated for coreboot: msrtool: add VIA C7
by Lubomir Rintel 28 Jan '17

28 Jan '17

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18258 -gerrit commit af248897391987f63a086e6600e2ace8b18dfd6f Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Jan 22 22:20:04 2017 +0100 msrtool: add VIA C7 Change-Id: I67c4f579f898a709dde3fab6bab1474a721da770 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/msrtool/Makefile.in | 2 +- util/msrtool/msrtool.c | 1 + util/msrtool/msrtool.h | 5 + util/msrtool/via_c7.c | 475 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 482 insertions(+), 1 deletion(-) diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in index 708515f..76b6a4b 100644 --- a/util/msrtool/Makefile.in +++ b/util/msrtool/Makefile.in @@ -22,7 +22,7 @@ PREFIX = @PREFIX@ CFLAGS = @CFLAGS@ -fno-pic LDFLAGS = @LDFLAGS@ -TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o +TARGETS = geodegx2.o geodelx.o cs5536.o k8.o via_c7.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o SYSTEMS = linux.o darwin.o freebsd.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 4060ba3..4f7c0ee 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -40,6 +40,7 @@ static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, { "K8", "AMD K8 Family", k8_probe, k8_msrs }, + { "via_c7", "VIA Esther processor, C7", via_c7_probe, via_c7_msrs }, { "intel_pentium3_early", "Intel Pentium III family", intel_pentium3_early_probe, intel_pentium3_early_msrs }, { "intel_pentium3", "Intel Pentium III Xeon Processor, Intel Pentium III Processor", intel_pentium3_probe, intel_pentium3_msrs }, { "intel_core1", "Intel Core Duo, Intel Core Solo processors", intel_core1_probe, intel_core1_msrs }, diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 7e85dc0..8559980 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -97,6 +97,7 @@ struct msrdef { typedef enum { VENDOR_INTEL = 0x756e6547, VENDOR_AMD = 0x68747541, + VENDOR_CENTAUR = 0x746e6543, } vendor_t; struct cpuid_t { @@ -216,6 +217,10 @@ extern const struct msrdef cs5536_msrs[]; extern int k8_probe(const struct targetdef *t, const struct cpuid_t *id); extern const struct msrdef k8_msrs[]; +/* via_c7.c */ +extern int via_c7_probe(const struct targetdef *t, const struct cpuid_t *id); +extern const struct msrdef via_c7_msrs[]; + /* intel_pentium3_early.c */ extern int intel_pentium3_early_probe(const struct targetdef *t, const struct cpuid_t *id); extern const struct msrdef intel_pentium3_early_msrs[]; diff --git a/util/msrtool/via_c7.c b/util/msrtool/via_c7.c new file mode 100644 index 0000000..83668e9 --- /dev/null +++ b/util/msrtool/via_c7.c @@ -0,0 +1,475 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * Copyright (C) 2017 Lubomir Rintel <lkundrak(a)v3.sk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msrtool.h" + +int via_c7_probe(const struct targetdef *target, const struct cpuid_t *id) { + return ((VENDOR_CENTAUR == id->vendor) && + (0x6 == id->family) && ( + (0xa == id->model) || /* C7 A */ + (0xd == id->model) || /* C7 D */ + (0xf == id->model) /* Nano */ + )); +} + +const struct msrdef via_c7_msrs[] = { + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[15:8] > 0 */ + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + "Performance Event Select Register 0", { + { 63, 32, RESERVED }, + { 31, 8, "CMASK", "R/W", PRESENT_HEX, { + /* When CMASK is not zero, the corresponding performance + * counter 0 increments each cycle if the event count + * is greater than or equal to the CMASK. + */ + { BITVAL_EOT } + }}, + { 23, 1, "INV", "R/W", PRESENT_BIN, { + { MSR1(0), "CMASK using as is" }, + { MSR1(1), "CMASK inerting" }, + { BITVAL_EOT } + }}, + { 22, 1, "EN", "R/W", PRESENT_BIN, { + { MSR1(0), "No commence counting" }, + { MSR1(1), "Commence counting" }, + { BITVAL_EOT } + }}, + { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "INT", "R/W", PRESENT_BIN, { + { MSR1(0), "Interrupt on counter overflow is disabled" }, + { MSR1(1), "Interrupt on counter overflow is enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "PC", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled pin control" }, + { MSR1(1), "Enabled pin control" }, + { BITVAL_EOT } + }}, + { 18, 1, "Edge", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled edge detection" }, + { MSR1(1), "Enabled edge detection" }, + { BITVAL_EOT } + }}, + { 17, 1, "OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is ring 0" }, + { BITVAL_EOT } + }}, + { 16, 1, "USR", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is not ring 0" }, + { BITVAL_EOT } + }}, + { 15, 8, "UMask", "R/W", PRESENT_HEX, { + /* Qualifies the microarchitectural condition + * to detect on the selected event logic. */ + { BITVAL_EOT } + }}, + { 7, 8, "Event Select", "R/W", PRESENT_HEX, { + /* Selects a performance event logic unit. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[15:8] > 0 */ + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + "Performance Event Select Register 1", { + { 63, 32, RESERVED }, + { 31, 8, "CMASK", "R/W", PRESENT_HEX, { + /* When CMASK is not zero, the corresponding performance + * counter 1 increments each cycle if the event count + * is greater than or equal to the CMASK. + */ + { BITVAL_EOT } + }}, + { 23, 1, "INV", "R/W", PRESENT_BIN, { + { MSR1(0), "CMASK using as is" }, + { MSR1(1), "CMASK inerting" }, + { BITVAL_EOT } + }}, + { 22, 1, "EN", "R/W", PRESENT_BIN, { + { MSR1(0), "No commence counting" }, + { MSR1(1), "Commence counting" }, + { BITVAL_EOT } + }}, + { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "INT", "R/W", PRESENT_BIN, { + { MSR1(0), "Interrupt on counter overflow is disabled" }, + { MSR1(1), "Interrupt on counter overflow is enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "PC", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled pin control" }, + { MSR1(1), "Enabled pin control" }, + { BITVAL_EOT } + }}, + { 18, 1, "Edge", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled edge detection" }, + { MSR1(1), "Enabled edge detection" }, + { BITVAL_EOT } + }}, + { 17, 1, "OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is ring 0" }, + { BITVAL_EOT } + }}, + { 16, 1, "USR", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is not ring 0" }, + { BITVAL_EOT } + }}, + { 15, 8, "UMask", "R/W", PRESENT_HEX, { + /* Qualifies the microarchitectural condition + * to detect on the selected event logic. */ + { BITVAL_EOT } + }}, + { 7, 8, "Event Select", "R/W", PRESENT_HEX, { + /* Selects a performance event logic unit. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { 63, 8, "Lowest Supported Clock Ratio", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 55, 8, "Lowest Supported Voltage", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 47, 8, "Highest Supported Clock Ratio", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 39, 8, "Highest Supported Voltage", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 8, "Lowest Clock Ratio", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 2, RESERVED }, + { 21, 2, "Performance Control MSR Transition", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 19, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 18, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 17, 1, "Voltage Transition in progress", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 16, 1, "Clock Ratio Transition in progress", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 15, 8, "Current Clock Ratio", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 8, "16*x + 700 = Current voltage in mV", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { 63, 48, RESERVED }, + { 15, 8, "Desired Clock Ratio", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 8, "16*x + 700 = Desired voltage in mV", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { 63, 59, RESERVED }, + { 15, 8, "allows selection of the on-demand clock modulation duty cycle", "R/W", PRESENT_BIN, { + { MSR1(0), "Reserved" }, + { MSR1(1), "12.5%" }, + { MSR1(2), "25.0%" }, + { MSR1(3), "37.5%" }, + { MSR1(4), "50.0%" }, + { MSR1(5), "62.5%" }, + { MSR1(6), "75.0%" }, + { MSR1(7), "87.5%" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { 63, 62, RESERVED }, + { 1, 1, "Enables APIC LVT interrupt on a low-to-high temp transition", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 0, 1, "Enables APIC LVT interrupt on a high-to-low temp transition", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { 63, 62, RESERVED }, + { 1, 1, "TCC assert detect", "R/O", PRESENT_BIN, { + { MSR1(0), "TCC not asserted" }, + { MSR1(1), "TCC asserted" }, + { BITVAL_EOT } + }}, + { 0, 1, "TCC trigger detect (Sticky bit, only cleared upon reset)", "R/O", PRESENT_BIN, { + { MSR1(0), "TCC not triggered" }, + { MSR1(1), "TCC triggered" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { 63, 47, RESERVED }, + { 16, 1, "Thermal Monitor enable", "R/W", PRESENT_HEX, { + { MSR1(0), "Thermal Monitor 1 enabled" }, + { MSR1(1), "Thermal Monitor 2 enabled" }, + { BITVAL_EOT } + }}, + { 15, 8, "Thermal Monitor 2 performance state clock ratio", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 8, "Thermal Monitor 2 performance state volatege", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + { 63, 43, RESERVED }, + { 20, 1, "PowerSaver lock", "R/W", PRESENT_BIN, { + { MSR1(0), "Bit 16 can be set and cleared." }, + { MSR1(1), "Bit 16 can only be cleared upon reset." }, + { BITVAL_EOT } + }}, + { 19, 3, RESERVED }, + { 16, 1, "Enhanced PowerSaver enable", "R/W", PRESENT_BIN, { + { MSR1(0), "Performance state changes disabled" }, + { MSR1(1), "Performance state changes enabled" }, + { BITVAL_EOT } + }}, + { 15, 5, RESERVED }, + { 10, 1, "PBE enable", "R/W", PRESENT_BIN, { + { MSR1(0), "FERR# legacy mode" }, + { MSR1(1), "Enables break events for APIC via FERR#" }, + { BITVAL_EOT } + }}, + { 9, 6, RESERVED }, + { 3, 1, "Thermal Monitor 2 enable", "R/W", PRESENT_BIN, { + { MSR1(0), "On-die clock throttling enabled" }, + { MSR1(1), "Thermal Monitor 1 or 2 enabled" }, + { BITVAL_EOT } + }}, + { 2, 3, RESERVED }, + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x1107, MSRTYPE_RDWR, MSR2(0,0), "FCR", + "Feature Control Register", { + { 63, 55, RESERVED }, + { 8, 1, "Disables L2 Cache", "R/W", PRESENT_BIN, { + { MSR1(0), "L2 Cache enabled" }, + { MSR1(1), "L2 Cache disabled" }, + { BITVAL_EOT } + }}, + { 7, 6, RESERVED }, + { 1, 1, "Enables CPUID reporting CMPXCHG8B", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled CPUID reporting CMPXCHG8B" }, + { MSR1(1), "Enabled CPUID reporting CMPXCHG8B" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x1108, MSRTYPE_RDWR, MSR2(0,0), "FCR2", + "Feature Control Register 2", { + { 63, 32, "Last 4 characters of Alternate Vendor ID string", "R/W", PRESENT_STR, { + { BITVAL_EOT } + }}, + { 31, 17, RESERVED }, + { 14, 1, "Use the Alternate Vendor ID string", "R/W", PRESENT_BIN, { + { MSR1(0), "The CPUID instruction vendor ID is CentaurHauls" }, + { MSR1(1), "The CPUID instruction returns the alternate Vendor ID" }, + { BITVAL_EOT } + }}, + { 13, 2, RESERVED }, + { 11, 4, "Family ID", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 4, "Model ID", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 3, 4, RESERVED }, + { BITS_EOT } + }}, + {0x1109, MSRTYPE_WRONLY, MSR2(0,0), "FCR3", + "Feature Control Register 3", { + { 63, 32, "First 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { + { BITVAL_EOT } + }}, + { 31, 32, "Middle 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1152, MSRTYPE_RDONLY, MSR2(0,0), "FUSES", "Fuses", { + { BITS_EOT } + }}, + {0x1153, MSRTYPE_RDONLY, MSR2(0,0), "BRAND", + "BRAND_1 XOR BRAND_2, (00b = C7-M, 01b = C7, 10b = Eden, 11b = Reserved)", { + { 63, 42, RESERVED }, + { 21, 2, "BRAND_1", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 2, "BRAND_2", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 17, 18, RESERVED }, + { BITS_EOT } + }}, + {0x1160, MSRTYPE_RDWR, MSR2(0,0), "UNK0", "", { + { BITS_EOT } + }}, + {0x1161, MSRTYPE_RDWR, MSR2(0,0), "UNK1", "", { + { BITS_EOT } + }}, + {0x1164, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_LOW", "(FUSES[6:4] * 5 + 65)", { + { BITS_EOT } + }}, + {0x1165, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_HI", "(FUSES[6:4] * 5 + 65) + 5", { + { BITS_EOT } + }}, + {0x1166, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_OVERSTRESS", "", { + { BITS_EOT } + }}, + {0x1167, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_USER_TRIP", "", { + { BITS_EOT } + }}, + {0x1168, MSRTYPE_RDWR, MSR2(0,0), "UNK2", "", { + { BITS_EOT } + }}, + {0x116a, MSRTYPE_RDWR, MSR2(0,0), "UNK3", "", { + { BITS_EOT } + }}, + {0x116b, MSRTYPE_RDWR, MSR2(0,0), "UNK4", "", { + { BITS_EOT } + }}, + { MSR_EOT } +};

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coreboot-gerrit January 2017