coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

1 participants
852 discussions

New patch to review for coreboot: mainboard/google/reef: Set edge triggered interrupt for GPIO_22
by Vaibhav Shankar 30 Jan '17

30 Jan '17

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18267 -gerrit commit 9086b8d1dd67f604153cfcaed8b91da2e2a2bbb9 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Jan 30 12:18:42 2017 -0800 mainboard/google/reef: Set edge triggered interrupt for GPIO_22 GPIO_22 currently configured as level triggered interrupt. This is casuing an interrupt storm during lid open from S0ix. This needs to be configured as EDGE_SINGLE. So this stops interttupt storm. BUG=chrome-os-partner:62458 TEST=Lid close/open. check CPU usage using top. It should not show 70% CPU usage. Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a --- src/mainboard/google/reef/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 3bb9a5f..a9a6248 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -299,7 +299,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ - PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE), /* EC wake */ PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */ PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */

1 0

Patch set updated for coreboot: build system: mark sub-make invocations as parallelizable
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18263 -gerrit commit e7627bccf6c45a515d0f964927c15935d5e41a27 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 15:29:34 2017 +0100 build system: mark sub-make invocations as parallelizable We rely on gnu make, so we can expect the jobserver to be around in parallel builds, too. Avoids some make warnings and slightly speeds up the build if those sub-makes are executed (eg for arm-trusted-firmware and vboot). Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile | 2 +- Makefile.inc | 4 ++-- src/arch/arm64/Makefile.inc | 4 ++-- src/vboot/Makefile.inc | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 2973030..4a05890 100644 --- a/Makefile +++ b/Makefile @@ -168,7 +168,7 @@ real-all: real-target .SECONDEXPANSION: $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) - $(MAKE) oldconfig + +$(MAKE) oldconfig # Add a new class of source/object files to the build system add-class= \ diff --git a/Makefile.inc b/Makefile.inc index d609ac4..2267f32 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -274,7 +274,7 @@ cbfs-files-processor-vsa= \ # arg2: output cbfs-files-processor-defconfig= \ $(eval $(2): $(1) $(obj)/build.h; \ - printf " CREATE $(2) (from $(1))\n"; \ + +printf " CREATE $(2) (from $(1))\n"; \ printf "\# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ $(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \ @@ -486,7 +486,7 @@ $(ROMCC_BIN): $(top)/util/romcc/romcc.c IFDTOOL:=$(objutil)/ifdtool/ifdtool $(IFDTOOL): @printf " Compile IFDTOOL\n" - $(MAKE) -C $(top)/util/ifdtool + +$(MAKE) -C $(top)/util/ifdtool cp -a $(top)/util/ifdtool/ifdtool $@ IFDFAKE:=$(objutil)/ifdfake/ifdfake diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 78ea427..c6c0280 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -172,8 +172,8 @@ BL31_LDFLAGS := --emit-relocs BL31 := $(obj)/bl31.elf $(BL31): $(obj)/build.h - @printf " MAKE $(subst $(obj)/,,$(@))\n" - CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ + printf " MAKE $(subst $(obj)/,,$(@))\n" + +CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ CFLAGS="$(BL31_CFLAGS)" \ LDFLAGS="$(BL31_LDFLAGS)" \ $(MAKE) -C $(BL31_SOURCE) $(BL31_MAKEARGS) $(BL31_TARGET) diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index c03d639..fb373c3 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -95,8 +95,8 @@ VBOOT_CFLAGS += -I$(abspath $(obj)) -include $(top)/src/include/kconfig.h -Wno-m VBOOT_CFLAGS += -DVBOOT_DEBUG $(VB2_LIB): $(obj)/config.h - @printf " MAKE $(subst $(obj)/,,$(@))\n" - $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ CC="$(CC_verstage)" \ CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ $(MAKE) -C $(VBOOT_SOURCE) \

1 0

Patch set updated for coreboot: util/xcompile: parallelize compiler checks
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18262 -gerrit commit 17417249d536a8f313bd512c085af99506b71000 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 15:27:35 2017 +0100 util/xcompile: parallelize compiler checks Speed up the execution of this script from ~6 seconds to ~1 on my system. There are some changes to its output, but they're actually _more_ correct: so far, architectures without compiler support kept compiler options for architectures that ran successfully earlier. Change-Id: I0532ea2178fbedb114a75cfd5ba39301e534e742 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/xcompile/xcompile | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 90220f6..32665f8 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -56,9 +56,6 @@ clean_up() { fi } -# Create temporary file(s). -TMPFILE="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" -touch "$TMPFILE" trap clean_up EXIT @@ -438,11 +435,24 @@ test_architecture() { fi } -# This loops over all supported architectures. +OUT="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" +rm -f $OUT + for architecture in $SUPPORTED_ARCHITECTURES; do + ( + TMPFILE="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" + touch $TMPFILE test_architecture "$architecture" detect_special_flags "$architecture" detect_compiler_runtime "$architecture" report_arch_toolchain + clean_up + ) > $OUT.$architecture & +done +wait + +for architecture in $SUPPORTED_ARCHITECTURES; do + cat $OUT.$architecture + rm -f $OUT.$architecture done echo XCOMPILE_COMPLETE:=1

1 0

Patch set updated for coreboot: build system: mark sub-make invocations as parallelizable
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18263 -gerrit commit ffc14e5d25f01cae4f25a07e01c34450dced3765 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 15:29:34 2017 +0100 build system: mark sub-make invocations as parallelizable We rely on gnu make, so we can expect the jobserver to be around in parallel builds, too. Avoids some make warnings and slightly speeds up the build if those sub-makes are executed (eg for arm-trusted-firmware and vboot). Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile | 2 +- Makefile.inc | 4 ++-- src/arch/arm64/Makefile.inc | 4 ++-- src/vboot/Makefile.inc | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 2973030..4a05890 100644 --- a/Makefile +++ b/Makefile @@ -168,7 +168,7 @@ real-all: real-target .SECONDEXPANSION: $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) - $(MAKE) oldconfig + +$(MAKE) oldconfig # Add a new class of source/object files to the build system add-class= \ diff --git a/Makefile.inc b/Makefile.inc index d609ac4..2267f32 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -274,7 +274,7 @@ cbfs-files-processor-vsa= \ # arg2: output cbfs-files-processor-defconfig= \ $(eval $(2): $(1) $(obj)/build.h; \ - printf " CREATE $(2) (from $(1))\n"; \ + +printf " CREATE $(2) (from $(1))\n"; \ printf "\# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ $(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \ @@ -486,7 +486,7 @@ $(ROMCC_BIN): $(top)/util/romcc/romcc.c IFDTOOL:=$(objutil)/ifdtool/ifdtool $(IFDTOOL): @printf " Compile IFDTOOL\n" - $(MAKE) -C $(top)/util/ifdtool + +$(MAKE) -C $(top)/util/ifdtool cp -a $(top)/util/ifdtool/ifdtool $@ IFDFAKE:=$(objutil)/ifdfake/ifdfake diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 78ea427..c6c0280 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -172,8 +172,8 @@ BL31_LDFLAGS := --emit-relocs BL31 := $(obj)/bl31.elf $(BL31): $(obj)/build.h - @printf " MAKE $(subst $(obj)/,,$(@))\n" - CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ + printf " MAKE $(subst $(obj)/,,$(@))\n" + +CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ CFLAGS="$(BL31_CFLAGS)" \ LDFLAGS="$(BL31_LDFLAGS)" \ $(MAKE) -C $(BL31_SOURCE) $(BL31_MAKEARGS) $(BL31_TARGET) diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index c03d639..fb373c3 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -95,8 +95,8 @@ VBOOT_CFLAGS += -I$(abspath $(obj)) -include $(top)/src/include/kconfig.h -Wno-m VBOOT_CFLAGS += -DVBOOT_DEBUG $(VB2_LIB): $(obj)/config.h - @printf " MAKE $(subst $(obj)/,,$(@))\n" - $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ CC="$(CC_verstage)" \ CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ $(MAKE) -C $(VBOOT_SOURCE) \

1 0

Patch set updated for coreboot: util/xcompile: parallelize compiler checks
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18262 -gerrit commit c993ad1a7b0c1e063091d52435c0b640f24119e6 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 15:27:35 2017 +0100 util/xcompile: parallelize compiler checks Speed up the execution of this script from ~6 seconds to ~1 on my system. There are some changes to its output, but they're actually _more_ correct: so far, architectures without compiler support kept compiler options for architectures that ran successfully earlier. Change-Id: I0532ea2178fbedb114a75cfd5ba39301e534e742 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/xcompile/xcompile | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 90220f6..32665f8 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -56,9 +56,6 @@ clean_up() { fi } -# Create temporary file(s). -TMPFILE="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" -touch "$TMPFILE" trap clean_up EXIT @@ -438,11 +435,24 @@ test_architecture() { fi } -# This loops over all supported architectures. +OUT="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" +rm -f $OUT + for architecture in $SUPPORTED_ARCHITECTURES; do + ( + TMPFILE="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" + touch $TMPFILE test_architecture "$architecture" detect_special_flags "$architecture" detect_compiler_runtime "$architecture" report_arch_toolchain + clean_up + ) > $OUT.$architecture & +done +wait + +for architecture in $SUPPORTED_ARCHITECTURES; do + cat $OUT.$architecture + rm -f $OUT.$architecture done echo XCOMPILE_COMPLETE:=1

1 0

Patch set updated for coreboot: nb/intel/x4x: Refactor dram freq and cas selection
by Arthur Heymans 30 Jan '17

30 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18156 -gerrit commit 30d24e0c265bef2fe30e79b5a97ba577e8ecb0de Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 16 23:32:02 2017 +0100 nb/intel/x4x: Refactor dram freq and cas selection The code did not check for tAC and for tCLK potentially selected the wrong spd offset for minimum cycle time. Adds some debugging output for freq and cas selection. The code is also written to be easily extendable for officially unsported dram frequencies like 533MHz and 400MHz which some vendor bios seem to support. Change-Id: Ie0d8326af50d3125bf35918ba645a6df27dd2ee4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 148 +++++++++++++++++++++++++----------- 1 file changed, 104 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..a0a7cbd 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -160,13 +160,6 @@ static void sdram_read_spds(struct sysinfo *s) } } -static u8 msbpos(u8 val) //Reverse -{ - u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); - return i; -} - static void mchinfo_ddr2(struct sysinfo *s) { const u32 eax = cpuid_ext(0x04, 0).eax; @@ -195,17 +188,58 @@ static void mchinfo_ddr2(struct sysinfo *s) } } +/* Decode tclk to picoseconds */ +static int decode_tclk(u8 spd_data) +{ + int high_nibble = (spd_data >> 4) * 1000; + int low_nibble; + switch (spd_data & 0xf) { + case 0xa: + low_nibble = 250; + break; + case 0xb: + low_nibble = 330; + break; + case 0xc: + low_nibble = 660; + break; + case 0xd: + low_nibble = 750; + default: + low_nibble = (spd_data & 0xf) * 100; + } + + return high_nibble + low_nibble; +} + static void sdram_detect_ram_speed(struct sysinfo *s) { - u8 i; + u8 i, j; u8 commoncas = 0; + u8 highest_commoncas; u8 currcas; u8 currfreq; u8 maxfreq; u8 freq = 0; + u8 high_cas; + u8 spd_tclk_lat[TOTAL_DIMMS][8] = { 0 }; + u8 spd_tac_lat[TOTAL_DIMMS][8] = { 0 }; + u8 tclk, tclk_target; + u8 tac, tac_target; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + 0x25, 0x40, /* DDR2 800: tCLK = 2.5ns tAC = 0.40ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD, + }; - // spdidx,cycletime @CAS 5 6 - u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}}; int found = 0; // Find max FSB speed @@ -225,57 +259,83 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; } - // Max RAM speed if (s->spd_type == DDR2) { - - maxfreq = MEM_CLOCK_800MHz; - - // Choose common CAS latency from {6,5}, 4 does not work - commoncas = 0x60; - + /* Only CAS 5 and 6 are supported */ + commoncas = SPD_CAS_LATENCY_DDR2_6 | SPD_CAS_LATENCY_DDR2_5; FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_7) { + high_cas = 7; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_6) { + high_cas = 6; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_5) { + high_cas = 5; + } /* Don't check for lower CAS since not supported */ commoncas &= s->dimms[i].cas_latencies; + for (j = 0; j < 3; i++) { + if (s->dimms[i].cas_latencies & (1 << (high_cas - j))) { + spd_tclk_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j]]; + spd_tac_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j + 1]]; + } + } } - if (commoncas == 0) { + if (commoncas == 0) die("No common CAS among dimms\n"); - } + else if (commoncas & SPD_CAS_LATENCY_DDR2_6) + highest_commoncas = 6; + else + highest_commoncas = 5; + + /* + * FIXME: datasheets say only 667MHz and 800MHz are supported + * but vendor bios also supports 533MHz and possibly 400MHz + */ + /* Test from higher to lower frequency, from lower to higher CAS latency */ + for (currfreq = MEM_CLOCK_800MHz; currfreq >= MEM_CLOCK_667MHz; currfreq--) { + printk(BIOS_DEBUG, "Trying DDR2: "); + switch (currfreq) { + case MEM_CLOCK_400MHz: + printk(BIOS_DEBUG, "%dMHz\n", 400); + case MEM_CLOCK_533MHz: + printk(BIOS_DEBUG, "%dMHz\n", 533); + case MEM_CLOCK_667MHz: + printk(BIOS_DEBUG, "%dMHz\n", 667); + case MEM_CLOCK_800MHz: + printk(BIOS_DEBUG, "%dMHz\n", 800); + } - // Working from fastest to slowest, - // fast->slow 5@800 6@800 5@667 - found = 0; - for (currcas = 5; currcas <= msbpos(commoncas); currcas++) { - currfreq = maxfreq; - if (currfreq == MEM_CLOCK_800MHz) { + for (currcas = 5; currcas <= highest_commoncas; currcas++) { + printk(BIOS_DEBUG, " Trying CAS: %d\n", currcas); found = 1; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) { - // this is too fast + tclk = decode_tclk(spd_tclk_lat[i][currcas]); + if (tclk == 0) { + /* this timing is not supprted */ found = 0; + break; + } + tclk_target = ddr2_speeds_table[2 * currfreq]; + tac = spd_tac_lat[i][currcas]; + tac_target = ddr2_speeds_table[2 * currfreq + 1]; + printk(BIOS_DEBUG, " tCLK: %dps , tCLK_target: %dps\n", tclk, tclk_target); + printk(BIOS_DEBUG, " tAC: 0.%xns , tAC_target: 0.%xns\n", tac, tac_target); + if ((tclk > tclk_target) && (tac > tac_target)) { + printk(BIOS_DEBUG, " Timing too fast\n"); + found = 0; + break; /* No need to check other dimms for these timings */ } } - if (found) - break; - } - } - - if (!found) { - currcas = 5; - currfreq = MEM_CLOCK_667MHz; - found = 1; - FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[9] > 0x30) { - // this is too fast - found = 0; + if (found) { + s->selected_timings.mem_clk = currfreq; + s->selected_timings.CAS = currcas; + return; } } } - if (!found) die("No valid CAS/frequencies detected\n"); - s->selected_timings.mem_clk = currfreq; - s->selected_timings.CAS = currcas; - } else { // DDR3 // Limit frequency for MCH maxfreq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;

1 0

Patch set updated for coreboot: nb/intel/x4x: Refactor dram freq and cas selection
by Arthur Heymans 30 Jan '17

30 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18156 -gerrit commit e078bd0f4ceede23341bb1b32c10359643066514 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 16 23:32:02 2017 +0100 nb/intel/x4x: Refactor dram freq and cas selection The code did not check for tAC and for tCLK potentially selected the wrong spd offset for minimum cycle time. Adds some debugging output for freq and cas selection. The code is also written to be easily extendable for officially unsported dram frequencies like 533MHz and 400MHz which some vendor bios seem to support. Change-Id: Ie0d8326af50d3125bf35918ba645a6df27dd2ee4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 136 ++++++++++++++++++++++++------------ 1 file changed, 92 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..23cb36f 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -160,13 +160,6 @@ static void sdram_read_spds(struct sysinfo *s) } } -static u8 msbpos(u8 val) //Reverse -{ - u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); - return i; -} - static void mchinfo_ddr2(struct sysinfo *s) { const u32 eax = cpuid_ext(0x04, 0).eax; @@ -195,17 +188,46 @@ static void mchinfo_ddr2(struct sysinfo *s) } } +/* Decode tclk to picoseconds */ +static int decode_tclk(u8 spd_data) +{ + int high_nibble = (spd_data >> 4) * 1000; + int low_nibble; + if ((spd_data & 0xf) > 0x9) /* Should be < 0xd */ + low_nibble = ((spd_data & 0xf) - 0x9) * 250; + else + low_nibble = spd_data * 100; + return high_nibble + low_nibble; +} + static void sdram_detect_ram_speed(struct sysinfo *s) { - u8 i; + u8 i, j; u8 commoncas = 0; + u8 highest_commoncas; u8 currcas; u8 currfreq; u8 maxfreq; u8 freq = 0; + u8 high_cas; + u8 spd_tclk_lat[TOTAL_DIMMS][8] = { 0 }; + u8 spd_tac_lat[TOTAL_DIMMS][8] = { 0 }; + u8 tclk, tclk_target; + u8 tac, tac_target; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + 0x25, 0x40, /* DDR2 800: tCLK = 2.5ns tAC = 0.40ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD, + }; - // spdidx,cycletime @CAS 5 6 - u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}}; int found = 0; // Find max FSB speed @@ -225,57 +247,83 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; } - // Max RAM speed if (s->spd_type == DDR2) { - - maxfreq = MEM_CLOCK_800MHz; - - // Choose common CAS latency from {6,5}, 4 does not work - commoncas = 0x60; - + /* Only CAS 5 and 6 are supported */ + commoncas = SPD_CAS_LATENCY_DDR2_6 | SPD_CAS_LATENCY_DDR2_5; FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_7) { + high_cas = 7; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_6) { + high_cas = 6; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_5) { + high_cas = 5; + } /* Don't check for lower CAS since not supported */ commoncas &= s->dimms[i].cas_latencies; + for (j = 0; j < 3; i++) { + if (s->dimms[i].cas_latencies & (1 << (high_cas - j))) { + spd_tclk_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j]]; + spd_tac_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j + 1]]; + } + } } - if (commoncas == 0) { + if (commoncas == 0) die("No common CAS among dimms\n"); - } + else if (commoncas & SPD_CAS_LATENCY_DDR2_6) + highest_commoncas = 6; + else + highest_commoncas = 5; + + /* + * FIXME: datasheets say only 667MHz and 800MHz are supported + * but vendor bios also supports 533MHz and possibly 400MHz + */ + /* Test from higher to lower frequency, from lower to higher CAS latency */ + for (currfreq = MEM_CLOCK_800MHz; currfreq >= MEM_CLOCK_667MHz; currfreq--) { + printk(BIOS_DEBUG, "Trying DDR2: "); + switch (currfreq) { + case MEM_CLOCK_400MHz: + printk(BIOS_DEBUG, "%dMHz\n", 400); + case MEM_CLOCK_533MHz: + printk(BIOS_DEBUG, "%dMHz\n", 533); + case MEM_CLOCK_667MHz: + printk(BIOS_DEBUG, "%dMHz\n", 667); + case MEM_CLOCK_800MHz: + printk(BIOS_DEBUG, "%dMHz\n", 800); + } - // Working from fastest to slowest, - // fast->slow 5@800 6@800 5@667 - found = 0; - for (currcas = 5; currcas <= msbpos(commoncas); currcas++) { - currfreq = maxfreq; - if (currfreq == MEM_CLOCK_800MHz) { + for (currcas = 5; currcas <= highest_commoncas; currcas++) { + printk(BIOS_DEBUG, " Trying CAS: %d\n", currcas); found = 1; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) { - // this is too fast + tclk = decode_tclk(spd_tclk_lat[i][currcas]); + if (tclk == 0) { + /* this timing is not supprted */ + found = 0; + break; + } + tclk_target = ddr2_speeds_table[2 * currfreq]; + tac = spd_tac_lat[i][currcas]; + tac_target = ddr2_speeds_table[2 * currfreq + 1]; + printk(BIOS_DEBUG, " tCLK: %dps , tCLK_target: %dps\n", tclk, tclk_target); + printk(BIOS_DEBUG, " tAC: 0.%xns , tAC_target: 0.%xns\n", tac, tac_target); + if ((tclk > tclk_target) && (tac > tac_target)) { + printk(BIOS_DEBUG, " Timing too fast\n"); found = 0; + break; /* No need to check other dimms for these timings */ } } - if (found) - break; - } - } - - if (!found) { - currcas = 5; - currfreq = MEM_CLOCK_667MHz; - found = 1; - FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[9] > 0x30) { - // this is too fast - found = 0; + if (found) { + s->selected_timings.mem_clk = currfreq; + s->selected_timings.CAS = currcas; + return; } } } - if (!found) die("No valid CAS/frequencies detected\n"); - s->selected_timings.mem_clk = currfreq; - s->selected_timings.CAS = currcas; - } else { // DDR3 // Limit frequency for MCH maxfreq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;

1 0

Patch set updated for coreboot: nb/intel/x4x: Refactor dram freq and cas selection
by Arthur Heymans 30 Jan '17

30 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18156 -gerrit commit d021ebead81c608d2c7cb6734c6488181765c477 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 16 23:32:02 2017 +0100 nb/intel/x4x: Refactor dram freq and cas selection The code did not check for tAC and for tCLK potentially selected the wrong spd offset for minimum cycle time. Adds some debugging output for freq and cas selection. The code is also written to be easily extendable for officially unsported dram frequencies like 533MHz and 400MHz which some vendor bios seem to support. Change-Id: Ie0d8326af50d3125bf35918ba645a6df27dd2ee4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 135 ++++++++++++++++++++++++------------ 1 file changed, 91 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..77e427c 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -160,13 +160,6 @@ static void sdram_read_spds(struct sysinfo *s) } } -static u8 msbpos(u8 val) //Reverse -{ - u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); - return i; -} - static void mchinfo_ddr2(struct sysinfo *s) { const u32 eax = cpuid_ext(0x04, 0).eax; @@ -195,17 +188,46 @@ static void mchinfo_ddr2(struct sysinfo *s) } } +/* Decode tclk to picoseconds */ +static int decode_tclk(u8 spd_data) +{ + int high_nibble = (spd_data >> 4) * 1000; + int low_nibble; + if ((spd_data & 0xf) > 0x9) /* Should be < 0xd */ + low_nibble = ((spd_data & 0xf) - 0x9) * 250; + else + low_nibble = spd_data * 100; + return high_nibble + low_nibble; +} + static void sdram_detect_ram_speed(struct sysinfo *s) { - u8 i; + u8 i, j; u8 commoncas = 0; + u8 highest_commoncas; u8 currcas; u8 currfreq; u8 maxfreq; u8 freq = 0; + u8 high_cas; + u8 spd_tclk_lat[TOTAL_DIMMS][8] = { 0 }; + u8 spd_tac_lat[TOTAL_DIMMS][8] = { 0 }; + u8 tclk, tclk_target; + u8 tac, tac_target; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + 0x25, 0x40, /* DDR2 800: tCLK = 2.5ns tAC = 0.40ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD, + }; - // spdidx,cycletime @CAS 5 6 - u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}}; int found = 0; // Find max FSB speed @@ -225,57 +247,82 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; } - // Max RAM speed if (s->spd_type == DDR2) { - - maxfreq = MEM_CLOCK_800MHz; - - // Choose common CAS latency from {6,5}, 4 does not work - commoncas = 0x60; - + /* Only CAS 5 and 6 are supported */ + commoncas = SPD_CAS_LATENCY_DDR2_6 | SPD_CAS_LATENCY_DDR2_5; FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_7) { + high_cas = 7; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_6) { + high_cas = 6; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_5) { + high_cas = 5; + } /* Don't check for lower CAS since not supported */ commoncas &= s->dimms[i].cas_latencies; + for (j = 0; j < 3; i++) { + if (s->dimms[i].cas_latencies & (1 << (high_cas - j))) { + spd_tclk_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j]]; + spd_tac_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j + 1]]; + } + } } - if (commoncas == 0) { + if (commoncas == 0) die("No common CAS among dimms\n"); - } + else if (commoncas & SPD_CAS_LATENCY_DDR2_6) + highest_commoncas = 6; + else + highest_commoncas = 5; + + /* + * FIXME: datasheets say only 667MHz and 800MHz are supported + * but vendor bios also supports 533MHz and possibly 400MHz + */ + /* Test from higher to lower frequency, from lower to higher CAS latency */ + for (currfreq = MEM_CLOCK_800MHz; currfreq >= MEM_CLOCK_667MHz; currfreq--) { + printk(BIOS_DEBUG, "Trying DDR2: "); + switch (currfreq) { + case MEM_CLOCK_400MHz: + printk(BIOS_DEBUG, "%dMHz\n", 400); + case MEM_CLOCK_533MHz: + printk(BIOS_DEBUG, "%dMHz\n", 533); + case MEM_CLOCK_667MHz: + printk(BIOS_DEBUG, "%dMHz\n", 667); + case MEM_CLOCK_800MHz: + printk(BIOS_DEBUG, "%dMHz\n", 800); + } - // Working from fastest to slowest, - // fast->slow 5@800 6@800 5@667 - found = 0; - for (currcas = 5; currcas <= msbpos(commoncas); currcas++) { - currfreq = maxfreq; - if (currfreq == MEM_CLOCK_800MHz) { + for (currcas = 5; currcas <= highest_commoncas; currcas++) { + printk(BIOS_DEBUG, " Trying CAS: %d\n", currcas); found = 1; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) { - // this is too fast + tclk = decode_tclk(spd_tclk_lat[i][currcas]); + if (tclk == 0) + /* this timing is not supprted */ found = 0; + break; + tclk_target = ddr2_speeds_table[2 * currfreq]; + tac = spd_tac_lat[i][currcas]; + tac_target = ddr2_speeds_table[2 * currfreq + 1]; + printk(BIOS_DEBUG, " tCLK: %dps , tCLK_target: %dps\n", tclk, tclk_target); + printk(BIOS_DEBUG, " tAC: 0.%xns , tAC_target: 0.%xns\n", tac, tac_target); + if ((tclk > tclk_target) && (tac > tac_target)) { + printk(BIOS_DEBUG, " Timing too fast\n"); + found = 0; + break; /* No need to check other dimms for these timings */ } } - if (found) - break; - } - } - - if (!found) { - currcas = 5; - currfreq = MEM_CLOCK_667MHz; - found = 1; - FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[9] > 0x30) { - // this is too fast - found = 0; + if (found) { + s->selected_timings.mem_clk = currfreq; + s->selected_timings.CAS = currcas; + return; } } } - if (!found) die("No valid CAS/frequencies detected\n"); - s->selected_timings.mem_clk = currfreq; - s->selected_timings.CAS = currcas; - } else { // DDR3 // Limit frequency for MCH maxfreq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;

1 0

Patch set updated for coreboot: nb/intel/x4x: Refactor dram freq and cas selection
by Arthur Heymans 30 Jan '17

30 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18156 -gerrit commit 7e00be230148488f225923c2370f0c781c6151eb Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 16 23:32:02 2017 +0100 nb/intel/x4x: Refactor dram freq and cas selection The code did not check for tAC and for tCLK potentially selected the wrong spd offset for minimum cycle time. Adds some debugging output for freq and cas selection. The code is also written to be easily extendable for officially unsported dram frequencies like 533MHz and 400MHz which some vendor bios seem to support. Change-Id: Ie0d8326af50d3125bf35918ba645a6df27dd2ee4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 135 ++++++++++++++++++++++++------------ 1 file changed, 91 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..a6ed7f4 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -160,13 +160,6 @@ static void sdram_read_spds(struct sysinfo *s) } } -static u8 msbpos(u8 val) //Reverse -{ - u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); - return i; -} - static void mchinfo_ddr2(struct sysinfo *s) { const u32 eax = cpuid_ext(0x04, 0).eax; @@ -195,17 +188,46 @@ static void mchinfo_ddr2(struct sysinfo *s) } } +/* Decode tclk to picoseconds */ +static int decode_tclk(u8 spd_data) +{ + int high_nibble = (spd_data >> 4) * 1000; + int low_nibble; + if ((spd_data & 0xf) > 0x9) /* Should be < 0xd */ + low_nibble = ((spd_data & 0xf) - 0x9) * 250; + else + low_nibble = spd_data * 100; + return high_nibble + low_nibble; +} + static void sdram_detect_ram_speed(struct sysinfo *s) { - u8 i; + u8 i, j; u8 commoncas = 0; + u8 highest_commoncas; u8 currcas; u8 currfreq; u8 maxfreq; u8 freq = 0; + u8 high_cas; + u8 spd_tclk_lat[TOTAL_DIMMS][8] = { 0 }; + u8 spd_tac_lat[TOTAL_DIMMS][8] = { 0 }; + u8 tclk, tclk_target; + u8 tac, tac_target; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + 0x25, 0x40, /* DDR2 800: tCLK = 2.5ns tAC = 0.40ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD, + }; - // spdidx,cycletime @CAS 5 6 - u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}}; int found = 0; // Find max FSB speed @@ -225,57 +247,82 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; } - // Max RAM speed if (s->spd_type == DDR2) { - - maxfreq = MEM_CLOCK_800MHz; - - // Choose common CAS latency from {6,5}, 4 does not work - commoncas = 0x60; - + /* Only CAS 5 and 6 are supported */ + commoncas = SPD_CAS_LATENCY_DDR2_6 | SPD_CAS_LATENCY_DDR2_5; FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_7) { + high_cas = 7; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_6) { + high_cas = 6; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_5) { + high_cas = 5; + } /* Don't check for lower CAS since not supported */ commoncas &= s->dimms[i].cas_latencies; + for (j = 0; j < 3; i++) { + if (s->dimms[i].cas_latencies & (1 << (hig_cas - j)) { + spd_tclk_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j]]; + spd_tac_lat[i][high_cas - j] = + s->dimms[i].spd_data[spd_lookup_table[2 * j + 1]]; + } + } } - if (commoncas == 0) { + if (commoncas == 0) die("No common CAS among dimms\n"); - } + else if (commoncas & SPD_CAS_LATENCY_DDR2_6) + highest_commoncas = 6; + else + highest_commoncas = 5; + + /* + * FIXME: datasheets say only 667MHz and 800MHz are supported + * but vendor bios also supports 533MHz and possibly 400MHz + */ + /* Test from higher to lower frequency, from lower to higher CAS latency */ + for (currfreq = MEM_CLOCK_800MHz; currfreq >= MEM_CLOCK_667MHz; currfreq--) { + printk(BIOS_DEBUG, "Trying DDR2: "); + switch (currfreq) { + case MEM_CLOCK_400MHz: + printk(BIOS_DEBUG, "%dMHz\n", 400); + case MEM_CLOCK_533MHz: + printk(BIOS_DEBUG, "%dMHz\n", 533); + case MEM_CLOCK_667MHz: + printk(BIOS_DEBUG, "%dMHz\n", 667); + case MEM_CLOCK_800MHz: + printk(BIOS_DEBUG, "%dMHz\n", 800); + } - // Working from fastest to slowest, - // fast->slow 5@800 6@800 5@667 - found = 0; - for (currcas = 5; currcas <= msbpos(commoncas); currcas++) { - currfreq = maxfreq; - if (currfreq == MEM_CLOCK_800MHz) { + for (currcas = 5; currcas <= highest_commoncas; currcas++) { + printk(BIOS_DEBUG, " Trying CAS: %d\n", currcas); found = 1; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) { - // this is too fast + tclk = decode_tclk(spd_tclk_lat[i][currcas]); + if (tclk == 0) + /* this timing is not supprted */ found = 0; + break; + tclk_target = ddr2_speeds_table[2 * currfreq]; + tac = spd_tac_lat[i][currcas]; + tac_target = ddr2_speeds_table[2 * currfreq + 1]; + printk(BIOS_DEBUG, " tCLK: %dps , tCLK_target: %dps\n", tclk, tclk_target); + printk(BIOS_DEBUG, " tAC: 0.%xns , tAC_target: 0.%xns\n", tac, tac_target); + if ((tclk > tclk_target) && (tac > tac_target)) { + printk(BIOS_DEBUG, " Timing too fast\n"); + found = 0; + break; /* No need to check other dimms for these timings */ } } - if (found) - break; - } - } - - if (!found) { - currcas = 5; - currfreq = MEM_CLOCK_667MHz; - found = 1; - FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[9] > 0x30) { - // this is too fast - found = 0; + if (found) { + s->selected_timings.mem_clk = currfreq; + s->selected_timings.CAS = currcas; + return; } } } - if (!found) die("No valid CAS/frequencies detected\n"); - s->selected_timings.mem_clk = currfreq; - s->selected_timings.CAS = currcas; - } else { // DDR3 // Limit frequency for MCH maxfreq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;

1 0

Patch set updated for coreboot: nb/intel/x4x: Refactor dram freq and cas selection
by Arthur Heymans 30 Jan '17

30 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18156 -gerrit commit 32310bdbfa53a5260f4901ef1bacb34ee3448f7c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 16 23:32:02 2017 +0100 nb/intel/x4x: Refactor dram freq and cas selection The code did not check for tAC and for tCLK potentially selected the wrong spd offset for minimum cycle time. Adds some debugging output for freq and cas selection. The code is also written to be easily extendable for officially unsported dram frequencies like 533MHz and 400MHz which some vendor bios seem to support. Change-Id: Ie0d8326af50d3125bf35918ba645a6df27dd2ee4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 130 ++++++++++++++++++++++++------------ 1 file changed, 86 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..d47b8a7 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -160,13 +160,6 @@ static void sdram_read_spds(struct sysinfo *s) } } -static u8 msbpos(u8 val) //Reverse -{ - u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); - return i; -} - static void mchinfo_ddr2(struct sysinfo *s) { const u32 eax = cpuid_ext(0x04, 0).eax; @@ -195,17 +188,46 @@ static void mchinfo_ddr2(struct sysinfo *s) } } +/* Decode tclk to picoseconds */ +static int decode_tclk(u8 spd_data) +{ + int high_nibble = (spd_data >> 4) * 1000; + int low_nibble; + if ((spd_data & 0xf) > 0x9) /* Should be < 0xd */ + low_nibble = ((spd_data & 0xf) - 0x9) * 250; + else + low_nibble = spd_data * 100; + return high_nibble + low_nibble; +} + static void sdram_detect_ram_speed(struct sysinfo *s) { - u8 i; + u8 i, j; u8 commoncas = 0; + u8 highest_commoncas; u8 currcas; u8 currfreq; u8 maxfreq; u8 freq = 0; + u8 high_cas; + u8 spd_tclk_lat[TOTAL_DIMMS][8]; + u8 spd_tac_lat[TOTAL_DIMMS][8]; + u8 tclk, tclk_target; + u8 tac, tac_target; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + 0x25, 0x40, /* DDR2 800: tCLK = 2.5ns tAC = 0.40ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD, + }; - // spdidx,cycletime @CAS 5 6 - u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}}; int found = 0; // Find max FSB speed @@ -225,57 +247,77 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; } - // Max RAM speed if (s->spd_type == DDR2) { - - maxfreq = MEM_CLOCK_800MHz; - - // Choose common CAS latency from {6,5}, 4 does not work - commoncas = 0x60; - + /* Only CAS 5 and 6 are supported */ + commoncas = SPD_CAS_LATENCY_DDR2_6 | SPD_CAS_LATENCY_DDR2_5; FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_7) { + high_cas = 7; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_6) { + high_cas = 6; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_5) { + high_cas = 5; + } /* Don't check for lower CAS since not supported */ commoncas &= s->dimms[i].cas_latencies; + for (j = 0; j < 3; i++) { + spd_tclk_lat[i][high_cas - j] = s->dimms[i].spd_data[spd_lookup_table[2 * j]]; + spd_tac_lat[i][high_cas - j] = s->dimms[i].spd_data[spd_lookup_table[2 * j + 1]]; + } } - if (commoncas == 0) { + if (commoncas == 0) die("No common CAS among dimms\n"); - } + else if (commoncas & SPD_CAS_LATENCY_DDR2_6) + highest_commoncas = 6; + else + highest_commoncas = 5; + + /* + * FIXME: datasheets say only 667MHz and 800MHz are supported + * but vendor bios also supports 533MHz and possibly 400MHz + */ + /* Test from higher to lower frequency, from lower to higher CAS latency */ + for (currfreq = MEM_CLOCK_800MHz; currfreq >= MEM_CLOCK_667MHz; currfreq--) { + printk(BIOS_DEBUG, "Trying DDR2: "); + switch (currfreq) { + case MEM_CLOCK_400MHz: + printk(BIOS_DEBUG, "%dMHz\n", 400); + case MEM_CLOCK_533MHz: + printk(BIOS_DEBUG, "%dMHz\n", 533); + case MEM_CLOCK_667MHz: + printk(BIOS_DEBUG, "%dMHz\n", 667); + case MEM_CLOCK_800MHz: + printk(BIOS_DEBUG, "%dMHz\n", 800); + } - // Working from fastest to slowest, - // fast->slow 5@800 6@800 5@667 - found = 0; - for (currcas = 5; currcas <= msbpos(commoncas); currcas++) { - currfreq = maxfreq; - if (currfreq == MEM_CLOCK_800MHz) { + for (currcas = 5; currcas <= highest_commoncas; currcas++) { + printk(BIOS_DEBUG, " Trying CAS: %d\n", currcas); found = 1; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) { - // this is too fast + tclk = decode_tclk(spd_tclk_lat[i][currcas]); + if (tclk == 0) + /* this timing is not supprted */ + break; + tclk_target = ddr2_speeds_table[2 * currfreq]; + tac = spd_tac_lat[i][currcas]; + tac_target = ddr2_speeds_table[2 * currfreq + 1]; + printk(BIOS_DEBUG, " tCLK: %dps , tCLK_target: %dps\n", tclk, tclk_target); + printk(BIOS_DEBUG, " tAC: 0.%xns , tAC_target: 0.%xns\n", tac, tac_target); + if ((tclk > tclk_target) && (tac > tac_target)) { + printk(BIOS_DEBUG, " Timing too fast\n"); found = 0; + break; /* No need to check other dimms for these timings */ } } - if (found) - break; - } - } - - if (!found) { - currcas = 5; - currfreq = MEM_CLOCK_667MHz; - found = 1; - FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[9] > 0x30) { - // this is too fast - found = 0; + if (found) { + s->selected_timings.mem_clk = currfreq; + s->selected_timings.CAS = currcas; + return; } } } - if (!found) die("No valid CAS/frequencies detected\n"); - s->selected_timings.mem_clk = currfreq; - s->selected_timings.CAS = currcas; - } else { // DDR3 // Limit frequency for MCH maxfreq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;

1 0

← Newer
1
2
3
4
5
6
7
...
86
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2017