coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: src/lib: Update Makefile to keep build/spd.bin rule private
by gerrit＠coreboot.org 31 Jan '17

31 Jan '17

the following patch was just integrated into master: commit 8e4bb3164a1af2a988c63dfa92777de9d60fae3f Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 29 18:11:36 2017 -0700 src/lib: Update Makefile to keep build/spd.bin rule private The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin' implementation. It wasn't guarded though, so it was generating a build warning for any other platform that generated an spd.bin file. Sample warning that this fixes: src/mainboard/gizmosphere/gizmo/Makefile.inc:42: warning: overriding recipe for target 'build/spd.bin' src/lib/Makefile.inc:298: warning: ignoring old recipe for target 'build/spd.bin' Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/18261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/18261 for details. -gerrit

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Patch set updated for coreboot: src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested
by Martin Roth 31 Jan '17

31 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17909 -gerrit commit 388cb964b7d7f8f559c2cb1c8754b1f602ecc020 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 16:04:55 2016 -0700 src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested The four options are only used in X86: - BOOTBLOCK_SIMPLE - BOOTBLOCK_NORMAL - BOOTBLOCK_SOURCE - SKIP_MAX_REBOOT_CNT_CLEAR Move them all into src/arch/x86/Kconfig - this puts them in the chipset menu instead of general setup. Verified that this makes no significant changes to any config file. Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 27 --------------------------- src/arch/x86/Kconfig | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 84ea565..8337264 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -214,33 +214,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -# TODO: This doesn't belong here, move to src/arch/x86/Kconfig -choice - prompt "Bootblock behaviour" - default BOOTBLOCK_SIMPLE - -config BOOTBLOCK_SIMPLE - bool "Always load fallback" - -config BOOTBLOCK_NORMAL - bool "Switch to normal if CMOS says so" - -endchoice - -config BOOTBLOCK_SOURCE - string - default "bootblock_simple.c" if BOOTBLOCK_SIMPLE - default "bootblock_normal.c" if BOOTBLOCK_NORMAL - -config SKIP_MAX_REBOOT_CNT_CLEAR - bool "Do not clear reboot count after successful boot" - depends on BOOTBLOCK_NORMAL - help - Do not clear the reboot count immediately after successful boot. - Set to allow the payload to control normal/fallback image recovery. - Note that it is the responsibility of the payload to reset the - normal boot bit to 1 after each successsful boot. - config UPDATE_IMAGE bool "Update existing coreboot.rom image" help diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6280024..c153a74 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -214,3 +214,29 @@ config ROMSTAGE_DEBUG_SPINLOOP help Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence. + +choice + prompt "Bootblock behaviour" + default BOOTBLOCK_SIMPLE + +config BOOTBLOCK_SIMPLE + bool "Always load fallback" + +config BOOTBLOCK_NORMAL + bool "Switch to normal if CMOS says so" + +endchoice + +config BOOTBLOCK_SOURCE + string + default "bootblock_simple.c" if BOOTBLOCK_SIMPLE + default "bootblock_normal.c" if BOOTBLOCK_NORMAL + +config SKIP_MAX_REBOOT_CNT_CLEAR + bool "Do not clear reboot count after successful boot" + depends on BOOTBLOCK_NORMAL + help + Do not clear the reboot count immediately after successful boot. + Set to allow the payload to control normal/fallback image recovery. + Note that it is the responsibility of the payload to reset the + normal boot bit to 1 after each successsful boot.

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Patch set updated for coreboot: src/Kconfig: Remove 'default n' statements from early in Kconfig
by Martin Roth 31 Jan '17

31 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17908 -gerrit commit 077e7f3cbd5fa9878fba6e45a49c43907a511a91 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:35:12 2016 -0700 src/Kconfig: Remove 'default n' statements from early in Kconfig For boolean types, 'n' is the default default value - it doesn't NEED to be set. If it IS set, it prevents a later default from being set. So by removing the 'default n' statements from the early symbols, they can be overridden other places in the tree. Verified that this makes no significant changes to any config file. Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c0776d8..84ea565 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -111,7 +111,6 @@ config SCONFIG_GENPARSER config USE_OPTION_TABLE bool "Use CMOS for configuration values" - default n depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" @@ -119,7 +118,6 @@ config USE_OPTION_TABLE config STATIC_OPTION_TABLE bool "Load default configuration values into CMOS on each boot" - default n depends on USE_OPTION_TABLE help Enable this option to reset "CMOS" NVRAM values to default on @@ -179,14 +177,12 @@ config INCLUDE_CONFIG_FILE config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. config USE_BLOBS bool "Allow use of binary-only repository" - default n help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. @@ -195,7 +191,6 @@ config USE_BLOBS config COVERAGE bool "Code coverage support" depends on COMPILER_GCC - default n help Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. @@ -204,7 +199,6 @@ config COVERAGE config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." - default n select RELOCATABLE_MODULES help The reloctable ramstage support allows for the ramstage to be built @@ -216,7 +210,6 @@ config RELOCATABLE_RAMSTAGE config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM depends on RELOCATABLE_RAMSTAGE bool "Cache the relocated ramstage outside of cbmem." - default n help The relocated ramstage is saved in an area specified by the by the board and/or chipset. @@ -241,7 +234,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" - default n depends on BOOTBLOCK_NORMAL help Do not clear the reboot count immediately after successful boot. @@ -251,7 +243,6 @@ config SKIP_MAX_REBOOT_CNT_CLEAR config UPDATE_IMAGE bool "Update existing coreboot.rom image" - default n help If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already @@ -270,7 +261,6 @@ config BOARD_ID_STRING config RAM_CODE_SUPPORT bool - default n help If enabled, coreboot discovers RAM configuration (value obtained by reading board straps) and stores it in coreboot table.

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Patch set updated for coreboot: src/Kconfig: Move options with no prompt towards the end of the file
by Martin Roth 31 Jan '17

31 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17907 -gerrit commit e05fff917a787be20801a9969455dea7d532a5b0 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:25:15 2016 -0700 src/Kconfig: Move options with no prompt towards the end of the file Options with no prompt can go anywhere in the tree with the same dependencies and they have the same effect. Moving them lower in the tree allows the default values to be overridden by other Kconfig files. Verified that this makes no significant changes to any config file. Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 193 ++++++++++++++++++++++++++++++------------------------------ 1 file changed, 95 insertions(+), 98 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f6c3ff7..c0776d8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -126,10 +126,6 @@ config STATIC_OPTION_TABLE every boot. Use this if you want the NVRAM configuration to never be modified from its default values. -config UNCOMPRESSED_RAMSTAGE - bool - default n - config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" # Default value set at the end of the file @@ -181,22 +177,6 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 -config NO_XIP_EARLY_STAGES - bool - default n if ARCH_X86 - default y - help - Identify if early stages are eXecute-In-Place(XIP). - -config EARLY_CBMEM_INIT - def_bool !LATE_CBMEM_INIT - -config EARLY_CBMEM_LIST - bool - default n - help - Enable display of CBMEM during romstage and postcar. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -221,14 +201,6 @@ config COVERAGE coverage information in CBMEM for extraction from user space. If unsure, say N. -config RELOCATABLE_MODULES - bool - default n - help - If RELOCATABLE_MODULES is selected then support is enabled for - building relocatable modules in the RAM stage. Those modules can be - loaded anywhere and all the relocations are handled automatically. - config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." @@ -249,13 +221,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -config NO_STAGE_CACHE - bool - default n - help - Do not save any component in stage cache for resume path. On resume, - all components would be read back from CBFS again. - # TODO: This doesn't belong here, move to src/arch/x86/Kconfig choice prompt "Bootblock behaviour" @@ -269,23 +234,11 @@ config BOOTBLOCK_NORMAL endchoice -# To be selected by arch, SoC or mainboard if it does not want use the normal -# src/lib/bootblock.c#main() C entry point. -config BOOTBLOCK_CUSTOM - bool - default n - config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL -# To be selected by arch or platform if a C environment is available during the -# bootblock. Normally this signifies availability of RW memory (e.g. SRAM). -config C_ENVIRONMENT_BOOTBLOCK - bool - default n - config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n @@ -307,56 +260,6 @@ config UPDATE_IMAGE If unsure, select 'N' -config GENERIC_GPIO_LIB - bool - default n - help - If enabled, compile the generic GPIO library. A "generic" GPIO - implies configurability usually found on SoCs, particularly the - ability to control internal pull resistors. - -config GENERIC_SPD_BIN - bool - default n - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - depends on GENERIC_SPD_BIN - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - depends on GENERIC_SPD_BIN - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config BOARD_ID_AUTO - bool - default n - help - Mainboards that can read a board ID from the hardware straps - (ie. GPIO) select this configuration option. - -config BOARD_ID_MANUAL - bool - default n - depends on !BOARD_ID_AUTO - help - If you want to maintain a board ID, but the hardware does not - have straps to automatically determine the ID, you can say Y - here and add a file named 'board_id' to CBFS. If you don't know - what this is about, say N. - config BOARD_ID_STRING string "Board ID" # Default value set at the end of the file @@ -1166,7 +1069,10 @@ config DEBUG_ADA_CODE endmenu -# These probably belong somewhere else, but they are needed somewhere. + +############################################################################### +# Set variables with no prompt - these can be set anywhere, and putting at +# the end of this file gives the most flexibility. config ENABLE_APIC_EXT_ID bool default n @@ -1272,6 +1178,97 @@ config RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y +config UNCOMPRESSED_RAMSTAGE + bool + +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + help + Identify if early stages are eXecute-In-Place(XIP). + +config EARLY_CBMEM_INIT + def_bool !LATE_CBMEM_INIT + +config EARLY_CBMEM_LIST + bool + default n + help + Enable display of CBMEM during romstage and postcar. + +config RELOCATABLE_MODULES + bool + help + If RELOCATABLE_MODULES is selected then support is enabled for + building relocatable modules in the RAM stage. Those modules can be + loaded anywhere and all the relocations are handled automatically. + +config NO_STAGE_CACHE + bool + help + Do not save any component in stage cache for resume path. On resume, + all components would be read back from CBFS again. + +config GENERIC_GPIO_LIB + bool + help + If enabled, compile the generic GPIO library. A "generic" GPIO + implies configurability usually found on SoCs, particularly the + ability to control internal pull resistors. + +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 4 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config BOARD_ID_AUTO + bool + default n + help + Mainboards that can read a board ID from the hardware straps + (ie. GPIO) select this configuration option. + +config BOARD_ID_MANUAL + bool + default n + depends on !BOARD_ID_AUTO + help + If you want to maintain a board ID, but the hardware does not + have straps to automatically determine the ID, you can say Y + here and add a file named 'board_id' to CBFS. If you don't know + what this is about, say N. + +config BOOTBLOCK_CUSTOM + # To be selected by arch, SoC or mainboard if it does not want use the normal + # src/lib/bootblock.c#main() C entry point. + bool + +config C_ENVIRONMENT_BOOTBLOCK + # To be selected by arch or platform if a C environment is available during the + # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). + bool + + ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in

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Patch set updated for coreboot: src/Kconfig: Move early defaults to the end of the file
by Martin Roth 31 Jan '17

31 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17906 -gerrit commit 6e566d4b9c754b663cbcb271eda9f6ecbfe7d75b Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:05:37 2016 -0700 src/Kconfig: Move early defaults to the end of the file For Kconfig options that we might want to override the default, move the fallback default to the bottom of the file. This allows the default to be set anywhere else, without requiring a select. This is especially important for non-boolean symbols, which can't have their defaults overridden in the Kconfig. Those can only be updated in a saved config file. Verified that this makes no significant changes to any config file. Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 46 +++++++++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 436964c..f6c3ff7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -132,8 +132,7 @@ config UNCOMPRESSED_RAMSTAGE config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" - default y if !UNCOMPRESSED_RAMSTAGE - default n + # Default value set at the end of the file help Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash @@ -142,7 +141,7 @@ config COMPRESS_RAMSTAGE config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 - default y + # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash space and speed up boot, since the time for reading the image from SPI @@ -152,7 +151,7 @@ config COMPRESS_PRERAM_STAGES config INCLUDE_CONFIG_FILE bool "Include the coreboot .config file into the ROM image" - default y + # Default value set at the end of the file help Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which @@ -360,7 +359,7 @@ config BOARD_ID_MANUAL config BOARD_ID_STRING string "Board ID" - default "(none)" + # Default value set at the end of the file depends on BOARD_ID_MANUAL help This string is placed in the 'board_id' CBFS file for indicating @@ -385,7 +384,7 @@ config BOOTSPLASH_IMAGE config BOOTSPLASH_FILE string "Bootsplash path and filename" depends on BOOTSPLASH_IMAGE - default "bootsplash.jpg" + # Default value set at the end of the file help The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. @@ -407,9 +406,9 @@ config DEVICETREE Examples: "devicetree.variant.cb" "variant/devicetree.cb" -# defaults for CBFS_SIZE are set at the end of the file. config CBFS_SIZE hex "Size of CBFS filesystem in ROM" + # Default value set at the end of the file help This is the part of the ROM actually managed by CBFS, located at the end of the ROM (passed through cbfstool -o) on x86 and at at the start @@ -1229,14 +1228,6 @@ config MAX_REBOOT_CNT with the normal image enabled before assuming the normal image is defective and switching to the fallback image. -config CBFS_SIZE - hex - default ROM_SIZE - help - This is the part of the ROM actually managed by CBFS. Set it to be - equal to the full ROM size if that hasn't been overridden by the - chipset or mainboard. - config CREATE_BOARD_CHECKLIST bool default n @@ -1280,3 +1271,28 @@ config RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y + +############################################################################### +# Set default values for symbols created before mainboards. This allows the +# option to be displayed in the general menu, but the default to be loaded in +# the mainboard if desired. +config COMPRESS_RAMSTAGE + default y if !UNCOMPRESSED_RAMSTAGE + +config COMPRESS_PRERAM_STAGES + depends on !ARCH_X86 + default y + +config INCLUDE_CONFIG_FILE + default y + +config BOARD_ID_STRING + default "(none)" + depends on BOARD_ID_MANUAL + +config BOOTSPLASH_FILE + depends on BOOTSPLASH_IMAGE + default "bootsplash.jpg" + +config CBFS_SIZE + default ROM_SIZE

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New patch to review for coreboot: siemens/mc_apl1: Add new mainboard
by Mario Scheithauer 31 Jan '17

31 Jan '17

Mario Scheithauer (mario.scheithauer(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18272 -gerrit commit fe26c636964e81a5f2afb69145cf50b13e15c614 Author: Mario Scheithauer <mario.scheithauer(a)siemens.com> Date: Tue Jan 31 15:45:13 2017 +0100 siemens/mc_apl1: Add new mainboard This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- src/mainboard/siemens/mc_apl1/Kconfig | 21 +++ src/mainboard/siemens/mc_apl1/Kconfig.name | 3 + src/mainboard/siemens/mc_apl1/Makefile.inc | 3 + src/mainboard/siemens/mc_apl1/acpi_tables.c | 14 ++ src/mainboard/siemens/mc_apl1/board_info.txt | 4 + src/mainboard/siemens/mc_apl1/bootblock.c | 22 +++ src/mainboard/siemens/mc_apl1/brd_gpio.h | 62 ++++++++ src/mainboard/siemens/mc_apl1/devicetree.cb | 230 +++++++++++++++++++++++++++ src/mainboard/siemens/mc_apl1/dsdt.asl | 42 +++++ src/mainboard/siemens/mc_apl1/mainboard.c | 25 +++ src/mainboard/siemens/mc_apl1/mc_apl1.fmd | 40 +++++ src/mainboard/siemens/mc_apl1/romstage.c | 119 ++++++++++++++ 12 files changed, 585 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig new file mode 100644 index 0000000..f7db44e --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -0,0 +1,21 @@ +if BOARD_SIEMENS_MC_APL1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default siemens/mc_apl1 + +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "MC APL1" + +endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name new file mode 100644 index 0000000..4e9796a --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_SIEMENS_MC_APL1 + bool "MC APL1" + diff --git a/src/mainboard/siemens/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/Makefile.inc new file mode 100644 index 0000000..9e3e892 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/acpi_tables.c b/src/mainboard/siemens/mc_apl1/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/siemens/mc_apl1/board_info.txt b/src/mainboard/siemens/mc_apl1/board_info.txt new file mode 100644 index 0000000..01963ec --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/board_info.txt @@ -0,0 +1,4 @@ +Board name: MC APL1 +Category: misc +ROM protocol: SPI +ROM socketed: no diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c new file mode 100644 index 0000000..3de44a8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/lpc.h> + +void bootblock_mainboard_init(void) +{ + lpc_configure_pads(); +} diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h new file mode 100644 index 0000000..33b839b --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb new file mode 100644 index 0000000..2ccf277 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -0,0 +1,230 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_122" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C0 for audio codec at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }" + + # Enable I2C2 bus early for TPM at 400kHz + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 57, + .fall_time_ns = 28, + }" + + # touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }" + + # trackpad at 400kHz + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 114, + .fall_time_ns = 164, + }" + + # digitizer at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on + chip drivers/i2c/wacom + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_DT_DESC, + .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl new file mode 100644 index 0000000..004523a --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c new file mode 100644 index 0000000..f7a2ef1 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + /* Nothing Here Yet */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd new file mode 100644 index 0000000..3da8467 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + WP_RO@0x0 0x400000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x1ff000 + RO_VPD@0x200000 0x4000 + RO_SECTION@0x204000 0x1fc000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x1bb000 + RO_UNUSED@0x1bc000 0x40000 + } + } + MISC_RW@0x400000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c new file mode 100644 index 0000000..5c784ba --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + memupd->FspmConfig.Package = 0x1; + memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LASR = 0x0; + memupd->FspmConfig.ScramblerSupport = 0x1; + memupd->FspmConfig.ChannelHashMask = 0x36; + memupd->FspmConfig.SliceHashMask = 0x9; + memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ChannelsSlicesEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.RmtMode = 0x0; + memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.LowMemoryMaxValue = 0x0; + memupd->FspmConfig.DisableFastBoot = 0x0; + memupd->FspmConfig.HighMemoryMaxValue = 0x0; + memupd->FspmConfig.DIMM0SPDAddress = 0x0; + memupd->FspmConfig.DIMM1SPDAddress = 0x0; + memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; + memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_Option = 0x3; + memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_TristateClk1 = 0x0; + memupd->FspmConfig.Ch0_Mode2N = 0x0; + memupd->FspmConfig.Ch0_OdtLevels = 0x0; + memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; + memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_Option = 0x3; + memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_TristateClk1 = 0x0; + memupd->FspmConfig.Ch1_Mode2N = 0x0; + memupd->FspmConfig.Ch1_OdtLevels = 0x0; + memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; + memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_Option = 0x3; + memupd->FspmConfig.Ch2_OdtConfig = 0x0; + memupd->FspmConfig.Ch2_TristateClk1 = 0x0; + memupd->FspmConfig.Ch2_Mode2N = 0x0; + memupd->FspmConfig.Ch2_OdtLevels = 0x0; + memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; + memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_Option = 0x3; + memupd->FspmConfig.Ch3_OdtConfig = 0x0; + memupd->FspmConfig.Ch3_TristateClk1 = 0x0; + memupd->FspmConfig.Ch3_Mode2N = 0x0; + memupd->FspmConfig.Ch3_OdtLevels = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.MrcDataSaving = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x0; + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; +}

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Patch merged into coreboot/master: mainboard/google/reef: remove NHLT DMIC 1ch and 2ch configuration
by gerrit＠coreboot.org 31 Jan '17

31 Jan '17

the following patch was just integrated into master: commit 545edca5779c2f6b057fc38f6371351ea762c5bd Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Fri Jan 27 14:51:59 2017 -0800 mainboard/google/reef: remove NHLT DMIC 1ch and 2ch configuration Apollolake boards should use DMIC-4ch configuration in Kernel side and use CaptureChannelMap in userspace to distinguish boards with different number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will not be required and hence removed. BUG=chrome-os-partner:60827 TEST=Verify internal mic capture TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Reviewed-on: https://review.coreboot.org/18252 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18252 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: Set edge triggered interrupt for GPIO_22
by gerrit＠coreboot.org 31 Jan '17

31 Jan '17

the following patch was just integrated into master: commit 6e5609124eb98b2f3e33fcec994b7d1b00a355ef Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Jan 30 12:18:42 2017 -0800 mainboard/google/reef: Set edge triggered interrupt for GPIO_22 EC sets the logic level based on outstanding wake events. When GPIO_22 is configured as a level triggered interrupt, the events are not cleared from the interrupt handler. Hence, we'd just be re-signalling over and over causing an interrupt storm upon lid open. So, GPIO_22 needs to be configured as EDGE_SINGLE instead of LEVEL. BUG=chrome-os-partner:62458 TEST=Lid close/open. check CPU usage using top. It should not show 70% CPU usage. Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a Reviewed-on: https://review.coreboot.org/18267 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18267 for details. -gerrit

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Patch set updated for coreboot: ddr3 spd: move accessor code into lib/spd_bin.c
by Patrick Georgi 31 Jan '17

31 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18265 -gerrit commit 71883d163d3862ba934ea243164cda4d389b4cef Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 15:59:25 2017 +0100 ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/Kconfig | 4 -- src/device/dram/Makefile.inc | 2 +- src/device/dram/spd_cache.c | 70 ----------------------------- src/include/spd_bin.h | 3 ++ src/include/spd_cache.h | 26 ----------- src/lib/Makefile.inc | 2 +- src/lib/spd_bin.c | 49 ++++++++++++++++++++ src/mainboard/amd/db-ft3b-lc/Kconfig | 1 - src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e20XX/Kconfig | 1 - src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/Kconfig | 1 - src/mainboard/gizmosphere/gizmo/Kconfig | 1 - src/mainboard/gizmosphere/gizmo2/Kconfig | 1 - src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu1/Kconfig | 1 - src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu2/Kconfig | 1 - src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/pi/def_callouts.c | 2 +- 20 files changed, 60 insertions(+), 115 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..4036a3d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -210,10 +210,6 @@ config SMBUS_HAS_AUX_CHANNELS bool default n -config SPD_CACHE - bool - default n - config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..b1a6755 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-y += ddr3.c diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c deleted file mode 100644 index 69cfc24..0000000 --- a/src/device/dram/spd_cache.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <device/dram/ddr3.h> -#include <spd_cache.h> -#include <stdint.h> -#include <string.h> - -int read_ddr3_spd_from_cbfs(u8 *buf, int idx) -{ - const int SPD_CRC_HI = 127; - const int SPD_CRC_LO = 126; - - const char *spd_file; - size_t spd_file_len = 0; - size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - - if (CONFIG_DIMM_SPD_SIZE != 128) { - printk(BIOS_EMERG, - "SPD size configured to 0x%x (!= 128) bytes\n", - CONFIG_DIMM_SPD_SIZE); - return -1; - } - - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); - if (spd_file_len < min_len) - printk(BIOS_EMERG, "Missing SPD data."); - if (!spd_file || spd_file_len < min_len) - return -1; - - memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); - - if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) - || (buf[SPD_CRC_LO] != (crc & 0xff)) - || (buf[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", - buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); - buf[SPD_CRC_LO] = crc & 0xff; - buf[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ", i); - printk(BIOS_WARNING, "%02x ", buf[i]); - } - printk(BIOS_WARNING, "\n"); - } - return 0; -} diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index a0c1bbd..60be868 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -54,4 +54,7 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and + verifies the checksum. */ +int read_ddr3_spd_from_cbfs(u8 *buf, int idx); #endif diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h deleted file mode 100644 index 912aa64..0000000 --- a/src/include/spd_cache.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPD_CACHE_H_ -#define _SPD_CACHE_H_ - -#include <stdint.h> - -#if IS_ENABLED(CONFIG_SPD_CACHE) -int read_ddr3_spd_from_cbfs(u8 *buf, int idx); -#else -static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; } -#endif - -#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9a9ddc8..37aa706 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -287,7 +287,7 @@ ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb endif # CONFIG_RAMSTAGE_LIBHWBASE -romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c +romstage-y += spd_bin.c LIB_SPD_BIN = $(obj)/spd.bin diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 4108839..1d6c5ae 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -19,6 +19,7 @@ #include <spd_bin.h> #include <string.h> #include <device/early_smbus.h> +#include <device/dram/ddr3.h> static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; @@ -164,3 +165,51 @@ void get_spd_smbus(struct spd_block *blk) update_spd_len(blk); } + +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) +{ + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; + + if (CONFIG_DIMM_SPD_SIZE != 128) { + printk(BIOS_EMERG, + "SPD size configured to 0x%x (!= 128) bytes\n", + CONFIG_DIMM_SPD_SIZE); + return -1; + } + + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", + buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ", i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index 7bf3c86..3999039 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 2ceb5c8..e6773b8 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -24,7 +24,7 @@ #include "imc.h" #endif #include <stdlib.h> -#include <spd_cache.h> +#include <spd_bin.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ee26772..6631ac8 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select SUPERIO_FINTEK_F81866D - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 10ec422..9b241fc 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -25,7 +25,7 @@ #endif #include "hudson.h" #include <stdlib.h> -#include <spd_cache.h> +#include <spd_bin.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 60a59ac..c8472c4 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select GFXUMA select SUPERIO_FINTEK_F81866D - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 8109019..4177b1d 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 349f827..f5509f6 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index f35cbd2..7604277 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <spd_cache.h> +#include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "heapManager.h" #include "SB800.h" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index f882b78..5e927cc 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 221b315..ab9d521 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <spd_cache.h> +#include <spd_bin.h> #include <northbridge/amd/pi/BiosCallOuts.h> #include "Ids.h" #include "OptionsIds.h" diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index de42721..4303b84 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 - select SPD_CACHE select HUDSON_DISABLE_IMC select USE_BLOBS diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 953774a..0805c02 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -15,7 +15,7 @@ */ #include <cbfs.h> -#include <spd_cache.h> +#include <spd_bin.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index e38d807..6b8aaee 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -15,7 +15,7 @@ */ #include <cbfs.h> -#include <spd_cache.h> +#include <spd_bin.h> #include "AGESA.h" #include "amdlib.h"

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Patch set updated for coreboot: ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()
by Patrick Georgi 31 Jan '17

31 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18264 -gerrit commit 5683bc17ab2ccf3906d805cebc1837957c79ce3a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 15:26:43 2017 +0100 ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs() Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/dram/spd_cache.c | 18 +++++++++++------- src/include/spd_cache.h | 4 ++-- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +- src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/pi/def_callouts.c | 2 +- 8 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index 3bdd9c1..69cfc24 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -21,18 +21,22 @@ #include <stdint.h> #include <string.h> -#define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 - -_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); - -int read_spd_from_cbfs(u8 *buf, int idx) +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + const char *spd_file; size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; + if (CONFIG_DIMM_SPD_SIZE != 128) { + printk(BIOS_EMERG, + "SPD size configured to 0x%x (!= 128) bytes\n", + CONFIG_DIMM_SPD_SIZE); + return -1; + } + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); if (!spd_file) diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h index 669639b..912aa64 100644 --- a/src/include/spd_cache.h +++ b/src/include/spd_cache.h @@ -18,9 +18,9 @@ #include <stdint.h> #if IS_ENABLED(CONFIG_SPD_CACHE) -int read_spd_from_cbfs(u8 *buf, int idx); +int read_ddr3_spd_from_cbfs(u8 *buf, int idx); #else -static inline int read_spd_from_cbfs(u8 *buf, int idx) { return -1; } +static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; } #endif #endif diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 9880b60..2ceb5c8 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -239,7 +239,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 41603da..10ec422 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -328,7 +328,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 536ec5f..f35cbd2 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -63,7 +63,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index fe64d64..221b315 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -141,7 +141,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index a2e12a9..953774a 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -143,7 +143,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 61b5c8b..e38d807 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -132,7 +132,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS;

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coreboot-gerrit January 2017