coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/intel/x4x: Refactor dram freq and cas selection
by Arthur Heymans 30 Jan '17

30 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18156 -gerrit commit ac5293ba5c940df2edc2d9914c645f9f122676d8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 16 23:32:02 2017 +0100 nb/intel/x4x: Refactor dram freq and cas selection The code did not check for tAC and for tCLK potentially selected the wrong spd offset for minimum cycle time. Adds some debugging output for freq and cas selection. The code is also written to be easily extendable for officially unsported dram frequencies like 533MHz and 400MHz which some vendor bios seem to support. Change-Id: Ie0d8326af50d3125bf35918ba645a6df27dd2ee4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 127 +++++++++++++++++++++++------------- 1 file changed, 83 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..1a7ee46 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -160,13 +160,6 @@ static void sdram_read_spds(struct sysinfo *s) } } -static u8 msbpos(u8 val) //Reverse -{ - u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); - return i; -} - static void mchinfo_ddr2(struct sysinfo *s) { const u32 eax = cpuid_ext(0x04, 0).eax; @@ -195,17 +188,46 @@ static void mchinfo_ddr2(struct sysinfo *s) } } +/* Decode tclk to picoseconds */ +static int decode_tclk(u8 spd_data) +{ + int high_nibble = (spd_data >> 4) * 1000; + int low_nibble; + if ((spd_data & 0xf) > 0x9) /* Should be < 0xd */ + low_nibble = ((spd_data & 0xf) - 0x9) * 250; + else + low_nibble = spd_data * 100; + return high_nibble + low_nibble; +} + static void sdram_detect_ram_speed(struct sysinfo *s) { - u8 i; + u8 i, j; u8 commoncas = 0; + u8 highest_commoncas; u8 currcas; u8 currfreq; u8 maxfreq; u8 freq = 0; + u8 high_cas; + u8 spd_tclk_lat[TOTAL_DIMMS][8]; + u8 spd_tac_lat[TOTAL_DIMMS][8]; + u8 tclk, tclk_target; + u8 tac, tac_target; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + 0x25, 0x40, /* DDR2 800: tCLK = 2.5ns tAC = 0.40ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD, + }; - // spdidx,cycletime @CAS 5 6 - u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}}; int found = 0; // Find max FSB speed @@ -225,57 +247,74 @@ static void sdram_detect_ram_speed(struct sysinfo *s) break; } - // Max RAM speed if (s->spd_type == DDR2) { - - maxfreq = MEM_CLOCK_800MHz; - - // Choose common CAS latency from {6,5}, 4 does not work - commoncas = 0x60; - + /* Only CAS 5 and 6 are supported */ + commoncas = SPD_CAS_LATENCY_DDR2_6 | SPD_CAS_LATENCY_DDR2_5; FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_7) { + high_cas = 7; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_6) { + high_cas = 6; + } else if (s->dimms[i].cas_latencies & SPD_CAS_LATENCY_DDR2_5) { + high_cas = 5; + } /* Don't check for lower CAS since not supported */ commoncas &= s->dimms[i].cas_latencies; + for (j = 0; j < 3; i++) { + spd_tclk_lat[i][high_cas - j] = s->dimms[i].spd_data[spd_lookup_table[2 * j]]; + spd_tac_lat[i][high_cas - j] = s->dimms[i].spd_data[spd_lookup_table[2 * j + 1]]; + } } - if (commoncas == 0) { + if (commoncas == 0) die("No common CAS among dimms\n"); - } + else if (commoncas & SPD_CAS_LATENCY_DDR2_6) + highest_commoncas = 6; + else + highest_commoncas = 5; + + /* + * FIXME: datasheets say only 667MHz and 800MHz are supported + * but vendor bios also supports 533MHz and possibly 400MHz + */ + /* Test from higher to lower frequency, from lower to higher CAS latency */ + for (currfreq = MEM_CLOCK_800MHz; currfreq >= MEM_CLOCK_667MHz; currfreq--) { + printk(BIOS_DEBUG, "Trying DDR2: "); + switch (currfreq) { + case MEM_CLOCK_400MHz: + printk(BIOS_DEBUG, "%dMHz\n", 400); + case MEM_CLOCK_533MHz: + printk(BIOS_DEBUG, "%dMHz\n", 533); + case MEM_CLOCK_667MHz: + printk(BIOS_DEBUG, "%dMHz\n", 667); + case MEM_CLOCK_800MHz: + printk(BIOS_DEBUG, "%dMHz\n", 800); + } - // Working from fastest to slowest, - // fast->slow 5@800 6@800 5@667 - found = 0; - for (currcas = 5; currcas <= msbpos(commoncas); currcas++) { - currfreq = maxfreq; - if (currfreq == MEM_CLOCK_800MHz) { + for (currcas = 5; currcas <= highest_commoncas; currcas++) { + printk(BIOS_DEBUG, " Trying CAS: %d\n", currcas); found = 1; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) { - // this is too fast + tclk = decode_tclk(spd_tclk_lat[i][currcas]); + tclk_target = ddr2_speeds_table[2 * currfreq]; + tac = spd_tac_lat[i][currcas]; + tac_target = ddr2_speeds_table[2 * currfreq + 1]; + printk(BIOS_DEBUG, " tCLK: %dps , tCLK_target: %dps\n", tclk, tclk_target); + printk(BIOS_DEBUG, " tAC: 0.%xns , tAC_target: 0.%xns\n", tac, tac_target); + if ((tclk > tclk_target) && (tac > tac_target)) { + printk(BIOS_DEBUG, " Timing too fast\n"); found = 0; + break; /* No need to check other dimms for these timings */ } } - if (found) - break; - } - } - - if (!found) { - currcas = 5; - currfreq = MEM_CLOCK_667MHz; - found = 1; - FOR_EACH_POPULATED_DIMM(s->dimms, i) { - if (s->dimms[i].spd_data[9] > 0x30) { - // this is too fast - found = 0; + if (found) { + s->selected_timings.mem_clk = currfreq; + s->selected_timings.CAS = currcas; + return; } } } - if (!found) die("No valid CAS/frequencies detected\n"); - s->selected_timings.mem_clk = currfreq; - s->selected_timings.CAS = currcas; - } else { // DDR3 // Limit frequency for MCH maxfreq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;

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New patch to review for coreboot: google/veyron*: mark GPIO array non-static
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18266 -gerrit commit c5ade8e87bbb42eff659ad594fcd24b3c3d140fd Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 17:53:34 2017 +0100 google/veyron*: mark GPIO array non-static That status isn't needed and making it non-static helps gcc 4.9.2 (or any compiler that insists on "standard C" behaviour with global const initializers) Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/mainboard/google/veyron/boardid.c | 4 ++-- src/mainboard/google/veyron_mickey/boardid.c | 4 ++-- src/mainboard/google/veyron_rialto/boardid.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index d0456d7..a610471 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -21,7 +21,7 @@ uint8_t board_id(void) { static int id = -1; - static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ if (id < 0) { @@ -35,7 +35,7 @@ uint8_t board_id(void) uint32_t ram_code(void) { uint32_t code; - static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ code = gpio_base2_value(pins, ARRAY_SIZE(pins)); diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index d0456d7..a610471 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -21,7 +21,7 @@ uint8_t board_id(void) { static int id = -1; - static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ if (id < 0) { @@ -35,7 +35,7 @@ uint8_t board_id(void) uint32_t ram_code(void) { uint32_t code; - static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ code = gpio_base2_value(pins, ARRAY_SIZE(pins)); diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index d0456d7..a610471 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -21,7 +21,7 @@ uint8_t board_id(void) { static int id = -1; - static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ if (id < 0) { @@ -35,7 +35,7 @@ uint8_t board_id(void) uint32_t ram_code(void) { uint32_t code; - static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ code = gpio_base2_value(pins, ARRAY_SIZE(pins));

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Patch set updated for coreboot: mb/lenovo/t400: Implement hybrid graphic in romstage
by Patrick Rudolph 30 Jan '17

30 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18010 -gerrit commit 13a7e9fe4a1117722e5b150cb3f40afd406bd4ed Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 2 16:16:45 2017 +0100 mb/lenovo/t400: Implement hybrid graphic in romstage The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work for t400/t500. Replace it with a custom romstage implementation. Tested on Lenovo T500 with dual graphics: * Intel Native GFX init * AMD VBios * GNU Linux 4.8.13 * SeaBios as payload * Discrete is working (44 W) * Integrated is working (24 W) * Switchable is working (34 W) ** Both GPUs are enabled, with Intel being connected to the panel ** DRI_PRIME allows to use AMD GPU ** ACPI doesn't seem to work (no vgaswitcheroo) Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/Kconfig | 1 - src/mainboard/lenovo/t400/Makefile.inc | 1 + src/mainboard/lenovo/t400/cmos.layout | 1 + src/mainboard/lenovo/t400/hybrid_graphics.c | 90 +++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/romstage.c | 10 +++- 5 files changed, 100 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f21f672..150199e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b382efb..c02a70b 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -15,3 +15,4 @@ ramstage-y += dock.c ramstage-y += cstates.c +romstage-y += hybrid_graphics.c diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..cf31453 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -142,6 +142,7 @@ enumerations 11 12 352M 12 0 Integrated Only 12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/hybrid_graphics.c b/src/mainboard/lenovo/t400/hybrid_graphics.c new file mode 100644 index 0000000..ad1c00f --- /dev/null +++ b/src/mainboard/lenovo/t400/hybrid_graphics.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/gm45/gm45.h> +#include <console/console.h> +#include <option.h> + +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define MUX_GPIO 22 +#define BCL_CTL_GPIO 19 +#define GFX_PWR_EN_GPIO 49 + +#define HYBRID_DETECT_GPIO 21 + +void hybrid_graphics_init(sysinfo_t *sysinfo); + +static bool hybrid_graphics_installed(void) +{ + if (get_gpio(HYBRID_DETECT_GPIO)) + return false; + else + return true; +} + +void hybrid_graphics_init(sysinfo_t *sysinfo) +{ + /* Set default mode */ + uint8_t hybrid_graphics_mode = 0; + + if (!hybrid_graphics_installed()) { + printk(BIOS_DEBUG, "Hybrid graphics not installed.\n"); + /* The display is not connected to a mux or switchable. */ + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + return; + } + + printk(BIOS_DEBUG, "Hybrid graphics available: "); + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + + /* Select appropriate hybrid graphics device */ + switch (hybrid_graphics_mode) { + default: + case HYBRID_GRAPHICS_INTEGRATED_ONLY: + printk(BIOS_DEBUG, "Activating Integrated Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_LOW); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + break; + case HYBRID_GRAPHICS_DISCRETE_ONLY: + printk(BIOS_DEBUG, "Activating Discrete Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_HIGH); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_HIGH); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + break; + case HYBRID_GRAPHICS_SWITCHABLE: + printk(BIOS_DEBUG, "Activating Switchable (both GPUs).\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 1; + break; + } +} diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index d110d4f..2a3a770 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -36,6 +36,8 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +void hybrid_graphics_init(sysinfo_t *sysinfo); + static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -101,9 +103,13 @@ void mainboard_romstage_entry(unsigned long bist) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); + + /* Configure graphic GPIOs. + * Make sure there's a little delay between + * setup_pch_gpios() and this call ! */ + hybrid_graphics_init(&sysinfo); + raminit(&sysinfo, s3resume); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);

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Patch merged into coreboot/master: vboot: Add mock functions for recovery space read/write
by gerrit＠coreboot.org 30 Jan '17

30 Jan '17

the following patch was just integrated into master: commit 775765eaf30a6e3cef6e49f4119967a09841c214 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Jan 26 15:33:01 2017 -0800 vboot: Add mock functions for recovery space read/write For the boards that intend to use mock tpm and have recovery mrc cache support enabled, provide mock functions to read and write mrc hash space. Reading MRC hash space returns TPM_SUCCESS as later checks take care of comparing the hash value and retraining if hash comparison fails. Thus, in case of mock tpm, device would always end up doing the memory retraining in recovery mode. BUG=chrome-os-partner:62413 BRANCH=None TEST=Verified that eve builds with mock tpm selected. Change-Id: I7817cda7821fadeea0e887cb9860804256dabfd9 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18248 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18248 for details. -gerrit

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New patch to review for coreboot: ddr3 spd: move accessor code into lib/spd_bin.c
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18265 -gerrit commit 4d6a746bff9c83d991cbac957c3d206752c27d57 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 15:59:25 2017 +0100 ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/Kconfig | 4 -- src/device/dram/Makefile.inc | 2 +- src/device/dram/spd_cache.c | 70 ----------------------------- src/include/spd_bin.h | 3 ++ src/include/spd_cache.h | 26 ----------- src/lib/Makefile.inc | 2 +- src/lib/spd_bin.c | 49 ++++++++++++++++++++ src/mainboard/amd/db-ft3b-lc/Kconfig | 1 - src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e20XX/Kconfig | 1 - src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/Kconfig | 1 - src/mainboard/gizmosphere/gizmo/Kconfig | 1 - src/mainboard/gizmosphere/gizmo2/Kconfig | 1 - src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu1/Kconfig | 1 - src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu2/Kconfig | 1 - src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/pi/def_callouts.c | 2 +- 20 files changed, 60 insertions(+), 115 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..4036a3d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -210,10 +210,6 @@ config SMBUS_HAS_AUX_CHANNELS bool default n -config SPD_CACHE - bool - default n - config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..b1a6755 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-y += ddr3.c diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c deleted file mode 100644 index 69cfc24..0000000 --- a/src/device/dram/spd_cache.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <device/dram/ddr3.h> -#include <spd_cache.h> -#include <stdint.h> -#include <string.h> - -int read_ddr3_spd_from_cbfs(u8 *buf, int idx) -{ - const int SPD_CRC_HI = 127; - const int SPD_CRC_LO = 126; - - const char *spd_file; - size_t spd_file_len = 0; - size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - - if (CONFIG_DIMM_SPD_SIZE != 128) { - printk(BIOS_EMERG, - "SPD size configured to 0x%x (!= 128) bytes\n", - CONFIG_DIMM_SPD_SIZE); - return -1; - } - - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); - if (spd_file_len < min_len) - printk(BIOS_EMERG, "Missing SPD data."); - if (!spd_file || spd_file_len < min_len) - return -1; - - memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); - - if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) - || (buf[SPD_CRC_LO] != (crc & 0xff)) - || (buf[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", - buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); - buf[SPD_CRC_LO] = crc & 0xff; - buf[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ", i); - printk(BIOS_WARNING, "%02x ", buf[i]); - } - printk(BIOS_WARNING, "\n"); - } - return 0; -} diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index a0c1bbd..60be868 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -54,4 +54,7 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and + verifies the checksum. */ +int read_ddr3_spd_from_cbfs(u8 *buf, int idx); #endif diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h deleted file mode 100644 index 912aa64..0000000 --- a/src/include/spd_cache.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPD_CACHE_H_ -#define _SPD_CACHE_H_ - -#include <stdint.h> - -#if IS_ENABLED(CONFIG_SPD_CACHE) -int read_ddr3_spd_from_cbfs(u8 *buf, int idx); -#else -static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; } -#endif - -#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9a9ddc8..37aa706 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -287,7 +287,7 @@ ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb endif # CONFIG_RAMSTAGE_LIBHWBASE -romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c +romstage-y += spd_bin.c LIB_SPD_BIN = $(obj)/spd.bin diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 4108839..1d6c5ae 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -19,6 +19,7 @@ #include <spd_bin.h> #include <string.h> #include <device/early_smbus.h> +#include <device/dram/ddr3.h> static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; @@ -164,3 +165,51 @@ void get_spd_smbus(struct spd_block *blk) update_spd_len(blk); } + +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) +{ + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; + + if (CONFIG_DIMM_SPD_SIZE != 128) { + printk(BIOS_EMERG, + "SPD size configured to 0x%x (!= 128) bytes\n", + CONFIG_DIMM_SPD_SIZE); + return -1; + } + + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", + buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ", i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index 7bf3c86..3999039 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 2ceb5c8..e6773b8 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -24,7 +24,7 @@ #include "imc.h" #endif #include <stdlib.h> -#include <spd_cache.h> +#include <spd_bin.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ee26772..6631ac8 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select SUPERIO_FINTEK_F81866D - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 10ec422..9b241fc 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -25,7 +25,7 @@ #endif #include "hudson.h" #include <stdlib.h> -#include <spd_cache.h> +#include <spd_bin.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 60a59ac..c8472c4 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select GFXUMA select SUPERIO_FINTEK_F81866D - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 8109019..4177b1d 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 349f827..f5509f6 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index f35cbd2..7604277 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <spd_cache.h> +#include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "heapManager.h" #include "SB800.h" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index f882b78..5e927cc 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 221b315..ab9d521 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <spd_cache.h> +#include <spd_bin.h> #include <northbridge/amd/pi/BiosCallOuts.h> #include "Ids.h" #include "OptionsIds.h" diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index de42721..4303b84 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 - select SPD_CACHE select HUDSON_DISABLE_IMC select USE_BLOBS diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 953774a..0805c02 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -15,7 +15,7 @@ */ #include <cbfs.h> -#include <spd_cache.h> +#include <spd_bin.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index e38d807..6b8aaee 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -15,7 +15,7 @@ */ #include <cbfs.h> -#include <spd_cache.h> +#include <spd_bin.h> #include "AGESA.h" #include "amdlib.h"

1 0

New patch to review for coreboot: ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18264 -gerrit commit ec5ea87b6ad0113cfc0897a5a38701de1f0aa784 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 15:26:43 2017 +0100 ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs() Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/dram/spd_cache.c | 18 +++++++++++------- src/include/spd_cache.h | 4 ++-- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +- src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/pi/def_callouts.c | 2 +- 8 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index 3bdd9c1..69cfc24 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -21,18 +21,22 @@ #include <stdint.h> #include <string.h> -#define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 - -_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); - -int read_spd_from_cbfs(u8 *buf, int idx) +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + const char *spd_file; size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; + if (CONFIG_DIMM_SPD_SIZE != 128) { + printk(BIOS_EMERG, + "SPD size configured to 0x%x (!= 128) bytes\n", + CONFIG_DIMM_SPD_SIZE); + return -1; + } + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); if (!spd_file) diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h index 669639b..912aa64 100644 --- a/src/include/spd_cache.h +++ b/src/include/spd_cache.h @@ -18,9 +18,9 @@ #include <stdint.h> #if IS_ENABLED(CONFIG_SPD_CACHE) -int read_spd_from_cbfs(u8 *buf, int idx); +int read_ddr3_spd_from_cbfs(u8 *buf, int idx); #else -static inline int read_spd_from_cbfs(u8 *buf, int idx) { return -1; } +static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; } #endif #endif diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 9880b60..2ceb5c8 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -239,7 +239,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 41603da..10ec422 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -328,7 +328,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 536ec5f..f35cbd2 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -63,7 +63,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index fe64d64..221b315 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -141,7 +141,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index a2e12a9..953774a 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -143,7 +143,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 61b5c8b..e38d807 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -132,7 +132,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS;

1 0

New patch to review for coreboot: build system: mark sub-make invocations as parallelizable
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18263 -gerrit commit 20b6def890edea70c067c9f5738d28cdf0d920e6 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 15:29:34 2017 +0100 build system: mark sub-make invocations as parallelizable We rely on gnu make, so we can expect the jobserver to be around in parallel builds, too. Avoids some make warnings and slightly speeds up the build if those sub-makes are executed (eg for arm-trusted-firmware and vboot). Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile | 2 +- Makefile.inc | 4 ++-- src/arch/arm64/Makefile.inc | 4 ++-- src/vboot/Makefile.inc | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 2973030..4a05890 100644 --- a/Makefile +++ b/Makefile @@ -168,7 +168,7 @@ real-all: real-target .SECONDEXPANSION: $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) - $(MAKE) oldconfig + +$(MAKE) oldconfig # Add a new class of source/object files to the build system add-class= \ diff --git a/Makefile.inc b/Makefile.inc index d609ac4..2267f32 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -274,7 +274,7 @@ cbfs-files-processor-vsa= \ # arg2: output cbfs-files-processor-defconfig= \ $(eval $(2): $(1) $(obj)/build.h; \ - printf " CREATE $(2) (from $(1))\n"; \ + +printf " CREATE $(2) (from $(1))\n"; \ printf "\# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ $(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \ @@ -486,7 +486,7 @@ $(ROMCC_BIN): $(top)/util/romcc/romcc.c IFDTOOL:=$(objutil)/ifdtool/ifdtool $(IFDTOOL): @printf " Compile IFDTOOL\n" - $(MAKE) -C $(top)/util/ifdtool + +$(MAKE) -C $(top)/util/ifdtool cp -a $(top)/util/ifdtool/ifdtool $@ IFDFAKE:=$(objutil)/ifdfake/ifdfake diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 78ea427..c6c0280 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -172,8 +172,8 @@ BL31_LDFLAGS := --emit-relocs BL31 := $(obj)/bl31.elf $(BL31): $(obj)/build.h - @printf " MAKE $(subst $(obj)/,,$(@))\n" - CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ + printf " MAKE $(subst $(obj)/,,$(@))\n" + +CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ CFLAGS="$(BL31_CFLAGS)" \ LDFLAGS="$(BL31_LDFLAGS)" \ $(MAKE) -C $(BL31_SOURCE) $(BL31_MAKEARGS) $(BL31_TARGET) diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index c03d639..fb373c3 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -95,8 +95,8 @@ VBOOT_CFLAGS += -I$(abspath $(obj)) -include $(top)/src/include/kconfig.h -Wno-m VBOOT_CFLAGS += -DVBOOT_DEBUG $(VB2_LIB): $(obj)/config.h - @printf " MAKE $(subst $(obj)/,,$(@))\n" - $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ CC="$(CC_verstage)" \ CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ $(MAKE) -C $(VBOOT_SOURCE) \

1 0

New patch to review for coreboot: util/xcompile: parallelize compiler checks
by Patrick Georgi 30 Jan '17

30 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18262 -gerrit commit fdb63e7cf38c114ced67a6f3d03fbeb442376876 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 30 15:27:35 2017 +0100 util/xcompile: parallelize compiler checks Speed up the execution of this script from ~6 seconds to ~1 on my system. There are some changes to its output, but they're actually _more_ correct: so far, architectures without compiler support kept compiler options for architectures that ran successfully earlier. Change-Id: I0532ea2178fbedb114a75cfd5ba39301e534e742 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/xcompile/xcompile | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 90220f6..ec295a9 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -58,7 +58,7 @@ clean_up() { # Create temporary file(s). TMPFILE="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" -touch "$TMPFILE" +rm -f "$TMPFILE" trap clean_up EXIT @@ -438,11 +438,24 @@ test_architecture() { fi } -# This loops over all supported architectures. +OUT="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" +rm -f $OUT + for architecture in $SUPPORTED_ARCHITECTURES; do + ( + TMPFILE="$(mktemp /tmp/temp.XXXXXX 2>/dev/null || echo /tmp/temp.coreboot.$RANDOM)" + touch $TMPFILE test_architecture "$architecture" detect_special_flags "$architecture" detect_compiler_runtime "$architecture" report_arch_toolchain + clean_up + ) > $OUT.$architecture & +done +wait + +for architecture in $SUPPORTED_ARCHITECTURES; do + cat $OUT.$architecture + rm -f $OUT.$architecture done echo XCOMPILE_COMPLETE:=1

1 0

New patch to review for coreboot: src/lib: Update Makefile to keep build/spd.bin rule private
by Martin Roth 30 Jan '17

30 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18261 -gerrit commit 39782a3a63deadb1734b7f0475a7af2a3e013b74 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 29 18:11:36 2017 -0700 src/lib: Update Makefile to keep build/spd.bin rule private The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin' implementation. It wasn't guarded though, so it was generating a build warning for any other platform that generated an spd.bin file. Sample warning that this fixes: src/mainboard/gizmosphere/gizmo/Makefile.inc:42: warning: overriding recipe for target 'build/spd.bin' src/lib/Makefile.inc:298: warning: ignoring old recipe for target 'build/spd.bin' Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/lib/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9a9ddc8..38b3c12 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -287,6 +287,7 @@ ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb endif # CONFIG_RAMSTAGE_LIBHWBASE +ifeq ($(CONFIG_GENERIC_SPD_BIN),y) romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c LIB_SPD_BIN = $(obj)/spd.bin @@ -304,3 +305,4 @@ $(LIB_SPD_BIN): $(LIB_SPD_DEPS) cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin spd.bin-file := $(LIB_SPD_BIN) spd.bin-type := spd +endif

1 0

Patch set updated for coreboot: Add Baytrail ChromeOS devices using variant scheme
by Matt DeVillier 30 Jan '17

30 Jan '17

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18164 -gerrit commit f91739ee9c524a1a3dac8c74760b70388e1bf0c2 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jan 16 17:32:38 2017 -0600 Add Baytrail ChromeOS devices using variant scheme Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty, heli, kip, orco, quawks, squawks, sumo, swanky, and winky using their common reference board (rambi) as a base. Chromium sources used: firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...] firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...] firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...] firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...] firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...] firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...] firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*] firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.] firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data] firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data] firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...] firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table] firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...] The same basic cleanup/changes are made here as with the initial BYT variant commit: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) - Micron 2GB SPD file for kip with updated values renamed to distinguish from same file used by other boards Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/rambi/Kconfig | 52 +++++ src/mainboard/google/rambi/Kconfig.name | 52 +++++ src/mainboard/google/rambi/Makefile.inc | 1 + .../google/rambi/acpi/touchscreen_amtel.asl | 56 ----- .../google/rambi/acpi/touchscreen_atmel.asl | 56 +++++ .../google/rambi/acpi/touchscreen_elan.asl | 53 +++++ .../google/rambi/acpi/touchscreen_wdt.asl | 53 +++++ src/mainboard/google/rambi/acpi/trackpad_amtel.asl | 53 ----- src/mainboard/google/rambi/acpi/trackpad_atmel.asl | 53 +++++ src/mainboard/google/rambi/mainboard.c | 2 +- src/mainboard/google/rambi/romstage.c | 8 +- .../spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex | 32 +++ .../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 ++ .../rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex | 32 +++ .../rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex | 32 +++ .../spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex | 16 ++ src/mainboard/google/rambi/spd/empty.spd.hex | 16 ++ .../spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex | 16 ++ .../micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex | 32 +++ .../spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex | 17 ++ .../google/rambi/variants/banjo/Makefile.inc | 45 ++++ .../google/rambi/variants/banjo/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/banjo/gpio.c | 229 ++++++++++++++++++++ .../variants/banjo/include/variant/acpi/dptf.asl | 41 ++++ .../banjo/include/variant/acpi/mainboard.asl | 17 ++ .../rambi/variants/banjo/include/variant/onboard.h | 33 +++ .../rambi/variants/banjo/include/variant/variant.h | 35 ++++ .../google/rambi/variants/candy/Makefile.inc | 58 ++++++ .../google/rambi/variants/candy/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/candy/gpio.c | 229 ++++++++++++++++++++ .../variants/candy/include/variant/acpi/dptf.asl | 41 ++++ .../candy/include/variant/acpi/mainboard.asl | 19 ++ .../rambi/variants/candy/include/variant/onboard.h | 39 ++++ .../rambi/variants/candy/include/variant/variant.h | 42 ++++ .../google/rambi/variants/clapper/Makefile.inc | 45 ++++ .../google/rambi/variants/clapper/devicetree.cb | 89 ++++++++ src/mainboard/google/rambi/variants/clapper/gpio.c | 230 ++++++++++++++++++++ .../variants/clapper/include/variant/acpi/dptf.asl | 29 +++ .../clapper/include/variant/acpi/mainboard.asl | 19 ++ .../variants/clapper/include/variant/onboard.h | 39 ++++ .../variants/clapper/include/variant/variant.h | 35 ++++ .../enguarde/include/variant/acpi/mainboard.asl | 2 - .../variants/enguarde/include/variant/onboard.h | 2 - .../google/rambi/variants/glimmer/Makefile.inc | 55 +++++ .../google/rambi/variants/glimmer/devicetree.cb | 98 +++++++++ src/mainboard/google/rambi/variants/glimmer/gpio.c | 231 +++++++++++++++++++++ .../variants/glimmer/include/variant/acpi/dptf.asl | 42 ++++ .../glimmer/include/variant/acpi/mainboard.asl | 19 ++ .../variants/glimmer/include/variant/onboard.h | 39 ++++ .../variants/glimmer/include/variant/variant.h | 42 ++++ .../google/rambi/variants/gnawty/Makefile.inc | 49 +++++ .../google/rambi/variants/gnawty/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/gnawty/gpio.c | 229 ++++++++++++++++++++ .../variants/gnawty/include/variant/acpi/dptf.asl | 41 ++++ .../gnawty/include/variant/acpi/mainboard.asl | 16 ++ .../variants/gnawty/include/variant/onboard.h | 39 ++++ .../variants/gnawty/include/variant/variant.h | 37 ++++ .../google/rambi/variants/heli/Makefile.inc | 55 +++++ .../google/rambi/variants/heli/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/heli/gpio.c | 228 ++++++++++++++++++++ .../variants/heli/include/variant/acpi/dptf.asl | 41 ++++ .../heli/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/heli/include/variant/onboard.h | 33 +++ .../rambi/variants/heli/include/variant/variant.h | 36 ++++ .../google/rambi/variants/kip/Makefile.inc | 49 +++++ .../google/rambi/variants/kip/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/kip/gpio.c | 230 ++++++++++++++++++++ .../variants/kip/include/variant/acpi/dptf.asl | 41 ++++ .../kip/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/kip/include/variant/onboard.h | 34 +++ .../rambi/variants/kip/include/variant/variant.h | 37 ++++ .../google/rambi/variants/orco/Makefile.inc | 49 +++++ .../google/rambi/variants/orco/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/orco/gpio.c | 229 ++++++++++++++++++++ .../variants/orco/include/variant/acpi/dptf.asl | 42 ++++ .../orco/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/orco/include/variant/onboard.h | 33 +++ .../rambi/variants/orco/include/variant/variant.h | 37 ++++ .../google/rambi/variants/quawks/Makefile.inc | 49 +++++ .../google/rambi/variants/quawks/devicetree.cb | 98 +++++++++ src/mainboard/google/rambi/variants/quawks/gpio.c | 230 ++++++++++++++++++++ .../variants/quawks/include/variant/acpi/dptf.asl | 41 ++++ .../quawks/include/variant/acpi/mainboard.asl | 16 ++ .../variants/quawks/include/variant/onboard.h | 34 +++ .../variants/quawks/include/variant/variant.h | 37 ++++ .../rambi/include/variant/acpi/mainboard.asl | 8 +- .../google/rambi/variants/squawks/Makefile.inc | 49 +++++ .../google/rambi/variants/squawks/devicetree.cb | 98 +++++++++ src/mainboard/google/rambi/variants/squawks/gpio.c | 230 ++++++++++++++++++++ .../variants/squawks/include/variant/acpi/dptf.asl | 41 ++++ .../squawks/include/variant/acpi/mainboard.asl | 16 ++ .../variants/squawks/include/variant/onboard.h | 34 +++ .../variants/squawks/include/variant/variant.h | 37 ++++ .../google/rambi/variants/sumo/Makefile.inc | 49 +++++ .../google/rambi/variants/sumo/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/sumo/gpio.c | 228 ++++++++++++++++++++ .../variants/sumo/include/variant/acpi/dptf.asl | 42 ++++ .../sumo/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/sumo/include/variant/onboard.h | 47 +++++ .../rambi/variants/sumo/include/variant/variant.h | 37 ++++ src/mainboard/google/rambi/variants/sumo/lan.c | 191 +++++++++++++++++ .../google/rambi/variants/swanky/Makefile.inc | 41 ++++ .../google/rambi/variants/swanky/devicetree.cb | 101 +++++++++ src/mainboard/google/rambi/variants/swanky/gpio.c | 229 ++++++++++++++++++++ .../variants/swanky/include/variant/acpi/dptf.asl | 41 ++++ .../swanky/include/variant/acpi/mainboard.asl | 16 ++ .../variants/swanky/include/variant/onboard.h | 33 +++ .../variants/swanky/include/variant/variant.h | 33 +++ .../google/rambi/variants/winky/Makefile.inc | 45 ++++ .../google/rambi/variants/winky/devicetree.cb | 102 +++++++++ src/mainboard/google/rambi/variants/winky/gpio.c | 228 ++++++++++++++++++++ .../variants/winky/include/variant/acpi/dptf.asl | 42 ++++ .../winky/include/variant/acpi/mainboard.asl | 16 ++ .../rambi/variants/winky/include/variant/onboard.h | 34 +++ .../rambi/variants/winky/include/variant/variant.h | 35 ++++ 116 files changed, 7372 insertions(+), 120 deletions(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index a2bdc43..128e609 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -26,28 +26,80 @@ config MAINBOARD_DIR config VARIANT_DIR string + default "banjo" if BOARD_GOOGLE_BANJO + default "candy" if BOARD_GOOGLE_CANDY + default "clapper" if BOARD_GOOGLE_CLAPPER default "enguarde" if BOARD_GOOGLE_ENGUARDE + default "glimmer" if BOARD_GOOGLE_GLIMMER + default "gnawty" if BOARD_GOOGLE_GNAWTY + default "heli" if BOARD_GOOGLE_HELI + default "kip" if BOARD_GOOGLE_KIP default "ninja" if BOARD_GOOGLE_NINJA + default "orco" if BOARD_GOOGLE_ORCO + default "quawks" if BOARD_GOOGLE_QUAWKS default "rambi" if BOARD_GOOGLE_RAMBI + default "squawks" if BOARD_GOOGLE_SQUAWKS + default "sumo" if BOARD_GOOGLE_SUMO + default "swanky" if BOARD_GOOGLE_SWANKY + default "winky" if BOARD_GOOGLE_WINKY config MAINBOARD_PART_NUMBER string + default "Banjo" if BOARD_GOOGLE_BANJO + default "Candy" if BOARD_GOOGLE_CANDY + default "Clapper" if BOARD_GOOGLE_CLAPPER default "Enguarde" if BOARD_GOOGLE_ENGUARDE + default "Glimmer" if BOARD_GOOGLE_GLIMMER + default "Gnawty" if BOARD_GOOGLE_GNAWTY + default "Heli" if BOARD_GOOGLE_HELI + default "Kip" if BOARD_GOOGLE_KIP default "Ninja" if BOARD_GOOGLE_NINJA + default "Orco" if BOARD_GOOGLE_ORCO + default "Quawks" if BOARD_GOOGLE_QUAWKS default "Rambi" if BOARD_GOOGLE_RAMBI + default "Squawks" if BOARD_GOOGLE_SQUAWKS + default "Sumo" if BOARD_GOOGLE_SUMO + default "Swanky" if BOARD_GOOGLE_SWANKY + default "Winky" if BOARD_GOOGLE_WINKY config GBB_HWID string depends on CHROMEOS + default "BANJO TEST A-A 8843" if BOARD_GOOGLE_BANJO + default "CANDY TEST A-A 3347" if BOARD_GOOGLE_CANDY + default "CLAPPER TEST A-A 7705" if BOARD_GOOGLE_CLAPPER default "ENGUARDE TEST A-A 0128" if BOARD_GOOGLE_ENGUARDE + default "GLIMMER TEST 8028" if BOARD_GOOGLE_GLIMMER + default "GNAWTY TEST A-A 3347" if BOARD_GOOGLE_GNAWTY + default "HELI TEST A-A 7705" if BOARD_GOOGLE_HELI + default "KIP TEST A-A 0128" if BOARD_GOOGLE_KIP default "NINJA TEST A-A 0653" if BOARD_GOOGLE_NINJA + default "ORCO TEST 8028" if BOARD_GOOGLE_ORCO + default "QUAWKS TEST A-A 3347" if BOARD_GOOGLE_QUAWKS default "RAMBI TEST A-A 0128" if BOARD_GOOGLE_RAMBI + default "SQUAWKS TEST A-A 7705" if BOARD_GOOGLE_SQUAWKS + default "SUMO TEST A-A 8843" if BOARD_GOOGLE_SUMO + default "SWANKY TEST A-A 0653" if BOARD_GOOGLE_SWANKY + default "WINKY TEST 0128" if BOARD_GOOGLE_WINKY config DEVICETREE string + default "variants/banjo/devicetree.cb" if BOARD_GOOGLE_BANJO + default "variants/candy/devicetree.cb" if BOARD_GOOGLE_CANDY + default "variants/clapper/devicetree.cb" if BOARD_GOOGLE_CLAPPER default "variants/enguarde/devicetree.cb" if BOARD_GOOGLE_ENGUARDE + default "variants/glimmer/devicetree.cb" if BOARD_GOOGLE_GLIMMER + default "variants/gnawty/devicetree.cb" if BOARD_GOOGLE_GNAWTY + default "variants/heli/devicetree.cb" if BOARD_GOOGLE_HELI + default "variants/kip/devicetree.cb" if BOARD_GOOGLE_KIP default "variants/ninja/devicetree.cb" if BOARD_GOOGLE_NINJA + default "variants/orco/devicetree.cb" if BOARD_GOOGLE_ORCO + default "variants/quawks/devicetree.cb" if BOARD_GOOGLE_QUAWKS default "variants/rambi/devicetree.cb" if BOARD_GOOGLE_RAMBI + default "variants/squawks/devicetree.cb" if BOARD_GOOGLE_SQUAWKS + default "variants/sumo/devicetree.cb" if BOARD_GOOGLE_SUMO + default "variants/swanky/devicetree.cb" if BOARD_GOOGLE_SWANKY + default "variants/winky/devicetree.cb" if BOARD_GOOGLE_WINKY config EC_GOOGLE_CHROMEEC_BOARDNAME string diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name index 0305bc4..12cc3ff 100644 --- a/src/mainboard/google/rambi/Kconfig.name +++ b/src/mainboard/google/rambi/Kconfig.name @@ -1,11 +1,63 @@ +config BOARD_GOOGLE_BANJO + bool "Banjo" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_CANDY + bool "Candy" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_CLAPPER + bool "Clapper" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_ENGUARDE bool "Enguarde" select BOARD_GOOGLE_BASEBOARD_RAMBI +config BOARD_GOOGLE_GLIMMER + bool "Glimmer" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_GNAWTY + bool "Gnawty" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_HELI + bool "Heli" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_KIP + bool "Kip" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_NINJA bool "Ninja" select BOARD_GOOGLE_BASEBOARD_RAMBI +config BOARD_GOOGLE_ORCO + bool "Orco" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_QUAWKS + bool "Quawks" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_SQUAWKS + bool "Squawks" + select BOARD_GOOGLE_BASEBOARD_RAMBI + config BOARD_GOOGLE_RAMBI bool "Rambi" select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_SUMO + bool "Sumo" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_SWANKY + bool "Swanky" + select BOARD_GOOGLE_BASEBOARD_RAMBI + +config BOARD_GOOGLE_WINKY + bool "Winky" + select BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index b08002d..7c0fb35 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -24,6 +24,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c +ramstage-$(CONFIG_BOARD_GOOGLE_SUMO) += variants/$(VARIANT_DIR)/lan.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl b/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl deleted file mode 100644 index 1aec3ce..0000000 --- a/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <variant/onboard.h> - -Scope (\_SB.I2C6) -{ - Device (ATSA) - { - Name (_HID, "ATML0001") - Name (_CID, EisaId ("PNP0C0E")) - Name (_DDN, "Atmel Touchscreen") - Name (_UID, 5) - Name (ISTP, 0) /* TouchScreen */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C6", // ResourceSource - ) - Interrupt (ResourceConsumer, Level, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - } -} diff --git a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl new file mode 100644 index 0000000..1aec3ce --- /dev/null +++ b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C6) +{ + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_CID, EisaId ("PNP0C0E")) + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + } +} diff --git a/src/mainboard/google/rambi/acpi/touchscreen_elan.asl b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl new file mode 100644 index 0000000..ac0763d --- /dev/null +++ b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C6) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "ELAN Touchscreen") + Name (_UID, 1) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl new file mode 100644 index 0000000..0b5c100 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C6) +{ + Device (WTSA) + { + Name (_HID, "WDHT0001") + Name (_DDN, "WDT Touchscreen") + Name (_UID, 6) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/acpi/trackpad_amtel.asl b/src/mainboard/google/rambi/acpi/trackpad_amtel.asl deleted file mode 100644 index 1d9fb46..0000000 --- a/src/mainboard/google/rambi/acpi/trackpad_amtel.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <variant/onboard.h> - -Scope (\_SB.I2C1) -{ - Device (ATPA) - { - Name (_HID, "ATML0000") - Name (_DDN, "Atmel Touchpad") - Name (_UID, 2) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.I2C1", // ResourceSource - ) - Interrupt (ResourceConsumer, Level, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} diff --git a/src/mainboard/google/rambi/acpi/trackpad_atmel.asl b/src/mainboard/google/rambi/acpi/trackpad_atmel.asl new file mode 100644 index 0000000..1d9fb46 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/trackpad_atmel.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/onboard.h> + +Scope (\_SB.I2C1) +{ + Device (ATPA) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") + Name (_UID, 2) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index eaf3079..acd4ffe 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -129,7 +129,7 @@ static int int15_handler(void) static void mainboard_init(device_t dev) { mainboard_ec_init(); -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO) lan_init(); #endif } diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 152d5e6..d8ba001 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -32,11 +32,15 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) ssus_disable_internal_pull(GPIO_SSUS_37_PAD); ssus_disable_internal_pull(GPIO_SSUS_38_PAD); ssus_disable_internal_pull(GPIO_SSUS_39_PAD); - +#ifdef GPIO_SSUS_40_PAD + ssus_disable_internal_pull(GPIO_SSUS_40_PAD); +#endif ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); - +#ifdef GPIO_SSUS_40_PAD + ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3); +#endif printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); if (ram_id >= total_spds) diff --git a/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex b/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex new file mode 100644 index 0000000..19fa083 --- /dev/null +++ b/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 40 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 07 92 01 +00 00 00 00 00 00 CC FB +48 54 54 43 34 47 36 33 +43 46 52 2D 50 42 41 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100644 index 0000000..8ced790 --- /dev/null +++ b/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6CFR6A-PBA +92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..ae17756 --- /dev/null +++ b/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4B 34 42 34 47 31 36 34 +36 51 2D 48 59 4B 30 20 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex b/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex new file mode 100644 index 0000000..fc27f6b --- /dev/null +++ b/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex b/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex new file mode 100644 index 0000000..6e3eab3 --- /dev/null +++ b/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex @@ -0,0 +1,16 @@ +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/rambi/spd/empty.spd.hex b/src/mainboard/google/rambi/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/rambi/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex new file mode 100644 index 0000000..0e8c1bd --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex @@ -0,0 +1,16 @@ +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 22 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 96 77 +48 4D 54 34 32 35 53 36 4D 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex new file mode 100644 index 0000000..b8815c8 --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex @@ -0,0 +1,32 @@ +92 13 0b 03 04 19 02 02 +03 11 01 08 09 00 fe 02 +69 78 69 30 69 11 10 79 +20 08 3c 3c 01 18 83 05 +00 00 ca 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 ec b8 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 39 50 +31 20 50 32 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex new file mode 100644 index 0000000..91133b4 --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex @@ -0,0 +1,32 @@ +92 13 0b 03 04 19 02 02 +03 11 01 08 09 00 fe 02 +69 78 69 30 69 11 10 79 +20 08 3c 3c 01 18 83 05 +00 00 ca 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 45 1d +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 39 50 +31 20 50 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex new file mode 100644 index 0000000..841291b --- /dev/null +++ b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646E-BYK0 +92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F +4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc new file mode 100644 index 0000000..e925263 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b101 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb new file mode 100644 index 0000000..e380920 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Banjo board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x0" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c new file mode 100644 index 0000000..bfb2c9a --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_NC, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_NC, /* S0-SC033 - SD3_CLK */ + GPIO_NC, /* S0-SC034 - SD3_D0 */ + GPIO_NC, /* S0-SC035 - SD3_D1 */ + GPIO_NC, /* S0-SC036 - SD3_D2 */ + GPIO_NC, /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_NC, /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_NC, /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - I2C_4_SDA */ + GPIO_NC, /* S0-SC087 - I2C_4_SCL */ + GPIO_NC, /* S0-SC088 - I2C_5_SDA */ + GPIO_NC, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..4276b1c --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 46 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 44 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..5a46bdc --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h new file mode 100644 index 0000000..38410e1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h new file mode 100644 index 0000000..afb1dff --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b101 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +*/ + +static const uint32_t dual_channel_config = + (1 << 1) | (1 << 3) | (1 << 5) ; + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc new file mode 100644 index 0000000..0a53d84 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b0010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b0011 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b0100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz +# 0b0111 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz +# 0b1000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz +# 0b1001 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz +# 0b1010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b1011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb new file mode 100644 index 0000000..5cbb974 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Candy board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c new file mode 100644 index 0000000..3cbfbaf --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - NC */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_INPUT_PD_20K, /* S540 - RAM_ID3 */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..8dd0885 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 85 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 53 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 70 +#define DPTF_TSR2_CRITICAL 80 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..33d3209 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Elan touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_elan.asl> diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h new file mode 100644 index 0000000..9a69821 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h new file mode 100644 index 0000000..0c58cee --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[3:0] are on GPIO_SSUS[40:37] + * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0111 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz + * 0b1000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b1001 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz + * 0b1010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b1011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 +#define GPIO_SSUS_40_PAD 52 + +#endif diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc new file mode 100644 index 0000000..1a01c8a --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb new file mode 100644 index 0000000..a95ddd1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -0,0 +1,89 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Clapper board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "5" # 400ms + register "gpu_pipea_power_on_delay" = "2000" # 200ms + register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c new file mode 100644 index 0000000..385b406 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_FUNC2, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ + GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ + GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_FUNC0, /* S537 - RAM_ID0 */ + GPIO_FUNC0, /* S538 - RAM_ID1 */ + GPIO_FUNC0, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..53dd09c --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 40 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 35 +#define DPTF_TSR2_CRITICAL 70 + +#undef DPTF_ENABLE_CHARGER diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..82510bd --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Atmel touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl> diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h new file mode 100644 index 0000000..016f657 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h new file mode 100644 index 0000000..38b156c --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl index 772b4ba..3cdd5c0 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl @@ -12,7 +12,5 @@ * GNU General Public License for more details. */ -#include <variant/onboard.h> - /* Elan trackpad */ #include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h index 1477794..2a1045d 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h @@ -31,6 +31,4 @@ #define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) #define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) -#define BOARD_ALS_I2C_ADDR 0x44 - #endif diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc new file mode 100644 index 0000000..341f6d3 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz +# 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb new file mode 100644 index 0000000..bf01cd9 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb @@ -0,0 +1,98 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Glimmer board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c new file mode 100644 index 0000000..8cfe90e --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT (NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + /* TODO(shawnn): Change to normal input once our old boards + * are no longer in use. */ + GPIO_FUNC(0, PULL_DOWN, 20K), /* S540 - RAM_ID3 */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..6e2630b --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Power_Bottom" +#define DPTF_TSR0_PASSIVE 75 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_RAM_bottom" +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 80 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 75 +#define DPTF_TSR2_CRITICAL 80 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x8ca, "mA", 0 }, /* 2.25A (MAX) */ + Package () { 0, 0, 0, 0, 32, 0x7d0, "mA", 0 }, /* 2.0A */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..82510bd --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> + +/* Atmel touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl> diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h new file mode 100644 index 0000000..121da36 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h new file mode 100644 index 0000000..0ea42c5 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz + * 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | + (1 << 4) | (1 << 6) | (1 << 7); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 +#define GPIO_SSUS_40_PAD 52 + +#endif diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc new file mode 100644 index 0000000..05fbc69 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b111 - 4GiB total - 2 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb new file mode 100644 index 0000000..bb6fcad --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Gnawty board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c new file mode 100644 index 0000000..e79dc5a --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..1df96fa --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 70 +#define DPTF_TSR1_CRITICAL 85 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 44 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h new file mode 100644 index 0000000..86ca488 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h new file mode 100644 index 0000000..f81a0dd --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b111 - 4GiB total - 2 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz +*/ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) ; + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc new file mode 100644 index 0000000..d76a127 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# RAM_ID Vendor Vendor_PN Freq Size Total_size channel +# 0b0011 Hynix H5TC4G63AFR-PBA 1600MHZ 4Gb 2GB single-channel +# 0b0100 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 2GB single-channel +# 0b0101 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 2GB single-channel +# 0b0110 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 4GB dual-channel +# 0b0111 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 4GB dual-channel +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += empty # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA # 0b0011 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA # 0b0100 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b0101 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA # 0b0110 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b0111 +SPD_SOURCES += empty # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += empty # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb new file mode 100644 index 0000000..d9b27e6 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Heli board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c new file mode 100644 index 0000000..2a61c55 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_NC, /* S0-SC058 - SIM_DET_C (NC)*/ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L (NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_NC, /* S0-SC072 - TOUCH_INT_L_DX (NC) */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# (NC) */ + GPIO_NC, /* S503 - LTE_WAKE_L# (NC) */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_NC, /* S535 - LTE_DISABLE_L (NC) */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_INPUT, /* S540 - RAM_ID3 */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..adc796d --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 52 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h new file mode 100644 index 0000000..f4ffed5 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h new file mode 100644 index 0000000..d25b9c9 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[3:0] are on GPIO_SSUS[40:37] + * RAM_ID Vendor Vendor_PN Freq Size Total_size channel + * 0b0011 Hynix H5TC4G63AFR-PBA 1600MHZ 4Gb 2GB single-channel + * 0b0100 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 2GB single-channel + * 0b0101 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 2GB single-channel + * 0b0110 Hynix H5TC4G63CFR-PBA 1600MHZ 4Gb 4GB dual-channel + * 0b0111 Samsung K4B4G1646Q-HYK0 1600MHZ 4Gb 4GB dual-channel + */ + +static const uint32_t dual_channel_config = + (1 << 6) | (1 << 7); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 +#define GPIO_SSUS_40_PAD 52 + +#endif diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc new file mode 100644 index 0000000..06bd0e7 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125a +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125a +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb new file mode 100644 index 0000000..f4e0a91 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Kip board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..e88ac7d --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 58 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 58 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 57 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h new file mode 100644 index 0000000..4bb37be --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h new file mode 100644 index 0000000..7f058d7 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc new file mode 100644 index 0000000..1f9706e --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb new file mode 100644 index 0000000..8291794 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Orco board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c new file mode 100644 index 0000000..f2bbe8a --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT (NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - I2C_4_SDA */ + GPIO_NC, /* S0-SC087 - I2C_4_SCL */ + GPIO_NC, /* S0-SC088 - I2C_5_SDA */ + GPIO_NC, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# - INT */ + GPIO_NC, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..3530d7b --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h new file mode 100644 index 0000000..b4a6c6e --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h new file mode 100644 index 0000000..ab81162 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc new file mode 100644 index 0000000..48956a1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb new file mode 100644 index 0000000..cc5146d --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb @@ -0,0 +1,98 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Quawks board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..7e36946 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 52 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 51 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 51 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6A4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */ + Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */ + Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */ + Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */ +}) diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h new file mode 100644 index 0000000..4bb37be --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h new file mode 100644 index 0000000..2b80bf4 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl index acacc5f..f4bc325 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl @@ -17,8 +17,8 @@ /* Elan trackpad */ #include <mainboard/google/rambi/acpi/trackpad_elan.asl> -/* Amtel trackpad */ -#include <mainboard/google/rambi/acpi/trackpad_amtel.asl> +/* Atmel trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_atmel.asl> -/* Amtel touchscreen trackpad */ -#include <mainboard/google/rambi/acpi/touchscreen_amtel.asl> +/* Atmel touchscreen trackpad */ +#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl> diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc new file mode 100644 index 0000000..48956a1 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb new file mode 100644 index 0000000..400a551 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -0,0 +1,98 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Squawks board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c new file mode 100644 index 0000000..3d79d37 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..b17f980 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 53 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 80 +#define DPTF_TSR1_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 53 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x7d0, "mA", 0 }, /* 2.0A */ + Package () { 0, 0, 0, 0, 24, 0x6a4, "mA", 0 }, /* 1.7A */ + Package () { 0, 0, 0, 0, 16, 0x578, "mA", 0 }, /* 1.4A */ + Package () { 0, 0, 0, 0, 8, 0x3e8, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 0, 0x258, "mA", 0 }, /* 0.6A */ +}) diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h new file mode 100644 index 0000000..4bb37be --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h new file mode 100644 index 0000000..2b80bf4 --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc new file mode 100644 index 0000000..b2552d3 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb new file mode 100644 index 0000000..89e2f2b --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Sumo board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c new file mode 100644 index 0000000..0856c29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_FUNC2, /* S0_NC07 - DDI1_DDCDATA */ + GPIO_FUNC2, /* S0_NC08 - DDI1_DDCCLK */ + GPIO_NC, /* S0_NC09 - NC */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_NC, /* S0_SC001 - NC */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE0# */ + GPIO_NC, /* S0-SC004 - NC# */ + GPIO_FUNC1, /* S0-SC005 - PCIE_CLKREQ_WLAN# */ + GPIO_FUNC1, /* S0-SC006 - PCIE_CLKREQ_LAN# */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_FUNC1, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_FUNC1, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_NC, /* S0-SC055 - NC */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - NC */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_NC, /* S0-SC076 - NC */ + GPIO_NC, /* S0-SC077 - NC */ + GPIO_NC, /* S0-SC078 - NC */ + GPIO_NC, /* S0-SC079 - NC */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - NC */ + GPIO_NC, /* S0-SC087 - NC */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_NC, /* S501 - NC */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_INPUT, /* S508 - SOC_RECOVER- */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..3530d7b --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..e7f06ee --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* WDT touchscreen */ +#include <mainboard/google/rambi/acpi/touchscreen_wdt.asl> diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h new file mode 100644 index 0000000..1fb268a --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +#ifndef __ACPI__ +void lan_init(void); +#endif + +/* defines for programming the MAC address */ +#define SUMO_NIC_VENDOR_ID 0x10EC +#define SUMO_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define SUMO_NIC_LED_MODE 0x00 + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 5 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x2c + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +/* Disable PS2 keyboard */ +#undef SIO_EC_ENABLE_PS2K + +#endif diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h new file mode 100644 index 0000000..8d2113c --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c new file mode 100644 index 0000000..07fe3d9 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <variant/onboard.h> + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(SUMO_NIC_VENDOR_ID, + SUMO_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((SUMO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc new file mode 100644 index 0000000..1458ebb --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz +# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb new file mode 100644 index 0000000..5e78a10 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Swanky board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c new file mode 100644 index 0000000..a713549 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_INPUT, /* S541 - PANEL_ID */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..e9b78a8 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..3cdd5c0 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_elan.asl> diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h new file mode 100644 index 0000000..f4ffed5 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h new file mode 100644 index 0000000..483983b --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + */ + +static const uint32_t dual_channel_config = + (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc new file mode 100644 index 0000000..962f30c --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb +# 0b001 - 4GiB total - 2 x Samsung_2Gib_K4B4G1646Q-HYK0 +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb +# 0b101 - 2GiB total - 1 x Samsung_2Gib_K4B4G1646Q-HYK0 +SPD_SOURCES = HT_micron_HTTC4G63CFR-PBA_x16_4Gb +SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0 +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += HT_micron_HTTC4G63CFR-PBA_x16_4Gb +SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb new file mode 100644 index 0000000..6d52b89 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Winky board + register "usb2_comp_bg" = "0x4680" + register "usb2_per_port_lane0" = "0x0004C209" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x0004B209" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c new file mode 100644 index 0000000..2242f98 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <soc/gpio.h> +#include <mainboard/google/rambi/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_NC, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_NC, /* S0-SC072 - TOUCH_INT_L_DX */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_NC, /* S0-SC086 - NC */ + GPIO_NC, /* S0-SC087 - NC */ + GPIO_NC, /* S0-SC088 - NC */ + GPIO_NC, /* S0-SC089 - NC */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_NC, /* S502 - TOUCH_INT# - INT */ + GPIO_NC, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..3530d7b --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..184ef83 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Atmel trackpad */ +#include <mainboard/google/rambi/acpi/trackpad_atmel.asl> diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h new file mode 100644 index 0000000..9771179 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/rambi/irqroute.h> + +/* PCH wake signal from EC. */ +#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0) + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x4b + +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +#endif diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h new file mode 100644 index 0000000..6bf5569 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 + */ + +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +#endif

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coreboot-gerrit January 2017