coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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1340 discussions

New patch to review for coreboot: southbridge/via/vt8237r: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16489 -gerrit commit f8af45600860578f559bb116d28e6181b131274a Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/via/vt8237r: transition away from device_t Replace the use of the old device_t definition inside southbridge/via/vt8237r. Change-Id: I9c1211e698ef35f56dd71c2c021dea680091c1ee Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/via/vt8237r/early_smbus.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index e53b71e..23f5928 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -144,9 +144,9 @@ void smbus_write_byte(u8 dimm, u8 offset, u8 data) #define PSONREADY_TIMEOUT 0x7fffffff -static device_t get_vt8237_lpc(void) +static pci_devfn_t get_vt8237_lpc(void) { - device_t dev; + pci_devfn_t dev; /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -169,7 +169,7 @@ static device_t get_vt8237_lpc(void) */ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; int loops; /* Power management controller */ @@ -258,7 +258,7 @@ void smbus_fixup(const struct mem_controller *ctrl) void vt8237_sb_enable_fid_vid(void) { - device_t dev, devctl; + pci_devfn_t dev, devctl; u16 devid; /* Power management controller */ @@ -315,7 +315,7 @@ void vt8237_sb_enable_fid_vid(void) void enable_rom_decode(void) { - device_t dev; + pci_devfn_t dev; /* Power management controller */ dev = get_vt8237_lpc(); @@ -328,7 +328,7 @@ void enable_rom_decode(void) int acpi_get_sleep_type(void) { - device_t dev; + pci_devfn_t dev; u16 tmp; printk(BIOS_DEBUG, "IN TEST WAKEUP\n"); @@ -353,7 +353,7 @@ int acpi_get_sleep_type(void) #if defined(__GNUC__) void vt8237_early_spi_init(void) { - device_t dev; + pci_devfn_t dev; volatile u16 *spireg; u32 tmp; @@ -410,7 +410,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) { struct vt8237_network_rom n; int i, loops; - device_t dev; + pci_devfn_t dev; u32 tmp; u8 status; u16 *rom_write;

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New patch to review for coreboot: southbridge/sis/sis966: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16488 -gerrit commit fe63ff0d7f1644a8c2a60e9c2cf3107cb4c83937 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/sis/sis966: transition away from device_t Replace the use of the old device_t definition inside southbridge/sis/sis966. Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/sis/sis966/early_smbus.c | 16 +++++++++------- src/southbridge/sis/sis966/sis966.h | 2 ++ 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index fc311ae..74ae1fa 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -19,7 +19,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 4a2b867..5ccceda 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -510,10 +510,12 @@ static const uint8_t SiS_SiS1183_init[44][3]={ */ static void Init_Share_Memory(uint8_t ShareSize) { - device_t dev; + pci_devfn_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5)); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, + PCI_DEVICE_ID_SIS_SIS761), 0); + pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | + (ShareSize << 5)); } /* In: => Aperture size @@ -526,7 +528,7 @@ static void Init_Share_Memory(uint8_t ShareSize) */ static void Init_Aper_Size(uint8_t AperSize) { - device_t dev; + pci_devfn_t dev; uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); @@ -538,7 +540,7 @@ static void Init_Aper_Size(uint8_t AperSize) static void sis_init_stage1(void) { - device_t dev; + pci_devfn_t dev; uint8_t temp8; int i; uint8_t GUI_En; @@ -600,7 +602,7 @@ static void sis_init_stage1(void) static void sis_init_stage2(void) { - device_t dev; + pci_devfn_t dev; msr_t msr; int i; uint8_t temp8; @@ -711,7 +713,7 @@ static void sis_init_stage2(void) static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; uint8_t temp8; printk(BIOS_DEBUG, "enable_smbus -------->\n"); diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index 31af002..61bf0ee 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -31,6 +31,8 @@ #define DEBUG_USB 0 #define DEBUG_USB2 0 +#ifndef __SIMPLE_DEVICE__ void sis966_enable(device_t dev); +#endif #endif /* SIS966_H */

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New patch to review for coreboot: southbridge/nvidia/mcp55: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16487 -gerrit commit db705a83d85c0a64987aab58c6443011340396cc Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/nvidia/mcp55: transition away from device_t Replace the use of the old device_t definition inside southbridge/nvidia/mcp55. Change-Id: I98ac468940eaf6c456fa95540ec3e718edfe26a7 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/early_setup_car.c | 4 ++-- src/southbridge/nvidia/mcp55/early_smbus.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 5e5c535..5e75adf 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -20,7 +20,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 619ba4c..76947ec 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -112,7 +112,7 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, { u32 tgio_ctrl, pll_ctrl, dword; int i; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(busnx, devnx + 1, 1); @@ -378,7 +378,7 @@ static int mcp55_early_setup_x(void) busnx = ht_c_index * HT_CHAIN_BUSN_D; for (devnx = 0; devnx < 0x20; devnx++) { u32 id; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(busnx, devnx, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); if (id == 0x036910de) { diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c index 349461a..595914a 100644 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ b/src/southbridge/nvidia/mcp55/early_smbus.c @@ -25,7 +25,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); if (dev == PCI_DEV_INVALID)

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New patch to review for coreboot: southbridge/nvidia/ck804: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16486 -gerrit commit 3868af1094076566b064abe2d93b29e3bfec4177 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/nvidia/ck804: transition away from device_t Replace the use of the old device_t definition inside southbridge/nvidia/ck801. Change-Id: I43d4d2175f0b6b9e7e2e6fe665ba3d99d792427c Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/nvidia/ck804/early_setup_car.c | 2 +- src/southbridge/nvidia/ck804/early_smbus.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 6b21a3f..689f989 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -334,7 +334,7 @@ static int ck804_early_setup_x(void) for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); else diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index 5f4c6fe..51e200b 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -32,7 +32,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0);

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New patch to review for coreboot: southbridge/intel/i82801dx: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16485 -gerrit commit f3376ed9fb6d6aa8834361404a1f82cf34da8b06 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/intel/i82801dx: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82801dx. Change-Id: Ic08a23f672f8b5e40b837d49a9475d52c728a306 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801dx/early_smbus.c | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 3a7d2b0..5bf87d8 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -22,7 +22,7 @@ void enable_smbus(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 821ed2c..3ab0fda 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -30,7 +30,7 @@ #include <arch/acpi.h> #if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) +#if !defined(__SIMPLE_DEVICE__) #include "chip.h" extern void i82801dx_enable(device_t dev); #else diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index a558169..3a08daa 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -240,7 +240,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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New patch to review for coreboot: southbridge/intel/i82801ax: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16484 -gerrit commit 86b20879ee3d16fad13ca75ae90e0d600078022f Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/intel/i82801ax: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82801ax. Change-Id: I46f0cc92e1034f045988b42df7246f5d0c8d24fc Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801ax/early_smbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index 0de3b62..2a224bf 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -25,7 +25,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3);

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New patch to review for coreboot: southbridge/intel/i82371eb: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16483 -gerrit commit 995ba58ddafe35a09ca7375a1d76ebe7d1033100 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/intel/i82371eb: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82371eb. Change-Id: Ie15a656c817a2ffe0f44ee3a89659d138a1bf212 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82371eb/early_pm.c | 2 +- src/southbridge/intel/i82371eb/early_smbus.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 0605d10..1794393 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -23,7 +23,7 @@ void enable_pm(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u16 reg16; diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 69e967a..af6b14b 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -24,7 +24,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u16 reg16;

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New patch to review for coreboot: southbridge/intel/i3100: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16482 -gerrit commit ddaedb4474145bbef0901dd7f03db573e786ab7e Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/intel/i3100: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i3100. Change-Id: Ic9616d5135cfb7206e086e51aaf82eb66540c4bb Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i3100/early_smbus.c | 2 +- src/southbridge/intel/i3100/i3100.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index 2cb241a..35c32a4 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -20,7 +20,7 @@ static void enable_smbus(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); printk(BIOS_SPEW, "SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); diff --git a/src/southbridge/intel/i3100/i3100.h b/src/southbridge/intel/i3100/i3100.h index 85b30b6..297a2a6 100644 --- a/src/southbridge/intel/i3100/i3100.h +++ b/src/southbridge/intel/i3100/i3100.h @@ -36,6 +36,8 @@ #define SATA_MODE_IDE 0x00 #define SATA_MODE_AHCI 0x01 +#ifndef __SIMPLE_DEVICE__ void i3100_enable(device_t dev); +#endif #endif

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New patch to review for coreboot: southbridge/intel/fsp_rangeley: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16481 -gerrit commit 40aaabd998073da4c2140c7a720f0392bebd1a7d Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/intel/fsp_rangeley: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/fsp_rangeley. Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/fsp_rangeley/early_smbus.c | 2 +- src/southbridge/intel/fsp_rangeley/early_usb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c index ee8c40c..f27fa87 100644 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c index edcd500..dfd8cc2 100644 --- a/src/southbridge/intel/fsp_rangeley/early_usb.c +++ b/src/southbridge/intel/fsp_rangeley/early_usb.c @@ -31,7 +31,7 @@ */ void enable_usb_bar(void) { - device_t usb0 = SOC_EHCI1_DEV; + pci_devfn_t usb0 = SOC_EHCI1_DEV; u32 cmd; /* USB Controller 0 */

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New patch to review for coreboot: southbridge/amd/sb800: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16480 -gerrit commit d04154215a2cd8d5f00239b59ea1328f30006dd0 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/sb800: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/sb800. Change-Id: I488cde4504128331106f50b34869905e30f5ab83 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/sb800/early_setup.c | 14 +++++++------- src/southbridge/amd/sb800/sb800.h | 3 +++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index ac06917..070c1f5 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -73,7 +73,7 @@ static void sb800_acpi_init(void) /* RPR 2.28 Get SB ASIC Revision.*/ static u8 get_sb800_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id; u8 rev = 0; @@ -123,7 +123,7 @@ void sb800_clk_output_48Mhz(void) static void sb800_lpc_init(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; //dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ dev = PCI_DEV(0, 0x14, 0); @@ -166,7 +166,7 @@ static void sb800_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = PCI_DEV(bus, 0x14, 0);//pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -238,7 +238,7 @@ void soft_reset(void) void sb800_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -344,7 +344,7 @@ struct pm_entry const pm_table[] = void sb800_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ byte = pmio_read(0xEC); @@ -361,7 +361,7 @@ void sb800_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb800_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb800_devices_por_init()\n"); @@ -543,7 +543,7 @@ static void sb800_pmio_por_init(void) */ static void sb800_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h index 6a037cf..b36d9bf 100644 --- a/src/southbridge/amd/sb800/sb800.h +++ b/src/southbridge/amd/sb800/sb800.h @@ -42,7 +42,10 @@ void pm_iowrite(u8 reg, u8 value); u8 pm_ioread(u8 reg); void pm2_iowrite(u8 reg, u8 value); u8 pm2_ioread(u8 reg); + +#ifndef __SIMPLE_DEVICE__ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); +#endif #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12

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coreboot-gerrit September 2016