coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16369 -gerrit commit 227bcc22003e2970e5ae90af6f299691cec7ab00 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:18:06 2016 +0200 device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__ Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__ in order to account for the coreboot stages that do not define device_t and are not __PRE_RAM__ (i.e. smm) device_t Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/include/device/pci.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 9ef3614..e167752 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -108,13 +108,13 @@ static inline const struct pci_operations *ops_pci(device_t dev) #endif /* ! __SIMPLE_DEVICE__ */ -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); -#else /* !__PRE_RAM__ */ +#else /* !__SIMPLE_DEVICE__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);

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Patch set updated for coreboot: cpu/amd/model_fxx: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16437 -gerrit commit 2b17190d5146d438c74efe6a960e9fa300fefc3d Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 cpu/amd/model_fxx: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/model_fxx. Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/include/cpu/amd/model_fxx_rev.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 63c8823..d38c552 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -342,7 +342,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 02a50d1..a5436c8 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -77,7 +77,7 @@ static inline int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -95,7 +95,7 @@ static inline int is_e0_later_in_bsp(int nodeid) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 0; dev = PCI_DEV(0, 0x18+nodeid, 3); @@ -106,7 +106,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; dev = PCI_DEV(0, 0x18+nodeid, 3);

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Patch set updated for coreboot: arch/acpi.h: add #if guard to handle the absence of device_t type
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16404 -gerrit commit 1f2522e6b0e6619cf3960bb81adea83b87025dde Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:08:01 2016 +0200 arch/acpi.h: add #if guard to handle the absence of device_t type Avoid the inclusion of a function declaration if the argument type device_t is not defined. This was not a problem until now because the old declaration of device_t and the new one overlapped. Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/arch/x86/include/arch/acpi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 21dae08..a30c5f1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -606,7 +606,7 @@ void acpi_create_slit(acpi_slit_t *slit, void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);

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Patch set updated for coreboot: mainboard/asus/*: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16438 -gerrit commit 7bac0f4a6a13bf49eb8aa6ae289e47feb7af2b03 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:47:40 2016 +0200 mainboard/asus/*: transition away from device_t Replace the use of the old device_t definition inside mainboard/asus/*. Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre/romstage.c | 4 ++-- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 4 ++-- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 ++-- 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 30a1a2a..e6b8ef5 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4d965e7..4a33f77 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 709dbcd..0e502e7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -62,7 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 14d529c..0f98062 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -82,7 +82,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 05ba1f9..0889f24 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -133,7 +133,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index fe83ca8..b547461 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -80,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -131,7 +131,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index f9e5d46..3bf54db 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -76,7 +76,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 544873c..daf0b50 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -101,7 +101,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index bceecf8..9eacecf 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -85,7 +85,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -183,7 +183,7 @@ static void m2v_it8712f_gpio_init(void) static void m2v_bus_init(void) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "m2v_bus_init\n");

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Patch set updated for coreboot: northbridge/intel/i945: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16371 -gerrit commit 597f19ef2ecff1fc88a45b63951fcd59bb6c22c3 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:11:24 2016 +0200 northbridge/intel/i945: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i945/debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 5b6c87a..6228d63 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -23,7 +23,7 @@ void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) {

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Patch set updated for coreboot: lenovo/t60: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16405 -gerrit commit ac5bd26282d3e9875ed195bc48a974f8b6da7354 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:12:20 2016 +0200 lenovo/t60: transition away from device_t Replace the use of the old device_t definition inside mainboard/lenovo/t60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/lenovo/t60/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3ed6afd..d3cd90c 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -95,7 +95,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0);

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Patch set updated for coreboot: mainboard/gigabyte/*: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16439 -gerrit commit b659eb7934f00c6e374c3013a929069142103bb7 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 mainboard/gigabyte/*: transition away from device_t Replace the use of the old device_t definition inside mainboard/gigabyte/*. Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 2 +- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index be6043a..dd889d1 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -33,7 +33,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> -static void it8728f_b75md3h_disable_reboot(device_t dev) +static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev) { /* GPIO SIO settings */ ite_reg_write(dev, 0xEF, 0x7E); // magic diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 55a2a96..fcdac6d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -33,7 +33,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> -static void it8728f_b75md3v_disable_reboot(device_t dev) +static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev) { /* GPIO SIO settings */ ite_reg_write(dev, 0xEF, 0x7E); // magic diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index b6be8fb..2503db9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -41,7 +41,7 @@ static void mb_gpio_init(void) { - device_t dev; + pci_devfn_t dev; /* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0);

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New patch to review for coreboot: mainboard/asus/*: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16438 -gerrit commit b1a37ed737c68e21c40f88e3bc5874bb20416ec2 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:47:40 2016 +0200 mainboard/asus/*: transition away from device_t Replace the use of the old device_t definition inside mainboard/asus/*. Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre/romstage.c | 4 ++-- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 4 ++-- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 ++-- 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 30a1a2a..e6b8ef5 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4d965e7..4a33f77 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 709dbcd..0e502e7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -62,7 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 14d529c..0f98062 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -82,7 +82,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 05ba1f9..0889f24 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -133,7 +133,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index fe83ca8..b547461 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -80,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -131,7 +131,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index f9e5d46..3bf54db 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -76,7 +76,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 544873c..daf0b50 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -101,7 +101,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index bceecf8..9eacecf 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -85,7 +85,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -183,7 +183,7 @@ static void m2v_it8712f_gpio_init(void) static void m2v_bus_init(void) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "m2v_bus_init\n");

1 0

New patch to review for coreboot: cpu/amd/model_fxx: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16437 -gerrit commit 694f16e96ec6f4f935530bed67340baa71e31bdb Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 cpu/amd/model_fxx: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/model_fxx. Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/include/cpu/amd/model_fxx_rev.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 63c8823..d38c552 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -342,7 +342,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 02a50d1..a5436c8 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -77,7 +77,7 @@ static inline int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -95,7 +95,7 @@ static inline int is_e0_later_in_bsp(int nodeid) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 0; dev = PCI_DEV(0, 0x18+nodeid, 3); @@ -106,7 +106,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; dev = PCI_DEV(0, 0x18+nodeid, 3);

1 0

New patch to review for coreboot: cpu/amd/family_10h-family_15h: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16436 -gerrit commit e4fcea9b6e27d51d900b447597121ff40999b29b Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:43:20 2016 +0200 cpu/amd/family_10h-family_15h: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/family_10h-family_15h. Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 39 +++++++++++++++++---------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2e6e153..faf93d0 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -122,7 +122,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i; nodes = get_nodes(); @@ -139,7 +139,8 @@ static void enable_fid_change(u8 fid) } } -static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { +static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) +{ // BKDG 2.4.2.8 // Fam10h revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -164,7 +165,8 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { } } -static void enableNbPState1( device_t dev ) { +static void enableNbPState1(pci_devfn_t dev) +{ uint64_t cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -184,7 +186,8 @@ static void enableNbPState1( device_t dev ) { } } -static u8 setPStateMaxVal(device_t dev) { +static u8 setPStateMaxVal(pci_devfn_t dev) +{ u8 i, maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -204,7 +207,8 @@ static u8 setPStateMaxVal(device_t dev) { return maxpstate; } -static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly(pci_devfn_t dev) +{ // BKDG 2.4.2.7 uint64_t cpuRev = mctGetLogicalCPUID(0xFF); @@ -248,7 +252,8 @@ static int vidTo100uV(u8 vid) return voltage; } -static void setVSRamp(device_t dev) { +static void setVSRamp(pci_devfn_t dev) +{ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -263,7 +268,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); } -static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -447,7 +452,8 @@ static u32 power_up_down(int node, u8 procPkg) { } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { - device_t dev = NODE_PCI(node, 3); + + pci_devfn_t dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -471,7 +477,9 @@ static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t pr } -static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) { +static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, + uint8_t procPkg) +{ /* check PVI/SVI */ uint32_t dword = pci_read_config32(dev, 0xa0); @@ -504,7 +512,8 @@ static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t pr pci_write_config32(dev, 0xa0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { +static void config_nb_syn_ptr_adj(pci_devfn_t dev, uint64_t cpuRev) +{ /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -526,7 +535,9 @@ static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) { +static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, + uint8_t procPkg) +{ if (is_fam15h()) { /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ pci_write_config32(dev, 0x80, 0xe20be281); @@ -594,7 +605,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i; /* This needs to be run before any Pstate changes are requested */ @@ -809,7 +820,7 @@ static u32 needs_NB_COF_VID_update(void) static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + pci_devfn_t dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -973,7 +984,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + pci_devfn_t dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 4405e3c..3c13e36 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -541,7 +541,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect;

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coreboot-gerrit September 2016