coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: northbridge/intel/e7505: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16469 -gerrit commit 726c77f4149c0750d832ee2b98016b9a27a1b5aa Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/intel/e7505: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/e7505. Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/e7505/debug.c | 6 +++--- src/northbridge/intel/e7505/raminit.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 33f1ed1..022257c 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -21,7 +21,7 @@ void print_debug_pci_dev(unsigned dev) void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -54,7 +54,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -71,7 +71,7 @@ void dump_pci_devices(void) void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 8eb4990..979ae0a 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -6,7 +6,7 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller // SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away

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New patch to review for coreboot: northbridge/amd/amdht: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16468 -gerrit commit 01d16611a1b617d12fb967702c633de73afee711 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/amd/amdht: transition away from device_t Replace the use of the old device_t definition inside northbridge/amd/amdht. Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/amd/amdht/ht_wrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index f31fcd2..20ffdd4 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -69,7 +69,7 @@ static u32 get_nodes(void) { - device_t dev; + pci_devfn_t dev; u32 nodes; dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0);

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New patch to review for coreboot: northbridge/amd/amdk8: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16467 -gerrit commit f4b15189fcffbbb48f6e0331c3d3f98ddc5a54a2 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/amd/amdk8: transition away from device_t Replace the use of the old device_t definition inside northbridge/amd/amdk8. Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/amd/amdk8/amdk8.h | 2 +- src/northbridge/amd/amdk8/coherent_ht.c | 11 ++++---- src/northbridge/amd/amdk8/debug.c | 9 ++++--- src/northbridge/amd/amdk8/early_ht.c | 4 +-- src/northbridge/amd/amdk8/f.h | 4 +-- src/northbridge/amd/amdk8/f_pci.c | 12 ++++++--- src/northbridge/amd/amdk8/incoherent_ht.c | 37 ++++++++++++++------------ src/northbridge/amd/amdk8/pre_f.h | 4 +-- src/northbridge/amd/amdk8/raminit.c | 8 +++--- src/northbridge/amd/amdk8/raminit.h | 2 +- src/northbridge/amd/amdk8/raminit_f.c | 8 +++--- src/northbridge/amd/amdk8/setup_resource_map.c | 4 +-- 12 files changed, 57 insertions(+), 48 deletions(-) diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..2992abc 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -12,7 +12,7 @@ #endif #ifdef __PRE_RAM__ -void showallroutes(int level, device_t dev); +void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 7dfc5ef..cd4333e 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -265,7 +265,7 @@ static int verify_connection(u8 dest) return 1; } -static uint16_t read_freq_cap(device_t dev, uint8_t pos) +static uint16_t read_freq_cap(pci_devfn_t dev, uint8_t pos) { /* Handle bugs in valid hypertransport frequency reporting */ uint16_t freq_cap; @@ -293,7 +293,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) return freq_cap; } -static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2) +static int optimize_connection(pci_devfn_t node1, uint8_t link1, + pci_devfn_t node2, uint8_t link2) { static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; @@ -1608,7 +1609,7 @@ static void coherent_ht_finalize(unsigned nodes) rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { - device_t dev; + pci_devfn_t dev; uint32_t val; dev = NODE_HT(node); @@ -1652,7 +1653,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) unsigned node; int needs_reset = 0; for (node = 0; node < nodes; node++) { - device_t dev; + pci_devfn_t dev; uint32_t cmd; dev = NODE_MC(node); #if !CONFIG_K8_REV_F_SUPPORT @@ -1722,7 +1723,7 @@ static int optimize_link_read_pointers(unsigned nodes) unsigned node; int needs_reset = 0; for (node = 0; node < nodes; node++) { - device_t f0_dev, f3_dev; + pci_devfn_t f0_dev, f3_dev; uint32_t cmd_ref, cmd; int link; f0_dev = NODE_HT(node); diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 35353bd..18fc858 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -18,7 +18,7 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -58,7 +58,8 @@ static void dump_pci_device(unsigned dev) } #if CONFIG_K8_REV_F_SUPPORT -static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); +static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, + uint32_t index_reg, uint32_t index); static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; @@ -82,7 +83,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -107,7 +108,7 @@ static inline void dump_pci_devices(void) static inline void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 8f6766d..d07da2a 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -13,7 +13,7 @@ static void enumerate_ht_chain(void) * links needs to be programed to point at bus 0. */ unsigned next_unitid, last_unitid; - device_t dev; + pci_devfn_t dev; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; @@ -61,7 +61,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index a449c34..ce039af 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -486,10 +486,10 @@ struct mem_info { // pernode } __attribute__((packed)); struct link_pair_st { - device_t udev; + pci_devfn_t udev; uint32_t upos; uint32_t uoffs; - device_t dev; + pci_devfn_t dev; uint32_t pos; uint32_t offs; diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index d89dadc..3ea4003 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -3,7 +3,8 @@ #ifdef UNUSED_CODE /* bit [10,8] are dev func, bit[1,0] are dev index */ -static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) +static uint32_t pci_read_config32_index(pci_devfn_t dev, uint32_t index_reg, + uint32_t index) { uint32_t dword; @@ -14,7 +15,8 @@ static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32 return dword; } -static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index(pci_devfn_t dev, uint32_t index_reg, + uint32_t index, uint32_t data) { pci_write_config32(dev, index_reg, index); @@ -22,7 +24,8 @@ static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t } #endif -static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index) +static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, + uint32_t index_reg, uint32_t index) { uint32_t dword; @@ -38,7 +41,8 @@ static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, u return dword; } -static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, + uint32_t index, uint32_t data) { uint32_t dword; diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index de2a4b3..bc50b66 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -18,7 +18,7 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval) printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } -static uint8_t ht_lookup_capability(device_t dev, uint16_t val) +static uint8_t ht_lookup_capability(pci_devfn_t dev, uint16_t val) { uint8_t pos; uint8_t hdr_type; @@ -51,13 +51,13 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val) return pos; } -static uint8_t ht_lookup_slave_capability(device_t dev) +static uint8_t ht_lookup_slave_capability(pci_devfn_t dev) { return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format } #if 0 -static uint8_t ht_lookup_host_capability(device_t dev) +static uint8_t ht_lookup_host_capability(pci_devfn_t dev) { return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format } @@ -65,7 +65,7 @@ static uint8_t ht_lookup_host_capability(device_t dev) static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) { - device_t dev; + pci_devfn_t dev; //actually, only for one HT device HT chain, and unitid is 0 #if !CONFIG_HT_CHAIN_UNITID_BASE @@ -111,7 +111,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid } } -static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) +static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) { /* Handle bugs in valid hypertransport frequency reporting */ uint16_t freq_cap; @@ -157,7 +157,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) return freq_cap; } -static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) +static uint8_t ht_read_width_cap(pci_devfn_t dev, uint8_t pos) { uint8_t width_cap = pci_read_config8(dev, pos); @@ -203,8 +203,8 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) PCI_HT_CAP_SLAVE_FREQ_CAP1) static int ht_optimize_link( - device_t dev1, uint8_t pos1, unsigned offs1, - device_t dev2, uint8_t pos2, unsigned offs2) + pci_devfn_t dev1, uint8_t pos1, unsigned offs1, + pci_devfn_t dev2, uint8_t pos2, unsigned offs2) { static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; @@ -290,9 +290,11 @@ static int ht_optimize_link( } #if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) +static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, + unsigned offset_unitid, struct sys_info *sysinfo) #else -static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) +static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, + unsigned offset_unitid) #endif { //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link @@ -348,7 +350,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } } while ((ctrl & (1 << 5)) == 0); - device_t dev = PCI_DEV(bus, 0, 0); + pci_devfn_t dev = PCI_DEV(bus, 0, 0); last_unitid = next_unitid; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -470,9 +472,10 @@ end_of_chain: ; #if 0 #if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo) +static void ht_setup_chain(pci_devfn_t udev, unsigned upos, + struct sys_info *sysinfo) #else -static int ht_setup_chain(device_t udev, unsigned upos) +static int ht_setup_chain(pci_devfn_t udev, unsigned upos) #endif { unsigned offset_unitid = 0; @@ -570,7 +573,7 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, uint32_t dword; uint8_t link_type; unsigned regpos; - device_t dev; + pci_devfn_t dev; /* This works on an Athlon64 because unimplemented links return 0 */ regpos = 0x98 + (linkn * 0x20); @@ -636,7 +639,7 @@ static int ht_setup_chains(uint8_t ht_c_num) * links needs to be programed to point at bus 0. */ uint8_t upos; - device_t udev; + pci_devfn_t udev; uint8_t i; #if !CONFIG_RAMINIT_SYSINFO @@ -742,7 +745,7 @@ static int ht_setup_chains_x(void) } for (nodeid=0; nodeid<nodes; nodeid++) { - device_t dev; + pci_devfn_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); for (linkn = 0; linkn<3; linkn++) { @@ -782,7 +785,7 @@ static int ht_setup_chains_x(void) for (nodeid = 1; nodeid<nodes; nodeid++) { int i; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); for (i = 0; i< 4; i++) { unsigned regpos; diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index c413b5b..9c1eeb6 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -240,10 +240,10 @@ //struct definitions struct link_pair_st { - device_t udev; + pci_devfn_t udev; uint32_t upos; uint32_t uoffs; - device_t dev; + pci_devfn_t dev; uint32_t pos; uint32_t offs; diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index a9516d8..aab9fa7 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -22,7 +22,7 @@ void setup_resource_map(const unsigned int *register_values, int max) int i; // printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = register_values[i] & ~0xfff; @@ -525,7 +525,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; @@ -817,7 +817,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, unsigned base; unsigned index; unsigned limit_reg, base_reg; - device_t device; + pci_devfn_t device; node_id = ctrl->node_id; index = (node_id << 3); @@ -2231,7 +2231,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, { int ii; uint32_t carry_over; - device_t dev; + pci_devfn_t dev; uint32_t base, limit; uint32_t basek; uint32_t hoist; diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 9da8417..610d7d3 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -6,7 +6,7 @@ #define DIMM_SOCKETS 4 struct mem_controller { unsigned node_id; - device_t f0, f1, f2, f3; + pci_devfn_t f0, f1, f2, f3; uint16_t channel0[DIMM_SOCKETS]; uint16_t channel1[DIMM_SOCKETS]; }; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 765fea1..67f3433 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -72,7 +72,7 @@ void setup_resource_map(const unsigned int *register_values, int max) { int i; for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = register_values[i] & ~0xff; @@ -688,7 +688,7 @@ index: printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; @@ -1011,7 +1011,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, unsigned base; unsigned index; unsigned limit_reg, base_reg; - device_t device; + pci_devfn_t device; node_id = ctrl->node_id; index = (node_id << 3); @@ -2903,7 +2903,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, { int ii; uint32_t carry_over; - device_t dev; + pci_devfn_t dev; uint32_t base, limit; uint32_t basek; uint32_t hoist; diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index f8f2bbf..fa03e4a 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -9,7 +9,7 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns printk(BIOS_DEBUG, "setting up resource map offset....\n"); #endif for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg = 0; #if RES_DEBUG @@ -58,7 +58,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg = 0; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev;

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New patch to review for coreboot: northbridge/amd/amdfam10: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16466 -gerrit commit ec7942b5696ce006cd29a36b7736674cc93715f3 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/amd/amdfam10: transition away from device_t Replace the use of the old device_t definition inside northbridge/amd/amdfam10. Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/amd/amdfam10/amdfam10.h | 8 +++++--- src/northbridge/amd/amdfam10/debug.c | 8 ++++---- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdfam10/pci.c | 11 +++++++---- src/northbridge/amd/amdfam10/raminit.h | 4 ++-- src/northbridge/amd/amdfam10/setup_resource_map.c | 8 ++++---- 6 files changed, 23 insertions(+), 18 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index c0bfc5a..4c3aec6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -984,10 +984,10 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #endif struct link_pair_t { - device_t udev; + pci_devfn_t udev; u32 upos; u32 uoffs; - device_t dev; + pci_devfn_t dev; u32 pos; u32 offs; u8 host; @@ -1048,7 +1048,7 @@ device_t get_node_pci(u32 nodeid, u32 fn); #endif #ifdef __PRE_RAM__ -void showallroutes(int level, device_t dev); +void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base); @@ -1072,9 +1072,11 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); struct acpi_rsdp; +#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(device_t device); +#endif #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index f8e5358..e01c44d 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -34,7 +34,7 @@ static void print_debug_pci_dev(u32 dev) static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -59,7 +59,7 @@ static inline void print_pci_devices(void) static inline void print_pci_devices_on_bus(u32 busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -160,7 +160,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -185,7 +185,7 @@ static inline void dump_pci_devices(void) static inline void dump_pci_devices_on_bus(u32 busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 57c992c..a1b411f 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -93,7 +93,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (next_unitid>=0x18) { diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 5892540..03b63b5 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -19,7 +19,7 @@ /* bit [10,8] are dev func, bit[1,0] are dev index */ -static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) +static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) { u32 dword; @@ -29,7 +29,8 @@ static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) } #ifdef UNUSED_CODE -static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, + u32 data) { pci_write_config32(dev, index_reg, index); @@ -39,7 +40,8 @@ static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 } #endif -static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) +static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, + u32 index) { u32 dword; @@ -54,7 +56,8 @@ static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) } #ifdef UNUSED_CODE -static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data) +static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, + u32 index, u32 data) { u32 dword; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 622a98a..7c7065df 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -23,7 +23,7 @@ #define DIMM_SOCKETS 8 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3, f4, f5; + pci_devfn_t f0, f1, f2, f3, f4, f5; /* channelA, channelB belong to DCT0, * channelC, channelD belong to DCT1 * Each DCT may support one ganged logical FBDIMM ---> 128 bit @@ -47,7 +47,7 @@ struct mem_controller { #define DIMM_SOCKETS 4 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3, f4, f5; + pci_devfn_t f0, f1, f2, f3, f4, f5; /* channel0 is DCT0 --- channelA * channel1 is DCT1 --- channelB * can be ganged, a single dual-channel DCT ---> 128 bit diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index a14fc3c..6de7a8c 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -23,7 +23,7 @@ static void setup_resource_map(const u32 *register_values, u32 max) // printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; @@ -43,7 +43,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p u32 i; // printk(BIOS_DEBUG, "setting up resource map offset...."); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; unsigned long reg; dev = (register_values[i] & ~0xfff) + offset_pci_dev; @@ -79,7 +79,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; @@ -147,7 +147,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max) switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = register_values[i+1] & ~0xff;

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New patch to review for coreboot: mainboard/bcom/winnetp680: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16465 -gerrit commit 47f5a03d2d8236b5083ae646ef24aeb8b4953e27 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 mainboard/bcom/winnetp680: transition away from device_t Replace the use of the old device_t definition inside mainboard/bcom/winnetp680. Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/bcom/winnetp680/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index f2144ff..0a3ba72 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -42,7 +42,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID)

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Patch set updated for coreboot: northbridge/intel/sandybridge: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16409 -gerrit commit 7f062f5db9eaddfa0d0a0ab42aadcc3c4b9f303b Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:17:26 2016 +0200 northbridge/intel/sandybridge: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/sandybridge. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/sandybridge/sandybridge.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..972ed9f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -234,7 +234,7 @@ void mainboard_config_superio(void); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp;

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Patch set updated for coreboot: northbridge/amd/lx: remove unused function declaration
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16435 -gerrit commit d4a488b0f0fb9df21d2fcda62b85d8e18c81ed82 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 12:50:16 2016 +0200 northbridge/amd/lx: remove unused function declaration Remove an unusued function declaration that caused problems while compiling the target. Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/amd/lx/northbridge.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index 1e0e650..9a4ff29 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -19,7 +19,6 @@ #include <cpu/amd/lxdef.h> /* northbridge.c */ -unsigned int lx_scan_root_bus(device_t root, unsigned int max); int sizeram(void); /* northbridgeinit.c */

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Patch set updated for coreboot: southbridge/amd/agesa/hudson: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16401 -gerrit commit 52caaa9183acd7ce6f77a88d2427b57c5ba90d70 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Sep 1 16:50:42 2016 +0200 southbridge/amd/agesa/hudson: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/agesa/hudson. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 57119f9..1cdaa05 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -28,7 +28,7 @@ void hudson_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); @@ -73,7 +73,7 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ outb(0xEC, 0xCD6); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 92058c6..d870845 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -70,7 +70,7 @@ u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

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Patch set updated for coreboot: cpu/amd/family_10h-family_15h: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16436 -gerrit commit 3bf8609f273f43f3e73150c4e35260e6db3b3d90 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:43:20 2016 +0200 cpu/amd/family_10h-family_15h: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/family_10h-family_15h. Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 39 +++++++++++++++++---------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2e6e153..faf93d0 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -122,7 +122,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i; nodes = get_nodes(); @@ -139,7 +139,8 @@ static void enable_fid_change(u8 fid) } } -static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { +static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) +{ // BKDG 2.4.2.8 // Fam10h revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -164,7 +165,8 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { } } -static void enableNbPState1( device_t dev ) { +static void enableNbPState1(pci_devfn_t dev) +{ uint64_t cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -184,7 +186,8 @@ static void enableNbPState1( device_t dev ) { } } -static u8 setPStateMaxVal(device_t dev) { +static u8 setPStateMaxVal(pci_devfn_t dev) +{ u8 i, maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -204,7 +207,8 @@ static u8 setPStateMaxVal(device_t dev) { return maxpstate; } -static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly(pci_devfn_t dev) +{ // BKDG 2.4.2.7 uint64_t cpuRev = mctGetLogicalCPUID(0xFF); @@ -248,7 +252,8 @@ static int vidTo100uV(u8 vid) return voltage; } -static void setVSRamp(device_t dev) { +static void setVSRamp(pci_devfn_t dev) +{ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -263,7 +268,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); } -static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -447,7 +452,8 @@ static u32 power_up_down(int node, u8 procPkg) { } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { - device_t dev = NODE_PCI(node, 3); + + pci_devfn_t dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -471,7 +477,9 @@ static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t pr } -static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) { +static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, + uint8_t procPkg) +{ /* check PVI/SVI */ uint32_t dword = pci_read_config32(dev, 0xa0); @@ -504,7 +512,8 @@ static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t pr pci_write_config32(dev, 0xa0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { +static void config_nb_syn_ptr_adj(pci_devfn_t dev, uint64_t cpuRev) +{ /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -526,7 +535,9 @@ static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) { +static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, + uint8_t procPkg) +{ if (is_fam15h()) { /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ pci_write_config32(dev, 0x80, 0xe20be281); @@ -594,7 +605,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i; /* This needs to be run before any Pstate changes are requested */ @@ -809,7 +820,7 @@ static u32 needs_NB_COF_VID_update(void) static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + pci_devfn_t dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -973,7 +984,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + pci_devfn_t dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 4405e3c..3c13e36 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -541,7 +541,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect;

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Patch set updated for coreboot: southbridge/intel/bd82x6x: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16407 -gerrit commit dafeeeede23864134b6b7f54b22e61210c36a381 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:14:39 2016 +0200 southbridge/intel/bd82x6x: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/bd82x6x. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/pch.c | 10 ++++++---- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 2b174c7..9f74fdd 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index b2fbd69..a5c63b6 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -38,7 +38,7 @@ static uint16_t read16p (uintptr_t addr) which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr; dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 974abb1..51fdd2e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -30,11 +30,12 @@ int pch_silicon_revision(void) { static int pch_revision_id = -1; - device_t dev; -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif @@ -46,11 +47,12 @@ int pch_silicon_revision(void) int pch_silicon_type(void) { static int pch_type = -1; - device_t dev; -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index f22fed5..1977c8f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,7 +66,7 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) -#if !defined(__SMM__) +#if !defined(__SIMPLE_DEVICE__) #include "chip.h" void pch_enable(device_t dev); #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 0478285..71ebb6e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -278,7 +278,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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coreboot-gerrit September 2016