coreboot-gerrit September 2016

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New patch to review for coreboot: southbridge/amd/sb700: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16479 -gerrit commit 9752ad5761dca6007df0010b4031050380461cae Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/sb700: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/sb700. Change-Id: I44b0be2070719066dd18bbf2882c417caef5d8b2 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/amd/sb700/sb700.h | 4 ++++ 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 755a161..1aa7be0 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -77,7 +77,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -134,7 +134,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -193,7 +193,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -206,7 +206,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -219,7 +219,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -284,7 +284,7 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -329,7 +329,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -348,7 +348,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; uint32_t dword; uint8_t nvram; @@ -705,7 +705,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; uint8_t acpi_s1_supported = 1; diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index f23956c..191dff1 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -42,7 +42,9 @@ extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); extern void pm2_iowrite(u8 reg, u8 value); extern u8 pm2_ioread(u8 reg); +#ifndef __SIMPLE_DEVICE__ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); +#endif #define REV_SB700_A11 0x11 #define REV_SB700_A12 0x12 @@ -56,7 +58,9 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); * The differentiate is 0x28, isn't it? */ #define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28) +#ifndef __SIMPLE_DEVICE__ void sb7xx_51xx_enable(device_t dev); +#endif #ifdef __PRE_RAM__ void sb7xx_51xx_lpc_port80(void);

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New patch to review for coreboot: southbridge/amd/sb600: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16478 -gerrit commit d841e559a1febb861204ae9c6722a9ecc6001af8 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/sb600: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/sb600. Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb600/sb600.h | 4 +++- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index cbe8b0c..2caa28b 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -36,7 +36,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -63,7 +63,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -102,7 +102,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -192,7 +192,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -237,7 +237,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -256,7 +256,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -516,7 +516,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h index 5c1111a..94ee861 100644 --- a/src/southbridge/amd/sb600/sb600.h +++ b/src/southbridge/amd/sb600/sb600.h @@ -34,9 +34,11 @@ extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); extern void pm2_iowrite(u8 reg, u8 value); extern u8 pm2_ioread(u8 reg); -extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); +#ifndef __SIMPLE_DEVICE__ +extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); void sb600_enable(device_t dev); +#endif void sb600_lpc_port80(void); void sb600_pci_port80(void);

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New patch to review for coreboot: southbridge/amd/rs780: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16477 -gerrit commit 8d815dc37888fa504c9a68a2c43ea0658c52882f Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/rs780: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/rs780. Change-Id: Ia9929baeec7423e9e2f06324038ddfbec006beb7 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/rs780/early_setup.c | 50 ++++++++++++++++----------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index c61493d..b0a40be 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -19,49 +19,49 @@ #define NBMISC_INDEX 0x60 #define NBMC_INDEX 0xE8 -static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); } -static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { pci_write_config32(dev, index_reg, index /* | 0x80 */ ); pci_write_config32(dev, index_reg + 0x4, data); } -static u32 nbmisc_read_index(device_t nb_dev, u32 index) +static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -static u32 htiu_read_index(device_t nb_dev, u32 index) +static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -static void htiu_write_index(device_t nb_dev, u32 index, u32 data) +static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -static u32 nbmc_read_index(device_t nb_dev, u32 index) +static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -static void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -73,7 +73,7 @@ static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } } -static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -85,7 +85,7 @@ static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } } -static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -98,8 +98,8 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } /* family 10 only, for reg > 0xFF */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 -static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, - u32 val) +static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos, + u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = Get_NB32(fam10_dev, reg_pos); @@ -114,7 +114,7 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m #endif -static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, +static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) { u8 reg_old, reg; @@ -126,7 +126,7 @@ static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, } } -static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -155,7 +155,7 @@ static u8 cpu_core_number(void) } #endif -static u8 get_nb_rev(device_t nb_dev) +static u8 get_nb_rev(pci_devfn_t nb_dev) { u8 reg; reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */ @@ -203,7 +203,7 @@ static void rs780_htinit(void) /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t cpu_f0, rs780_f0, clk_f1; + pci_devfn_t cpu_f0, rs780_f0, clk_f1; u32 reg; u8 cpu_ht_freq, ibias; @@ -299,7 +299,7 @@ static void rs780_htinit(void) *******************************************************/ static void k8_optimization(void) { - device_t k8_f0, k8_f2, k8_f3; + pci_devfn_t k8_f0, k8_f2, k8_f3; msr_t msr; printk(BIOS_INFO, "k8_optimization()\n"); @@ -341,7 +341,7 @@ static void k8_optimization(void) #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static void fam10_optimization(void) { - device_t cpu_f0, cpu_f2, cpu_f3; + pci_devfn_t cpu_f0, cpu_f2, cpu_f3; u32 val; printk(BIOS_INFO, "fam10_optimization()\n"); @@ -406,7 +406,7 @@ static void fam10_optimization(void) /***************************************** * rs780_por_pcicfg_init() *****************************************/ -static void rs780_por_pcicfg_init(device_t nb_dev) +static void rs780_por_pcicfg_init(pci_devfn_t nb_dev) { /* enable PCI Memory Access */ set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); @@ -456,7 +456,7 @@ static void rs780_por_pcicfg_init(device_t nb_dev) set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02); } -static void rs780_por_mc_index_init(device_t nb_dev) +static void rs780_por_mc_index_init(pci_devfn_t nb_dev) { set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); @@ -467,7 +467,7 @@ static void rs780_por_mc_index_init(device_t nb_dev) set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E); } -static void rs780_por_misc_index_init(device_t nb_dev) +static void rs780_por_misc_index_init(pci_devfn_t nb_dev) { /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL * Block non-snoop DMA request if PMArbDis is set. @@ -524,7 +524,7 @@ static void rs780_por_misc_index_init(device_t nb_dev) /***************************************** * Some setting is from rpr. Some is from CIMx. *****************************************/ -static void rs780_por_htiu_index_init(device_t nb_dev) +static void rs780_por_htiu_index_init(pci_devfn_t nb_dev) { #if 0 /* get from rpr. */ set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); @@ -583,7 +583,7 @@ static void rs780_por_htiu_index_init(device_t nb_dev) * POR: Power On Reset * RPR: Register Programming Requirements *****************************************/ -static void rs780_por_init(device_t nb_dev) +static void rs780_por_init(pci_devfn_t nb_dev) { printk(BIOS_INFO, "rs780_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ @@ -621,7 +621,7 @@ static void rs780_before_pci_init(void) static void rs780_early_setup(void) { - device_t nb_dev = PCI_DEV(0, 0, 0); + pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs780_early_setup()\n"); /* The printk(BIOS_INFO, s) below cause the system unstable. */

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New patch to review for coreboot: southbridge/amd/rs690: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16476 -gerrit commit 9e3f0a304bf771e18cc7bebc2a36f805e0738b31 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/rs690: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/rs690. Change-Id: Ief43393f62312bfe82e960faf56b1e2ec048f4ff Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/rs690/early_setup.c | 44 ++++++++++++++++----------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/southbridge/amd/rs690/early_setup.c b/src/southbridge/amd/rs690/early_setup.c index ec14073..7746fca 100644 --- a/src/southbridge/amd/rs690/early_setup.c +++ b/src/southbridge/amd/rs690/early_setup.c @@ -19,49 +19,49 @@ #define NBMISC_INDEX 0x60 #define NBMC_INDEX 0xE8 -static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); } -static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { pci_write_config32(dev, index_reg, index /* | 0x80 */ ); pci_write_config32(dev, index_reg + 0x4, data); } -static u32 nbmisc_read_index(device_t nb_dev, u32 index) +static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -static u32 htiu_read_index(device_t nb_dev, u32 index) +static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -static void htiu_write_index(device_t nb_dev, u32 index, u32 data) +static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -static u32 nbmc_read_index(device_t nb_dev, u32 index) +static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -static void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -73,7 +73,7 @@ static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } } -static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -85,7 +85,7 @@ static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } } -static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -97,7 +97,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } } -static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, +static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) { u8 reg_old, reg; @@ -109,7 +109,7 @@ static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, } } -static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -148,7 +148,7 @@ static void get_cpu_rev(void) printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } -static u8 get_nb_rev(device_t nb_dev) +static u8 get_nb_rev(pci_devfn_t nb_dev) { u32 reg; reg = pci_read_config32(nb_dev, 0x00); @@ -172,7 +172,7 @@ static void rs690_htinit(void) /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0, rs690_f0; + pci_devfn_t k8_f0, rs690_f0; u32 reg; u8 reg8; u8 k8_ht_freq; @@ -227,7 +227,7 @@ static void rs690_htinit(void) *******************************************************/ static void k8_optimization(void) { - device_t k8_f0, k8_f2, k8_f3; + pci_devfn_t k8_f0, k8_f2, k8_f3; msr_t msr; printk(BIOS_INFO, "k8_optimization()\n"); @@ -266,7 +266,7 @@ static void k8_optimization(void) /***************************************** * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE *****************************************/ -static void rs690_por_pcicfg_init(device_t nb_dev) +static void rs690_por_pcicfg_init(pci_devfn_t nb_dev) { /* enable PCI Memory Access */ set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); @@ -318,7 +318,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev) /***************************************** * Compliant with CIM_33's ATINB_MCIndex_POR_TABLE *****************************************/ -static void rs690_por_mc_index_init(device_t nb_dev) +static void rs690_por_mc_index_init(pci_devfn_t nb_dev) { set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); @@ -333,7 +333,7 @@ static void rs690_por_mc_index_init(device_t nb_dev) * Compliant with CIM_33's ATINB_MISCIND_POR_TABLE * Compliant with CIM_33's MISC_INIT_TBL *****************************************/ -static void rs690_por_misc_index_init(device_t nb_dev) +static void rs690_por_misc_index_init(pci_devfn_t nb_dev) { /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL * Block non-snoop DMA request if PMArbDis is set. @@ -386,7 +386,7 @@ static void rs690_por_misc_index_init(device_t nb_dev) /***************************************** * Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE *****************************************/ -static void rs690_por_htiu_index_init(device_t nb_dev) +static void rs690_por_htiu_index_init(pci_devfn_t nb_dev) { /* 0xBC: * Enables GSM mode for C1e or C3 with pop-up @@ -419,7 +419,7 @@ static void rs690_por_htiu_index_init(device_t nb_dev) * POR: Power On Reset * RPR: Register Programming Requirements *****************************************/ -static void rs690_por_init(device_t nb_dev) +static void rs690_por_init(pci_devfn_t nb_dev) { printk(BIOS_INFO, "rs690_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */ @@ -458,7 +458,7 @@ static void rs690_before_pci_init(void) */ static void rs690_early_setup(void) { - device_t nb_dev = PCI_DEV(0, 0, 0); + pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs690_early_setup()\n"); /*ATINB_PrepareInit */

1 0

New patch to review for coreboot: southbridge/amd/pi/hudson: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16475 -gerrit commit dd0d379fc156835330f7483307f4e7d4068aaff4 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/pi/hudson: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/pi/hudson. Change-Id: I8b22a8d9f0e90afaf0f218c5c0924a78883b7498 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/pi/hudson/early_setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index f4fcf8b..dce1620 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -60,7 +60,7 @@ void configure_hudson_uart(void) void hudson_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); @@ -105,7 +105,7 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ outb(0xEC, 0xCD6); @@ -123,7 +123,7 @@ void hudson_lpc_port80(void) void hudson_lpc_decode(void) { - device_t dev; + pci_devfn_t dev; u32 tmp = 0; /* Enable I/O decode to LPC bus */

1 0

New patch to review for coreboot: southbridge/amd/cimx: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16474 -gerrit commit 245d0e63e1296a34273f3fc939283dda1bde88d9 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/cimx: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/cimx. Change-Id: Ibe2766b956b0ca02be63621aee9a230b16d9923b Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 5af2a5e..d706a56 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -30,7 +30,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -65,7 +65,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -79,7 +79,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 866353d..3e2c10a 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -28,7 +28,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0);

1 0

New patch to review for coreboot: southbridge/amd/amd8111: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16473 -gerrit commit 4d4704d2273b92906902a477bd80b5dbdb9b75ec Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/amd/amd8111: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/amd8111. Change-Id: I76cdc32171b7ce819b53c534b3a5e57e9dd5f3dd Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/amd8111/amd8111.h | 2 ++ src/southbridge/amd/amd8111/early_ctrl.c | 8 ++++---- src/southbridge/amd/amd8111/early_smbus.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h index e877f2a..10df590 100644 --- a/src/southbridge/amd/amd8111/amd8111.h +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -3,7 +3,9 @@ #include "chip.h" +#ifndef __SIMPLE_DEVICE__ void amd8111_enable(device_t dev); +#endif #ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index d84ef18..15f3123 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -4,7 +4,7 @@ /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one 8111 on a hypertransport chain/bus. @@ -19,7 +19,7 @@ static unsigned get_sbdn(unsigned bus) static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; uint8_t byte; dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI @@ -48,7 +48,7 @@ void hard_reset(void) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI @@ -61,7 +61,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index aed4ebb..4c0ace5 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -4,7 +4,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; uint8_t enable; dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);

1 0

New patch to review for coreboot: northbridge/intel/x4x: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16472 -gerrit commit 70bb5098088a18a48f70055c56a875fd2f665137 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/intel/x4x: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/x4x. Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/x4x/early_init.c | 2 +- src/northbridge/intel/x4x/x4x.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index a430538..1b0d4f9 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -23,7 +23,7 @@ void x4x_early_init(void) { - const device_t d0f0 = PCI_DEV(0, 0, 0); + const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e02ee02..a97734d 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -324,6 +324,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map); void raminit_ddr2(struct sysinfo *); struct acpi_rsdp; +#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); +#endif /* __SIMPLE_DEVICE__ */ #endif #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */

1 0

New patch to review for coreboot: northbridge/intel/i5000: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16471 -gerrit commit 3ed7eac53a65ee0285a48445db541981272e4a95 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/intel/i5000: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/i5000. Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i5000/raminit.c | 34 +++++++++++++++++----------------- src/northbridge/intel/i5000/raminit.h | 2 +- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index ef49380..a0bfd1b 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -86,7 +86,7 @@ static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) { u16 status; - device_t dev = d->branch->branchdev; + pci_devfn_t dev = d->branch->branchdev; int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; @@ -112,7 +112,7 @@ static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) static void i5000_clear_fbd_errors(void) { - device_t dev16_1, dev16_2; + pci_devfn_t dev16_1, dev16_2; dev16_1 = PCI_ADDR(0, 16, 1, 0); dev16_2 = PCI_ADDR(0, 16, 2, 0); @@ -141,7 +141,7 @@ static void i5000_clear_fbd_errors(void) static int i5000_branch_reset(struct i5000_fbd_branch *b) { - device_t dev = b->branchdev; + pci_devfn_t dev = b->branchdev; pci_write_config8(dev, I5000_FBDRST, 0x00); @@ -337,7 +337,7 @@ static int i5000_read_spd_data(struct i5000_fbdimm *d) static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) { u16 status; - device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + pci_devfn_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; int timeout = 1000; @@ -360,7 +360,7 @@ static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out) { u16 status; - device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + pci_devfn_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; int timeout = 1000; @@ -658,7 +658,7 @@ static int i5000_amb_preinit(struct i5000_fbdimm *d) static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) { int timeout = 10000; - device_t dev = b->branchdev; + pci_devfn_t dev = b->branchdev; printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state); @@ -681,7 +681,7 @@ static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) { int i = 10; - device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + pci_devfn_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, c->num ? I5000_FBDISTS1 : I5000_FBDISTS0); printk(BIOS_DEBUG, " waiting for pattern recognition..."); @@ -703,7 +703,7 @@ static const char *pattern_names[16] = { static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait) { - device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + pci_devfn_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, c->num ? I5000_FBDICMD1 : I5000_FBDICMD0); printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", @@ -720,7 +720,7 @@ static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wai static int i5000_set_ambpresent(struct i5000_fbd_channel *c) { int i; - device_t branchdev = c->branch->branchdev; + pci_devfn_t branchdev = c->branch->branchdev; u16 ambpresent = 0x8000; for (i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { @@ -740,7 +740,7 @@ static int i5000_set_ambpresent(struct i5000_fbd_channel *c) static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad) { - device_t branchdev = c->branch->branchdev; + pci_devfn_t branchdev = c->branch->branchdev; int off = c->num ? 0x100 : 0; u32 portctl; int i, cnt = 1000; @@ -833,7 +833,7 @@ static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c) static int i5000_setup_channel(struct i5000_fbd_channel *c) { - device_t branchdev = c->branch->branchdev; + pci_devfn_t branchdev = c->branch->branchdev; int off = c->branch->num ? 0x100 : 0; u32 val; @@ -857,7 +857,7 @@ static int i5000_setup_channel(struct i5000_fbd_channel *c) static int i5000_link_training0(struct i5000_fbd_branch *b) { - device_t branchdev = b->branchdev; + pci_devfn_t branchdev = b->branchdev; pci_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1); @@ -1186,7 +1186,7 @@ static int get_dmir(u8 *rankmap, int *_set, int limit) static int i5000_setup_dmir(struct i5000_fbd_branch *b) { struct i5000_fbdimm *d; - device_t dev = b->branchdev; + pci_devfn_t dev = b->branchdev; u8 rankmap = 0, dmir = 0; u32 dmirval = 0; int i, set, rankoffset = 0, ranksize = 0, ranks = 0; @@ -1250,7 +1250,7 @@ static int i5000_setup_dmir(struct i5000_fbd_branch *b) static void i5000_setup_interleave(struct i5000_fbd_setup *setup) { - device_t dev16 = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev16 = PCI_ADDR(0, 16, 1, 0); u32 mir0, mir1, mir2, size0, size1, minsize, tmp; size0 = i5000_setup_dmir(&setup->branch[1]) >> 12; @@ -1289,7 +1289,7 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) { - device_t dev16 = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev16 = PCI_ADDR(0, 16, 1, 0); u32 tolm, drta, drtb, mc, mca; int t_wrc, bl2; @@ -1453,7 +1453,7 @@ static void i5000_reserved_register_init(struct i5000_fbd_setup *setup) } static void i5000_dump_error_registers(void) { - device_t dev = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev = PCI_ADDR(0, 16, 1, 0); printk(BIOS_ERR, "Dump of FBD error registers:\n" "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" @@ -1536,7 +1536,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) { int fbd, fsb, ddrfrq, ddrfrqnow; msr_t msr; - device_t dev = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev = PCI_ADDR(0, 16, 1, 0); switch(setup->ddr_speed) { case DDR_667MHZ: diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h index ab51fb1..0c55443 100644 --- a/src/northbridge/intel/i5000/raminit.h +++ b/src/northbridge/intel/i5000/raminit.h @@ -276,7 +276,7 @@ struct i5000_fbd_channel { struct i5000_fbd_branch { struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; struct i5000_fbd_setup *setup; - device_t branchdev; + pci_devfn_t branchdev; int num; int used; /* memory size in MB on this branch */

1 0

New patch to review for coreboot: northbridge/intel/fsp_rangeley: transition away from device_t
by Antonello Dettori 03 Sep '16

03 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16470 -gerrit commit 85f97c688ef3bdff7103f6a75a529d02a138b3ed Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/intel/fsp_rangeley: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/fsp_rangeley. Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 61931fd..ba4cfdd 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -72,7 +72,7 @@ void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); -#if ENV_RAMSTAGE +#ifndef __SIMPLE_DEVICE__ void northbridge_acpi_fill_ssdt_generator(device_t device); #endif

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2022

2021

2020

2019

2018

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2016

2015

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2013

coreboot-gerrit September 2016