coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: nb/intel/x4x: Increase MMIO PCI space to 2GiB
by Damien Zammit 04 Sep '16

04 Sep '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16494 -gerrit commit ef0a933b90bb1a0045a5d68d0c4cbd6a37dfa851 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Sep 5 02:32:40 2016 +1000 nb/intel/x4x: Increase MMIO PCI space to 2GiB This is necessary for PCI express graphics card add-ons, otherwise the pci allocator cannot fit the mmio for the add on card into the space it has available and the OS turns off the card. Old value was 1GiB. Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit_ddr2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index ed6ab60..206ea0b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1633,7 +1633,7 @@ static void mmap_ddr2(struct sysinfo *s) gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; tsegsize = 1; // 1MB TSEG - mmiosize = 0x400; // 1GB MMIO + mmiosize = 0x800; // 2GB MMIO tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom);

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Patch set updated for coreboot: nb/intel/x4x: Fix DMI init
by Damien Zammit 04 Sep '16

04 Sep '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16491 -gerrit commit 12da510e67f0e260f8a6548871d3a78c90bc6b2f Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun Sep 4 23:49:10 2016 +1000 nb/intel/x4x: Fix DMI init No more hang on DMI init when loop for DMI is re-enabled. This has been tested on GA-G41M-ES2L with patches following. An NVIDIA GT218 card was detected by the OS and displayed using the nouveau driver with no blobs. Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/pcie.c | 148 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 137 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index d432fea..0dd5313 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -26,42 +26,168 @@ #include "x4x.h" #define DEFAULT_RCBA 0xfed1c000 +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) static void init_egress(void) { + const u32 v2c_800 = 0x00014514; + const u32 v2c_1066 = 0x0001a6db; + const u32 v2c_1333 = 0x00022861; + u32 reg32; + /* VC0: TC0 only */ EPBAR8(0x14) = 1; EPBAR8(0x4) = 1; + switch (MCHBAR32(0xc00) & 0x7) { + case 0x0: + // FSB 1066 + EPBAR32(0x2c) = v2c_1066; + break; + case 0x2: + // FSB 800 + EPBAR32(0x2c) = v2c_800; + break; + default: + case 0x4: + // FSB 1333 + EPBAR32(0x2c) = v2c_1333; + break; + } + EPBAR32(0x28) = 0x0a0a0a0a; + EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2; + EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000; + MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7; + /* VC1: ID1, TC7 */ - EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); - EPBAR8(0x20) = 1 << 7; + reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); + reg32 = (reg32 & ~0xfe) | (1 << 7); + EPBAR32(0x20) = reg32; + + /* Init VC1 port arbitration table */ + EPBAR32(0x100) = 0x001000001; + EPBAR32(0x104) = 0x000040000; + EPBAR32(0x108) = 0x000001000; + EPBAR32(0x10c) = 0x000000040; + EPBAR32(0x110) = 0x001000001; + EPBAR32(0x114) = 0x000040000; + EPBAR32(0x118) = 0x000001000; + EPBAR32(0x11c) = 0x000000040; + + /* Load table */ + reg32 = EPBAR32(0x20) | (1 << 16); + EPBAR32(0x20) = reg32; + asm("nop"); + EPBAR32(0x20) = reg32; + + /* Wait for table load */ + while ((EPBAR8(0x26) & (1 << 0)) != 0) ; /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0) ; + /* Wait for VC1 */ + while ((EPBAR8(0x26) & (1 << 1)) != 0) ; - printk(BIOS_DEBUG, "Done EP loop\n"); + printk(BIOS_DEBUG, "Done Egress Port\n"); } static void init_dmi(void) { + u32 reg32; + u16 reg16; + + /* Assume IGD present */ + + /* Clear error status */ + DMIBAR32(0x1c4) = 0xffffffff; + DMIBAR32(0x1d0) = 0xffffffff; + /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) = 1; DMIBAR8(0x4) = 1; /* VC1: ID1, TC7 */ - DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); - DMIBAR8(DMIVC1RCTL) = 1 << 7; + reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); + reg32 = (reg32 & ~0xff) | 1 << 7; /* VC1: enable */ - DMIBAR32(DMIVC1RCTL) |= 1 << 31; + reg32 |= 1 << 31; + reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17); + + DMIBAR32(DMIVC1RCTL) = reg32; + + /* Southbridge RCBA setup */ + RCBA8(0x3022) &= ~1; + + reg32 = (0x5 << 28) | (1 << 6); // PCIe x4 + RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32; + + /* Assign VC1 id 1 */ + RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24); + + /* Map TC7 to VC1 */ + RCBA8(0x20) &= 1; + RCBA8(0x20) |= 1 << 7; - // Hangs - //while ((DMIBAR8(0x26) & 2) != 0) ; - //printk(BIOS_DEBUG, "Done DMI loop\n"); + /* Map TC0 to VC0 */ + RCBA8(0x14) &= 1; + /* Init DMI VC1 port arbitration table */ + RCBA32(0x20) &= 0xfff1ffff; + RCBA32(0x20) |= 1 << 19; + + RCBA32(0x30) = 0x0000000f; + RCBA32(0x34) = 0x000f0000; + RCBA32(0x38) = 0; + RCBA32(0x3c) = 0x000000f0; + RCBA32(0x40) = 0x0f000000; + RCBA32(0x44) = 0; + RCBA32(0x48) = 0x0000f000; + RCBA32(0x4c) = 0; + RCBA32(0x50) = 0x0000000f; + RCBA32(0x54) = 0x000f0000; + RCBA32(0x58) = 0; + RCBA32(0x5c) = 0x000000f0; + RCBA32(0x60) = 0x0f000000; + RCBA32(0x64) = 0; + RCBA32(0x68) = 0x0000f000; + RCBA32(0x6c) = 0; + + RCBA32(0x20) |= 1 << 16; + + /* Enable VC1 */ + RCBA32(0x20) |= 1 << 31; + + /* Wait for VC1 */ + while ((RCBA8(0x26) & (1 << 1)) != 0); + + /* Wait for table load */ + while ((RCBA8(0x26) & (1 << 0)) != 0); + + /* ASPM on DMI link */ + RCBA16(0x1a8) &= ~0x3; + reg16 = RCBA16(0x1a8); + RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10); + reg32 = RCBA32(0x2010); + + /* Set up VC1 max time */ + RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; + + while ((DMIBAR32(0x26) & (1 << 1)) != 0); + printk(BIOS_DEBUG, "Done DMI setup\n"); + + /* ASPM on DMI */ + DMIBAR32(0x200) &= ~(0x3 << 26); + DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; + DMIBAR32(0x88) &= ~0x3; + DMIBAR32(0x88) |= 0x3; + reg16 = DMIBAR16(0x88); +} + +/* DMIBAR32(0x0028) = 0x00000001; DMIBAR32(0x002c) = 0x86000000; DMIBAR32(0x0040) = 0x08010005; @@ -167,7 +293,7 @@ static void init_dmi(void) EPBAR32(0x68) = 0x00008000; EPBAR32(0x70) = 0x03000002; EPBAR32(0x78) = 0x00030000; -} +*/ void x4x_late_init(void) {

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New patch to review for coreboot: Kconfig: Relocate DEVICETREE symbol
by Marshall Dawson 04 Sep '16

04 Sep '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16493 -gerrit commit 21529d251b21bded15f5bd5a57290a0da8f51514 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Sep 4 08:38:33 2016 -0600 Kconfig: Relocate DEVICETREE symbol Place config DEVICETREE after the sourced mainboard Kconfig. This gives the mainboard the opportunity to set a unique default value. Change-Id: Id877e1e8f555334a99b6c0ee1782d06a4a2b7a04 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/Kconfig | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 64da061..a43a979 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -341,17 +341,6 @@ config BOARD_ID_STRING This string is placed in the 'board_id' CBFS file for indicating board type. -config DEVICETREE - string - default "devicetree.cb" - help - This symbol allows mainboards to select a different file under their - mainboard directory for the devicetree.cb file. This allows the board - variants that need different devicetrees to be in the same directory. - - Examples: "devicetree.variant.cb" - "variant/devicetree.cb" - config RAM_CODE_SUPPORT bool default n @@ -382,6 +371,17 @@ menu "Mainboard" source "src/mainboard/Kconfig" +config DEVICETREE + string + default "devicetree.cb" + help + This symbol allows mainboards to select a different file under their + mainboard directory for the devicetree.cb file. This allows the board + variants that need different devicetrees to be in the same directory. + + Examples: "devicetree.variant.cb" + "variant/devicetree.cb" + # defaults for CBFS_SIZE are set at the end of the file. config CBFS_SIZE hex "Size of CBFS filesystem in ROM"

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New patch to review for coreboot: nb/intel/x4x: Fix DMI init
by Damien Zammit 04 Sep '16

04 Sep '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16491 -gerrit commit 6d9b310a447ebd9104689d6e8acfa56b6647e189 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun Sep 4 23:49:10 2016 +1000 nb/intel/x4x: Fix DMI init No more hang on DMI init when loop for DMI is re-enabled. Need to test this on GA-G41M-ES2L to see if PCIe add-on cards are now working or not. Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/pcie.c | 148 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 137 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index d432fea..0dd5313 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -26,42 +26,168 @@ #include "x4x.h" #define DEFAULT_RCBA 0xfed1c000 +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) static void init_egress(void) { + const u32 v2c_800 = 0x00014514; + const u32 v2c_1066 = 0x0001a6db; + const u32 v2c_1333 = 0x00022861; + u32 reg32; + /* VC0: TC0 only */ EPBAR8(0x14) = 1; EPBAR8(0x4) = 1; + switch (MCHBAR32(0xc00) & 0x7) { + case 0x0: + // FSB 1066 + EPBAR32(0x2c) = v2c_1066; + break; + case 0x2: + // FSB 800 + EPBAR32(0x2c) = v2c_800; + break; + default: + case 0x4: + // FSB 1333 + EPBAR32(0x2c) = v2c_1333; + break; + } + EPBAR32(0x28) = 0x0a0a0a0a; + EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2; + EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000; + MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7; + /* VC1: ID1, TC7 */ - EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); - EPBAR8(0x20) = 1 << 7; + reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); + reg32 = (reg32 & ~0xfe) | (1 << 7); + EPBAR32(0x20) = reg32; + + /* Init VC1 port arbitration table */ + EPBAR32(0x100) = 0x001000001; + EPBAR32(0x104) = 0x000040000; + EPBAR32(0x108) = 0x000001000; + EPBAR32(0x10c) = 0x000000040; + EPBAR32(0x110) = 0x001000001; + EPBAR32(0x114) = 0x000040000; + EPBAR32(0x118) = 0x000001000; + EPBAR32(0x11c) = 0x000000040; + + /* Load table */ + reg32 = EPBAR32(0x20) | (1 << 16); + EPBAR32(0x20) = reg32; + asm("nop"); + EPBAR32(0x20) = reg32; + + /* Wait for table load */ + while ((EPBAR8(0x26) & (1 << 0)) != 0) ; /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0) ; + /* Wait for VC1 */ + while ((EPBAR8(0x26) & (1 << 1)) != 0) ; - printk(BIOS_DEBUG, "Done EP loop\n"); + printk(BIOS_DEBUG, "Done Egress Port\n"); } static void init_dmi(void) { + u32 reg32; + u16 reg16; + + /* Assume IGD present */ + + /* Clear error status */ + DMIBAR32(0x1c4) = 0xffffffff; + DMIBAR32(0x1d0) = 0xffffffff; + /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) = 1; DMIBAR8(0x4) = 1; /* VC1: ID1, TC7 */ - DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); - DMIBAR8(DMIVC1RCTL) = 1 << 7; + reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); + reg32 = (reg32 & ~0xff) | 1 << 7; /* VC1: enable */ - DMIBAR32(DMIVC1RCTL) |= 1 << 31; + reg32 |= 1 << 31; + reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17); + + DMIBAR32(DMIVC1RCTL) = reg32; + + /* Southbridge RCBA setup */ + RCBA8(0x3022) &= ~1; + + reg32 = (0x5 << 28) | (1 << 6); // PCIe x4 + RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32; + + /* Assign VC1 id 1 */ + RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24); + + /* Map TC7 to VC1 */ + RCBA8(0x20) &= 1; + RCBA8(0x20) |= 1 << 7; - // Hangs - //while ((DMIBAR8(0x26) & 2) != 0) ; - //printk(BIOS_DEBUG, "Done DMI loop\n"); + /* Map TC0 to VC0 */ + RCBA8(0x14) &= 1; + /* Init DMI VC1 port arbitration table */ + RCBA32(0x20) &= 0xfff1ffff; + RCBA32(0x20) |= 1 << 19; + + RCBA32(0x30) = 0x0000000f; + RCBA32(0x34) = 0x000f0000; + RCBA32(0x38) = 0; + RCBA32(0x3c) = 0x000000f0; + RCBA32(0x40) = 0x0f000000; + RCBA32(0x44) = 0; + RCBA32(0x48) = 0x0000f000; + RCBA32(0x4c) = 0; + RCBA32(0x50) = 0x0000000f; + RCBA32(0x54) = 0x000f0000; + RCBA32(0x58) = 0; + RCBA32(0x5c) = 0x000000f0; + RCBA32(0x60) = 0x0f000000; + RCBA32(0x64) = 0; + RCBA32(0x68) = 0x0000f000; + RCBA32(0x6c) = 0; + + RCBA32(0x20) |= 1 << 16; + + /* Enable VC1 */ + RCBA32(0x20) |= 1 << 31; + + /* Wait for VC1 */ + while ((RCBA8(0x26) & (1 << 1)) != 0); + + /* Wait for table load */ + while ((RCBA8(0x26) & (1 << 0)) != 0); + + /* ASPM on DMI link */ + RCBA16(0x1a8) &= ~0x3; + reg16 = RCBA16(0x1a8); + RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10); + reg32 = RCBA32(0x2010); + + /* Set up VC1 max time */ + RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; + + while ((DMIBAR32(0x26) & (1 << 1)) != 0); + printk(BIOS_DEBUG, "Done DMI setup\n"); + + /* ASPM on DMI */ + DMIBAR32(0x200) &= ~(0x3 << 26); + DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; + DMIBAR32(0x88) &= ~0x3; + DMIBAR32(0x88) |= 0x3; + reg16 = DMIBAR16(0x88); +} + +/* DMIBAR32(0x0028) = 0x00000001; DMIBAR32(0x002c) = 0x86000000; DMIBAR32(0x0040) = 0x08010005; @@ -167,7 +293,7 @@ static void init_dmi(void) EPBAR32(0x68) = 0x00008000; EPBAR32(0x70) = 0x03000002; EPBAR32(0x78) = 0x00030000; -} +*/ void x4x_late_init(void) {

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Patch set updated for coreboot: src/northbridge: Improve code formatting
by HAOUAS Elyes 04 Sep '16

04 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16414 -gerrit commit 6d3ef862c78cce925ec114c38c64f5a4d1b89da1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Sep 2 19:22:00 2016 +0200 src/northbridge: Improve code formatting Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/family10/northbridge.c | 10 +- src/northbridge/amd/agesa/family12/northbridge.c | 316 ++++++++++----------- src/northbridge/amd/agesa/family15/northbridge.c | 4 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 4 +- src/northbridge/amd/amdfam10/chip.h | 2 +- src/northbridge/amd/amdht/comlib.c | 48 ++-- src/northbridge/amd/amdht/ht_wrapper.c | 4 +- src/northbridge/amd/amdk8/amdk8.h | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 31 +- src/northbridge/amd/cimx/rd890/early.c | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/e7501/debug.c | 88 +++--- src/northbridge/intel/e7501/northbridge.c | 40 +-- src/northbridge/intel/e7505/debug.c | 86 +++--- src/northbridge/intel/e7505/northbridge.c | 44 +-- src/northbridge/intel/haswell/northbridge.c | 24 +- src/northbridge/intel/i3100/northbridge.c | 14 +- src/northbridge/intel/i3100/raminit_ep80579.c | 2 +- src/northbridge/intel/i5000/raminit.c | 4 +- src/northbridge/intel/i855/debug.c | 40 +-- src/northbridge/intel/i855/northbridge.c | 66 ++--- src/northbridge/intel/i855/raminit.c | 34 +-- src/northbridge/intel/i945/debug.c | 34 +-- src/northbridge/intel/pineview/gma.c | 30 +- src/northbridge/intel/x4x/x4x.h | 46 +-- src/northbridge/via/cn700/vga.c | 2 +- src/northbridge/via/cx700/vga.c | 2 +- src/northbridge/via/vx800/detection.c | 12 +- src/northbridge/via/vx800/vga.c | 2 +- 35 files changed, 504 insertions(+), 511 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1c8f904..e7bfdd8 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -41,8 +41,8 @@ extern uint32_t agesawrapper_amdinitmid(void); typedef struct amdfam10_sysconf_t sys_info_conf_t; typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 } dram_base_mask_t; @@ -218,9 +218,9 @@ static device_t get_node_pci(u32 nodeid, u32 fn) static unsigned int read_nb_cfg_54(void) { - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - return (( msr.hi >> (54-32)) & 1); + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + return (( msr.hi >> (54-32)) & 1); } static void get_fx_devs(void) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index df6b3e4..1526972 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -269,47 +269,47 @@ struct hw_mem_hole_info { static struct hw_mem_hole_info get_hw_mem_hole_info(void) { - struct hw_mem_hole_info mem_hole; - - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - - struct dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(0); - if (d.mask & 1) { - hole = pci_read_config32(__f1_dev[0], 0xf0); - if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = 0; // record the node No with hole - } - } + struct hw_mem_hole_info mem_hole; + + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + + struct dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(0); + if (d.mask & 1) { + hole = pci_read_config32(__f1_dev[0], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = 0; // record the node No with hole + } + } #if 0 /* We need to double check if there is special set on base reg and limit reg * are not continuous instead of hole, it will find out its hole_startk. */ - if (mem_hole.node_id==-1) { - resource_t limitk_pri = 0; - struct dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(0); - if (d.base & 1) { - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k <= 4 *1024 * 1024) { - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G - mem_hole.node_id = 0; - } - } - - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } + if (mem_hole.node_id==-1) { + resource_t limitk_pri = 0; + struct dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(0); + if (d.base & 1) { + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (base_k <= 4 *1024 * 1024) { + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G + mem_hole.node_id = 0; + } + } + + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } #endif - return mem_hole; + return mem_hole; } #endif @@ -471,44 +471,44 @@ static void setup_uma_memory(void) static void domain_read_resources(device_t dev) { - unsigned reg; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xc0; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned nodeid, reg_link; - device_t reg_dev; - if (reg<0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - struct resource *resource; - /* Initialize the system-wide I/O space constraints. */ + unsigned reg; + + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xc0; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + + struct resource *resource; + /* Initialize the system-wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0x1000; + resource->base = 0x1000; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; @@ -520,40 +520,40 @@ static void domain_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void domain_set_resources(device_t dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); - - unsigned long mmio_basek; - u32 pci_tolm; - u64 ramtop = 0; - int idx; - struct bus *link; + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); + + unsigned long mmio_basek; + u32 pci_tolm; + u64 ramtop = 0; + int idx; + struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; #endif - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); - } + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = my_find_pci_tolm(link, pci_tolm); + } - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -562,77 +562,76 @@ static void domain_set_resources(device_t dev) * otherwise We reset the hole to the mmio_basek */ - mem_hole = get_hw_mem_hole_info(); + mem_hole = get_hw_mem_hole_info(); - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } #endif - idx = 0x10; + idx = 0x10; - struct dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T + struct dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(0); + d = get_dram_base_mask(0); - if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); -printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); + if (d.mask & 1) { + basek = ((resource_t)(d.base)) << 8; + limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); + printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); - /* Convert these values to multiples of 1K for ease of math. */ - basek >>= 10; - limitk >>= 10; - sizek = limitk - basek + 1; + /* Convert these values to multiples of 1K for ease of math. */ + basek >>= 10; + limitk >>= 10; + sizek = limitk - basek + 1; -printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek); + printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek); - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < 640) && (sizek > 768)) { -printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); - ram_resource(dev, (idx | 0), basek, 640 - basek); - idx += 0x10; - basek = 768; - sizek = limitk - 768; - } + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < 640) && (sizek > 768)) { + printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); + ram_resource(dev, (idx | 0), basek, 640 - basek); + idx += 0x10; + basek = 768; + sizek = limitk - 768; + } printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { - if (basek <= mmio_basek) { - unsigned pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { - ram_resource(dev, idx, basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } - else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - - ram_resource(dev, (idx | 0), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - 0, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; - } + /* split the region to accommodate pci memory space */ + if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, idx, basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + if (!ramtop) + ramtop = mmio_basek * 1024; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + + ram_resource(dev, (idx | 0), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + 0, mmio_basek, basek, limitk); + if (!ramtop) + ramtop = limitk * 1024; + } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA @@ -642,13 +641,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); set_top_of_ram(ramtop); #endif - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } -printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + for (link = dev->link_list; link; link = link->next) { + if (link->children) + assign_resources(link); + } + printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index f347b63..0c14bdd 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1080,9 +1080,9 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = 3; /* FIXME */ if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index ccb256b..d1560b7 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -1070,9 +1070,9 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = 3; /* FIXME */ if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 63ca2af..7b57cc3 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1069,9 +1069,9 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = 3; /* FIXME */ if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index c0769e7..28302ef 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1086,9 +1086,9 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = 3; /* FIXME */ if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h index 60dc00f..daf429d 100644 --- a/src/northbridge/amd/amdfam10/chip.h +++ b/src/northbridge/amd/amdfam10/chip.h @@ -19,7 +19,7 @@ #include <stdint.h> struct northbridge_amd_amdfam10_config { - uint64_t maximum_memory_capacity; + uint64_t maximum_memory_capacity; }; #endif /* _AMD_FAM10_CHIP_H_ */ diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index e2d158f..64092ff 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -249,38 +249,38 @@ void ErrorStop(u32 value) ; ; For use with SimNow the unrotated error code is also written to port 84h ErrorStop PROC FAR PASCAL PUBLIC Value:DWORD - pushad - mov eax, Value - mov bx, 0DEADh - out 84h, eax + pushad + mov eax, Value + mov bx, 0DEADh + out 84h, eax ErrorStopTop: - out 80h, eax + out 80h, eax - mov cx, 4 ; Rotate the display by one nibble + mov cx, 4 ; Rotate the display by one nibble @@: - bt bx, 15 - rcl eax, 1 - rcl bx, 1 - loop @B + bt bx, 15 + rcl eax, 1 + rcl bx, 1 + loop @B - push eax ; Delay a few hundred milliseconds - push ebx - mov ecx, 10h ; TSC - db 00Fh, 032h ; RDMSR - mov ebx, eax + push eax ; Delay a few hundred milliseconds + push ebx + mov ecx, 10h ; TSC + db 00Fh, 032h ; RDMSR + mov ebx, eax @@: - db 00Fh, 032h ; RDMSR - sub eax, ebx - cmp eax, 500000000 - jb @B - pop ebx - pop eax + db 00Fh, 032h ; RDMSR + sub eax, ebx + cmp eax, 500000000 + jb @B + pop ebx + pop eax - jmp ErrorStopTop + jmp ErrorStopTop - popad - ret + popad + ret ErrorStop ENDP */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index f31fcd2..0dfc6ab 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -29,9 +29,9 @@ /* Single CPU system? */ #if (CONFIG_MAX_PHYSICAL_CPUS == 1) /* FIXME - * This #define is used by other #included .c files + * This #define is used by other #included .c files * When set, multiprocessor support is completely disabled - */ + */ #define HT_BUILD_NC_ONLY 1 #endif diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..2cde166 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -6,9 +6,9 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - #include "f.h" + #include "f.h" #else - #include "pre_f.h" + #include "pre_f.h" #endif #ifdef __PRE_RAM__ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0c37366..08d8d43 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2398,10 +2398,10 @@ static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanosec tsc_msr = rdmsr(0x00000010); start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; - do { + do { tsc_msr = rdmsr(0x00000010); current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; - } while ((current_timestamp - start_timestamp) < cycle_count); + } while ((current_timestamp - start_timestamp) < cycle_count); } static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 324e35e..8024179 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -930,7 +930,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 0ba2d33..143468a 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -476,34 +476,31 @@ static void mctHookAfterDramInit(void) #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ static void vErratum372(struct DCTStatStruc *pDCTstat) { - msr_t msr = rdmsr(NB_CFG_MSR); + msr_t msr = rdmsr(NB_CFG_MSR); int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32))); - // is this the right way to check for NB pstate 1 or DDR3-1333 ? - if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) - &&(!pDCTstat->GangedMode)) { - /* DisableCf8ExtCfg */ - msr.hi &= ~(3 << (51 - 32)); - wrmsr(NB_CFG_MSR, msr); - } + // is this the right way to check for NB pstate 1 or DDR3-1333 ? + if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) + &&(!pDCTstat->GangedMode)) { + /* DisableCf8ExtCfg */ + msr.hi &= ~(3 << (51 - 32)); + wrmsr(NB_CFG_MSR, msr); + } } static void vErratum414(struct DCTStatStruc *pDCTstat) { - int dct=0; - for (; dct < 2 ; dct++) - { - int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); + int dct=0; + for (; dct < 2 ; dct++) { + int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); int powerDown = dRAMConfigHi & (1 << PowerDownEn ); int ddr3 = dRAMConfigHi & (1 << Ddr3Mode ); - int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); + int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel); - if (powerDown && ddr3 && pchgPDModeSel ) - { - Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); + if (powerDown && ddr3 && pchgPDModeSel ) + Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); } - } } #endif diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c index 5852aa3..4904e52 100644 --- a/src/northbridge/amd/cimx/rd890/early.c +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -34,7 +34,7 @@ void sr56x0_rd890_disable_pcie_bridge(void) AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); - nb_cfg->ConfigPtr = &cfg_ptr; + nb_cfg->ConfigPtr = &cfg_ptr; nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); val = (1 << 2) | (1 << 3); /*GPP1*/ val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index c55cefb..0f9e5f5 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -1077,7 +1077,7 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 1caecf9..efee0a4 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1077,7 +1077,7 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6f7f993..6d5418a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1108,7 +1108,7 @@ static void cpu_bus_scan(device_t dev) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index af9a8bf..9246106 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -35,7 +35,7 @@ static void dump_pci_device(unsigned dev) for (i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "\n%02x:",i); + printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config8(dev, i); printk(BIOS_DEBUG, " %02x", val); } @@ -61,19 +61,19 @@ static inline void dump_pci_devices(void) static inline void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } + device_t dev; + for (dev = PCI_DEV(busn, 0, 0); + dev <= PCI_DEV(busn, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } } static inline void dump_spd_registers(const struct mem_controller *ctrl) @@ -103,18 +103,18 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); + printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); for (j = 0; j < 128; j++) { int status; unsigned char byte; if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); status = smbus_read_byte(device, j); if (status < 0) { break; } byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); + printk(BIOS_DEBUG, "%02x ", byte); } printk(BIOS_DEBUG, "\n"); } @@ -123,24 +123,24 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) static inline void dump_smbus_registers(void) { unsigned device; - printk(BIOS_DEBUG, "\n"); - for (device = 1; device < 0x80; device++) { - int j; + printk(BIOS_DEBUG, "\n"); + for (device = 1; device < 0x80; device++) { + int j; if ( smbus_read_byte(device, 0) < 0 ) continue; printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { + for (j = 0; j < 256; j++) { + int status; + unsigned char byte; + status = smbus_read_byte(device, j); + if (status < 0) { break; - } - if ((j & 0xf) == 0) + } + if ((j & 0xf) == 0) printk(BIOS_DEBUG, "\n%02x: ",j); - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); + byte = status & 0xff; + printk(BIOS_DEBUG, "%02x ", byte); + } + printk(BIOS_DEBUG, "\n"); } } @@ -149,28 +149,28 @@ static inline void dump_io_resources(unsigned port) int i; printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) + for (i=0;i<256;i++) { + uint8_t val; + if ((i & 0x0f) == 0) printk(BIOS_DEBUG, "%02x:", i); - val = inb(port); + val = inb(port); printk(BIOS_DEBUG, " %02x",val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } + if ((i & 0x0f) == 0x0f) { + printk(BIOS_DEBUG, "\n"); + } port++; - } + } } static inline void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i=start;i<end;i++) { if ((i & 0xf)==0) printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); - } + } + printk(BIOS_DEBUG, "\n"); +} #endif diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 5296bdb..d4f77ae 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -23,9 +23,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm; - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. @@ -102,36 +102,36 @@ static void pci_domain_set_resources(device_t dev) } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, }; static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, }; static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } } struct chip_operations northbridge_intel_e7501_ops = { diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 33f1ed1..e20d676 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -45,7 +45,7 @@ void dump_pci_device(unsigned dev) for (i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "\n%02x:",i); + printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config8(dev, i); printk(BIOS_DEBUG, " %02x", val); } @@ -71,19 +71,19 @@ void dump_pci_devices(void) void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } + device_t dev; + for (dev = PCI_DEV(busn, 0, 0); + dev <= PCI_DEV(busn, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } } void dump_spd_registers(const struct mem_controller *ctrl) @@ -113,18 +113,18 @@ void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); + printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); for (j = 0; j < 128; j++) { int status; unsigned char byte; if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); status = spd_read_byte(device, j); if (status < 0) { break; } byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); + printk(BIOS_DEBUG, "%02x ", byte); } printk(BIOS_DEBUG, "\n"); } @@ -133,24 +133,24 @@ void dump_spd_registers(const struct mem_controller *ctrl) void dump_smbus_registers(void) { unsigned device; - printk(BIOS_DEBUG, "\n"); - for (device = 1; device < 0x80; device++) { - int j; + printk(BIOS_DEBUG, "\n"); + for (device = 1; device < 0x80; device++) { + int j; if ( spd_read_byte(device, 0) < 0 ) continue; printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = spd_read_byte(device, j); - if (status < 0) { + for (j = 0; j < 256; j++) { + int status; + unsigned char byte; + status = spd_read_byte(device, j); + if (status < 0) { break; - } - if ((j & 0xf) == 0) + } + if ((j & 0xf) == 0) printk(BIOS_DEBUG, "\n%02x: ",j); - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); + byte = status & 0xff; + printk(BIOS_DEBUG, "%02x ", byte); + } + printk(BIOS_DEBUG, "\n"); } } @@ -159,27 +159,27 @@ void dump_io_resources(unsigned port) int i; printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) + for (i=0;i<256;i++) { + uint8_t val; + if ((i & 0x0f) == 0) printk(BIOS_DEBUG, "%02x:", i); - val = inb(port); + val = inb(port); printk(BIOS_DEBUG, " %02x",val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } + if ((i & 0x0f) == 0x0f) { + printk(BIOS_DEBUG, "\n"); + } port++; - } + } } void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i=start;i<end;i++) { if ((i & 0xf)==0) printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); + } + printk(BIOS_DEBUG, "\n"); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 4a3e993..71b19f6 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -12,16 +12,16 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ - return current; + /* Just a dummy */ + return current; } static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm; - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. @@ -108,37 +108,37 @@ static struct pci_operations intel_pci_ops = { }; static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .ops_pci = &intel_pci_ops, .ops_pci_bus = pci_bus_default_ops, }; static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, }; static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } } struct chip_operations northbridge_intel_e7505_ops = { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4af6e11..d4b6e90 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -101,8 +101,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, - u32 *len) +static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -122,7 +121,7 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; int (*get_resource)(device_t dev, unsigned int index, - u32 *base, u32 *size); + u32 *base, u32 *size); const char *description; }; @@ -154,13 +153,13 @@ static void mc_add_fixed_mmio_resources(device_t dev) size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + &base, &size)) continue; resource = new_resource(dev, mc_fixed_resources[i].index); resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", @@ -198,8 +197,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, - uint64_t *result) +static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; @@ -345,16 +343,16 @@ static void mc_add_dram_resources(device_t dev) resource->base = mc_values[TSEG_REG]; resource->size = mc_values[BGSM_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; /* BGSM -> TOLUD */ resource = new_resource(dev, index++); resource->base = mc_values[BGSM_REG]; resource->size = mc_values[TOLUD_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; /* 4GiB -> TOUUD */ base_k = 4096 * 1024; /* 4GiB */ @@ -370,7 +368,7 @@ static void mc_add_dram_resources(device_t dev) */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + (0x100000 - 0xc0000) >> 10); #if CONFIG_CHROMEOS_RAMOOPS reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index c8e3221..a48d8fe 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -40,7 +40,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; u32 pci_tolm; - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -211,15 +211,15 @@ static const struct pci_driver mc_driver __pci_driver = { static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, }; diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 497339c..001ec0d 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -618,7 +618,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); do data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000); - } + } udelay(16); /* No command */ diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index ef49380..ed3f0b4 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -599,7 +599,7 @@ static int i5000_ddr_init(struct i5000_fbdimm *d) val = (d->setup->t_al << 19) | ((odt & 1) << 18) | - ((odt & 2) << 21) | 1; + ((odt & 2) << 21) | 1; printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val); @@ -1268,7 +1268,7 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) mir0 = (size0 << 1) | 3; mir1 = (size0 << 1); mir2 = (size0 << 1); - } else if (!size0) { + } else if (!size0) { mir0 = size1 | 1; mir1 = size1; mir2 = size1; diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index 05e934d..2a9e407 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -104,26 +104,26 @@ static inline void dump_spd_registers(void) static inline void dump_smbus_registers(void) { - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 1; i < 0x80; i++) { - unsigned device; - device = i; - int j; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); - status = smbus_read_byte(device, j); - if (status < 0) { - printk(BIOS_DEBUG, "bad device\n"); - break; - } - byte = status & 0xff; + int i; + printk(BIOS_DEBUG, "\n"); + for (i = 1; i < 0x80; i++) { + unsigned device; + device = i; + int j; + printk(BIOS_DEBUG, "smbus: %02x", device); + for (j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) + printk(BIOS_DEBUG, "\n%02x: ", j); + status = smbus_read_byte(device, j); + if (status < 0) { + printk(BIOS_DEBUG, "bad device\n"); + break; + } + byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); + } + printk(BIOS_DEBUG, "\n"); } } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index e9b1cac..bc497a8 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -30,33 +30,33 @@ static void northbridge_init(device_t dev) { - printk(BIOS_SPEW, "Northbridge init\n"); + printk(BIOS_SPEW, "Northbridge init\n"); } static struct device_operations northbridge_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x3580, + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x3580, }; static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm; - printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); @@ -107,39 +107,39 @@ static void pci_domain_set_resources(device_t dev) } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, }; static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); } static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, }; static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } } struct chip_operations northbridge_intel_i855_ops = { - CHIP_NAME("Intel 855 Northbridge") + CHIP_NAME("Intel 855 Northbridge") .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index fe6059d..43400ab 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -369,32 +369,32 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) PRINTK_DEBUG(" Sending RAM command 0x%08x\n", reg32); pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32); - // RAM_COMMAND_NORMAL is an exception. - // It affects only the memory controller and does not need to be "sent" to the DIMMs. + // RAM_COMMAND_NORMAL is an exception. + // It affects only the memory controller and does not need to be "sent" to the DIMMs. - if (command != RAM_COMMAND_NORMAL) { + if (command != RAM_COMMAND_NORMAL) { - // Send the command to all DIMMs by accessing a memory location within each - // NOTE: for mode select commands, some of the location address bits - // are part of the command + // Send the command to all DIMMs by accessing a memory location within each + // NOTE: for mode select commands, some of the location address bits + // are part of the command - // Map JEDEC mode bits to i855 - if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) { + // Map JEDEC mode bits to i855 + if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) { /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9)); - } + } - for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { - uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); - if (dimm_end_32M_multiple > dimm_start_32M_multiple) { + for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { + uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); + if (dimm_end_32M_multiple > dimm_start_32M_multiple) { - uint32_t dimm_start_address = dimm_start_32M_multiple << 25; + uint32_t dimm_start_address = dimm_start_32M_multiple << 25; PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits); - read32((void *)(dimm_start_address + i855_mode_bits)); + read32((void *)(dimm_start_address + i855_mode_bits)); - // Set the start of the next DIMM - dimm_start_32M_multiple = dimm_end_32M_multiple; - } + // Set the start of the next DIMM + dimm_start_32M_multiple = dimm_end_32M_multiple; + } } } } diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 5b6c87a..d3be886 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -78,21 +78,21 @@ void dump_pci_devices(void) void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while (device <= DIMM3) { - int status = 0; - int i; - printk(BIOS_DEBUG, "\ndimm %02x", device); + unsigned device; + device = DIMM0; + while (device <= DIMM3) { + int status = 0; + int i; + printk(BIOS_DEBUG, "\ndimm %02x", device); - for (i = 0; (i < 256) ; i++) { - if ((i % 16) == 0) { + for (i = 0; (i < 256) ; i++) { + if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - printk(BIOS_DEBUG, "bad device: %02x\n", -status); - break; + if (status < 0) { + printk(BIOS_DEBUG, "bad device: %02x\n", -status); + break; } printk(BIOS_DEBUG, "%02x ", status); } @@ -103,13 +103,13 @@ void dump_spd_registers(void) void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { + for (i=start;i<end;i++) { if ((i & 0xf)==0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); - } + } + printk(BIOS_DEBUG, "\n"); +} diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 989f5ef..335e38a 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -46,31 +46,31 @@ #define PGETBL_ENABLED 0x1 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ - ADPA_CRT_HOTPLUG_WARMUP_10MS | \ - ADPA_CRT_HOTPLUG_MONITOR_COLOR| \ - ADPA_CRT_HOTPLUG_SAMPLE_4S | \ - ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ - ADPA_CRT_HOTPLUG_VOLREF_325MV | \ - ADPA_CRT_HOTPLUG_ENABLE) + ADPA_CRT_HOTPLUG_WARMUP_10MS | \ + ADPA_CRT_HOTPLUG_MONITOR_COLOR| \ + ADPA_CRT_HOTPLUG_SAMPLE_4S | \ + ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ + ADPA_CRT_HOTPLUG_VOLREF_325MV | \ + ADPA_CRT_HOTPLUG_ENABLE) static struct resource *gtt_res = NULL; static struct resource *mmio_res = NULL; static int gtt_setup(u8 *mmiobase) { - u32 gttbase; - device_t dev = dev_find_slot(0, PCI_DEVFN(0,0)); + u32 gttbase; + device_t dev = dev_find_slot(0, PCI_DEVFN(0,0)); - gttbase = pci_read_config32(dev, BGSM); - printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase); + gttbase = pci_read_config32(dev, BGSM); + printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase); - write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB); - udelay(50); - write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB); + write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB); + udelay(50); + write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB); - write32(mmiobase + GFX_FLSH_CNTL, 0); + write32(mmiobase + GFX_FLSH_CNTL, 0); - return 0; + return 0; } static void intel_gma_init(const struct northbridge_intel_pineview_config *info, diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e02ee02..4c61e1c 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -289,29 +289,29 @@ struct sysinfo { }; enum ddr2_signals { - CLKSET0 = 0, - CTRL0, - CLKSET1, - CMD, - CTRL1, - CTRL2, - CTRL3, - DQS1, - DQS2, - DQS3, - DQS4, - DQS5, - DQS6, - DQS7, - DQS8, - DQ1, - DQ2, - DQ3, - DQ4, - DQ5, - DQ6, - DQ7, - DQ8 + CLKSET0 = 0, + CTRL0, + CLKSET1, + CMD, + CTRL1, + CTRL2, + CTRL3, + DQS1, + DQS2, + DQS3, + DQS4, + DQS5, + DQS6, + DQS7, + DQS8, + DQ1, + DQ2, + DQ3, + DQ4, + DQ5, + DQ6, + DQ7, + DQ8 }; #ifndef __BOOTBLOCK__ diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 2e453dc..10b7f65 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -64,7 +64,7 @@ static int via_cn700_int15_handler(void) case 0x5f0f: X86_EAX=0x860f; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 7f9d286..16f0ea0 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -116,7 +116,7 @@ static int via_cx700_int15_handler(void) res=1; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index c2397c8..ce643a0 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -146,16 +146,16 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) LoadNum = (u8) (ModuleDataWidth / ChipWidth); /* Set the RANK map. */ - /* Get bit0,1, the most number of supported RANK is 2. */ + /* Get bit0,1, the most number of supported RANK is 2. */ RankNum = (u8) (pSPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x3); if (RAMTYPE_SDRAMDDR2 == DramAttr->DramType) - /* - * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK - * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK - */ + /* + * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK + * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK + */ RankNum++; - /* Every DIMM have 1 or 2 ranks. */ + /* Every DIMM have 1 or 2 ranks. */ if (RankNum != 2 && RankNum != 1) { Status = CB_DEVICE_ERROR; PRINT_DEBUG_MEM("Memory Device ERROR: Number " diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index f02236d..61d4563 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -114,7 +114,7 @@ static int via_vx800_int15_handler(void) X86_EAX = 0x005f; res = 1; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); X86_EAX = 0;

1 0

Patch set updated for coreboot: console/serialice: Add SerialICE
by Antonello Dettori 04 Sep '16

04 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 07d80294cad66ef98c3a787ddb530668ce10b638 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520 and Lenovo X60. Needs tests: * Ramstage Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/Kconfig | 34 ++++ src/arch/x86/c_start.S | 2 +- src/arch/x86/exception.c | 7 +- src/console/Makefile.inc | 2 + src/console/console.c | 23 --- src/console/init.c | 9 +- src/console/serialice.c | 430 ++++++++++++++++++++++++++++++++++++++++ src/console/serialice_priv.h | 105 ++++++++++ src/include/console/serialice.h | 30 +++ src/include/console/streams.h | 6 - src/include/console/uart.h | 8 - src/include/console/usb.h | 10 - src/include/debug-com.h | 24 +++ src/lib/Makefile.inc | 5 + src/lib/debug-com.c | 99 +++++++++ 15 files changed, 740 insertions(+), 54 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 64da061..270cd70 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1135,6 +1135,40 @@ config DEBUG_PRINT_PAGE_TABLES After the page tables have been built, print them on the debug console. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + default n + depends on ARCH_X86 + depends on CONSOLE_SERIAL || CONSOLE_USB + depends on !GDB_STUB + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +if DEBUG_SERIALICE + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + depends on CONSOLE_SERIAL || USBDEBUG_IN_ROMSTAGE + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + +endif + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 9a64fa6..0946432 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -111,7 +111,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT - call gdb_hw_init + call debug_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 84328be..9c68746 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -14,6 +14,7 @@ #include <console/console.h> #include <console/streams.h> #include <string.h> +#include <debug-com.h> #if CONFIG_GDB_STUB @@ -231,17 +232,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - gdb_tx_byte(ch); + debug_tx_byte(ch); } static inline void stub_flush(void) { - gdb_tx_flush(); + debug_tx_flush(); } static inline int stub_getc(void) { - return gdb_rx_byte(); + return debug_rx_byte(); } static int hex(char ch) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 68afb8a..9514fd3 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/console.c b/src/console/console.c index 7b0dfc2..bb659b4 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -74,26 +74,3 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes) while (number_of_bytes--) console_tx_byte(*buffer++); } - - -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -void gdb_hw_init(void) -{ - __gdb_hw_init(); -} - -void gdb_tx_byte(unsigned char byte) -{ - __gdb_tx_byte(byte); -} - -void gdb_tx_flush(void) -{ - __gdb_tx_flush(); -} - -unsigned char gdb_rx_byte(void) -{ - return __gdb_rx_byte(); -} -#endif diff --git a/src/console/init.c b/src/console/init.c index 189079b..0fe6d7e 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -14,13 +14,14 @@ * GNU General Public License for more details. */ +#include <option.h> +#include <rules.h> +#include <version.h> #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> -#include <option.h> -#include <rules.h> -#include <version.h> /* While in romstage, console loglevel is built-time constant. */ static ROMSTAGE_CONST int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; @@ -43,6 +44,8 @@ asmlinkage void console_init(void) console_hw_init(); + serialice_main(); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..d33e925 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,430 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/serialice.h> +#include <arch/io.h> +#include <debug-com.h> +#include "serialice_priv.h" + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + debug_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + debug_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + val = debug_rx_byte(); + if (val) { +#if ECHO_MODE + sio_putc(val); +#endif + return val; + } + + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = s_cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = s_cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = s_cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = s_cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +void serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } +} diff --git a/src/console/serialice_priv.h b/src/console/serialice_priv.h new file mode 100644 index 0000000..0004c9a --- /dev/null +++ b/src/console/serialice_priv.h @@ -0,0 +1,105 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +#include <stdint.h> + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 s_cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 s_cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 s_cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 s_cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..a2b27e7 --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,30 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#define ECHO_MODE 1 + +#if (ENV_RAMSTAGE && CONFIG_DEBUG_SERIALICE_RAMSTAGE) || \ + (ENV_ROMSTAGE && CONFIG_DEBUG_SERIALICE_ROMSTAGE) +void serialice_main(void); +#else +static inline void serialice_main(void) { } +#endif + +#endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 6e944a6..9b62585 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -27,10 +27,4 @@ void console_tx_flush(void); */ void console_write_line(uint8_t *buffer, size_t number_of_bytes); -/* For remote GDB debugging. */ -void gdb_hw_init(void); -void gdb_tx_byte(unsigned char byte); -void gdb_tx_flush(void); -unsigned char gdb_rx_byte(void); - #endif /* _CONSOLE_STREAMS_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ffcc088..00c2083 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -69,14 +69,6 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif -#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) -#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE -static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } -static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } -#endif - #endif /* __ROMCC__ */ #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..ebf7a2b 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -31,7 +31,6 @@ int usb_can_rx_byte(int idx); ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) #define USB_PIPE_FOR_CONSOLE 0 -#define USB_PIPE_FOR_GDB 0 #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } @@ -43,13 +42,4 @@ static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} #endif -/* */ -#if 0 && CONFIG_GDB_STUB && \ - ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } -#endif - #endif /* _CONSOLE_USB_H_ */ diff --git a/src/include/debug-com.h b/src/include/debug-com.h new file mode 100644 index 0000000..d716ee9 --- /dev/null +++ b/src/include/debug-com.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DEBUG_COM_H_ +#define _DEBUG_COM_H_ + +#include <stdint.h> + +void debug_hw_init(void); +void debug_tx_byte(unsigned char byte); +void debug_tx_flush(void); +unsigned char debug_rx_byte(void); + +#endif /* _DEBUG_COM_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e2cf9ef..a319b83 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -223,6 +223,11 @@ postcar-y += prog_ops.c postcar-y += rmodule.c postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += debug-com.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += debug-com.c +romstage-$(CONFIG_GDB_STUB) += debug-com.c +ramstage-$(CONFIG_GDB_STUB) += debug-com.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld diff --git a/src/lib/debug-com.c b/src/lib/debug-com.c new file mode 100644 index 0000000..b8cfaa7 --- /dev/null +++ b/src/lib/debug-com.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <stdint.h> +#include <console/uart.h> +#include <console/usb.h> +#include <debug-com.h> + +#define CONFIG_UART_FOR_GDB 0 +#define USB_PIPE_FOR_GDB 0 + +#define CONFIG_UART_FOR_SERIALICE 0 +#define USB_PIPE_FOR_SERIALICE 0 + +/* Configure functions to use GDB arguments */ +#if __CONSOLE_USB_ENABLE__ && CONFIG_GDB_STUB + +static inline void __debug_hw_init(void) { usbdebug_init(); } +static inline void __debug_tx_byte(u8 data) + { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __debug_tx_flush(void) + { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __debug_rx_byte(void) + { return usb_rx_byte(USB_PIPE_FOR_GDB); } + +#elif __CONSOLE_SERIAL_ENABLE__ && CONFIG_GDB_STUB + +static inline void __debug_hw_init(void) + { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __debug_tx_byte(u8 data) + { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __debug_tx_flush(void) + { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __debug_rx_byte(void) + { return uart_rx_byte(CONFIG_UART_FOR_GDB); } + +/* Configure functions to use SerialICE arguments */ +#elif __CONSOLE_USB_ENABLE__ && CONFIG_DEBUG_SERIALICE + +static inline void __debug_hw_init(void) { usbdebug_init(); } +static inline void __debug_tx_byte(u8 data) + { usb_tx_byte(USB_PIPE_FOR_SERIALICE, data); } +static inline void __debug_tx_flush(void) + { usb_tx_flush(USB_PIPE_FOR_SERIALICE); } +static inline u8 __debug_rx_byte(void) + { return usb_rx_byte(USB_PIPE_FOR_SERIALICE); } + +#elif __CONSOLE_SERIAL_ENABLE__ && CONFIG_DEBUG_SERIALICE + +static inline void __debug_hw_init(void) + { uart_init(CONFIG_UART_FOR_SERIALICE); } +static inline void __debug_tx_byte(u8 data) + { uart_tx_byte(CONFIG_UART_FOR_SERIALICE, data); } +static inline void __debug_tx_flush(void) + { uart_tx_flush(CONFIG_UART_FOR_SERIALICE); } +static inline u8 __debug_rx_byte(void) + { return uart_rx_byte(CONFIG_UART_FOR_SERIALICE); } + +#else + +static inline void __debug_hw_init(void) {} +static inline void __debug_tx_byte(u8 data) {} +static inline void __debug_tx_flush(void) {} +static inline u8 __debug_rx_byte(void) { return 0; } + +#endif + + +void debug_hw_init(void) +{ + __debug_hw_init(); +} + +void debug_tx_byte(unsigned char byte) +{ + __debug_tx_byte(byte); +} + +void debug_tx_flush(void) +{ + __debug_tx_flush(); +} + +unsigned char debug_rx_byte(void) +{ + return __debug_rx_byte(); +} +

1 0

Patch set updated for coreboot: lib/selfboot: Replace rdev_mmap_full()
by Antonello Dettori 04 Sep '16

04 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15525 -gerrit commit a127fa7cbcc7c17fd3173277d92e2fbd6a3973a5 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Jul 1 14:28:17 2016 +0200 lib/selfboot: Replace rdev_mmap_full() Avoid loading the entire payload into memory, instead read each segment when it is required. If the segment is uncompressed rdev_readat() it into memory, otherwise rdev_mmap() the segment and uncompress it. The purpose of the change is to improve the performance during the payload load phase by avoiding any unnecessary mmap operation where possible. Change-Id: I27cd4358a1747a65a79995114df23e296d1410fd Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/lib/selfboot.c | 153 ++++++++++++++++++++++++++++++++--------------------- 1 file changed, 94 insertions(+), 59 deletions(-) diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 2fdf8ce..ab79e3d 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -36,9 +36,8 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; - unsigned long s_filesz; + struct region_device src; int compression; }; @@ -58,6 +57,16 @@ static void segment_insert_after(struct segment *seg, struct segment *new) seg->next = new; } +static size_t segment_file_sz(const struct segment *seg) +{ + return region_device_sz(&seg->src); +} + +static size_t segment_file_offset(const struct segment *seg) +{ + return region_device_offset(&seg->src); +} + /* The problem: * Static executables all want to share the same addresses * in memory because only a few addresses are reliably present on @@ -137,7 +146,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) die ("bounce buffer not supported"); start = seg->s_dstaddr; - middle = start + seg->s_filesz; + middle = start + segment_file_sz(seg); end = start + seg->s_memsz; printk(BIOS_SPEW, "segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", @@ -155,12 +164,16 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; - if (seg->s_filesz > len) { - new->s_filesz = len; - seg->s_filesz -= len; + if (segment_file_sz(seg) > len) { + if (rdev_chain(&new->src, &new->src, 0, len) < 0) + return 0; + + if (rdev_chain(&seg->src, &seg->src, len, + segment_file_sz(seg) - len) < 0) + return 0; } else { - seg->s_filesz = 0; + if (rdev_chain(&seg->src, &seg->src, len, 0) < 0) + return 0; } /* Order by stream offset */ @@ -171,7 +184,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) printk(BIOS_SPEW, " early: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, - new->s_dstaddr + new->s_filesz, + new->s_dstaddr + segment_file_sz(new), new->s_dstaddr + new->s_memsz); ret = 1; @@ -188,19 +201,23 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; - if (seg->s_filesz > len) { - seg->s_filesz = len; - new->s_filesz -= len; + if (segment_file_sz(seg) > len) { + if (rdev_chain(&seg->src, &seg->src, 0, len) < 0) + return 0; + + if (rdev_chain(&new->src, &new->src, len, + segment_file_sz(new) - len)) + return 0; } else { - new->s_filesz = 0; + if (rdev_chain(&new->src, &new->src, len, 0) < 0) + return 0; } /* Order by stream offset */ segment_insert_after(seg, new); printk(BIOS_SPEW, " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, - new->s_dstaddr + new->s_filesz, + new->s_dstaddr + segment_file_sz(new), new->s_dstaddr + new->s_memsz); } } @@ -214,7 +231,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) printk(BIOS_SPEW, " bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n", seg->s_dstaddr, - seg->s_dstaddr + seg->s_filesz, + seg->s_dstaddr + segment_file_sz(seg), seg->s_dstaddr + seg->s_memsz); return ret; @@ -234,24 +251,29 @@ static void cbfs_decode_payload_segment(struct cbfs_payload_segment *segment, segment->mem_len = read_be32(&src->mem_len); } -static int build_self_segment_list( - struct segment *head, - struct cbfs_payload *cbfs_payload, uintptr_t *entry) +static int build_self_segment_list(struct segment *head, + struct region_device *cbfs_payload, uintptr_t *entry) { struct segment *new; - struct cbfs_payload_segment *current_segment, *first_segment, segment; + struct cbfs_payload_segment segment; + size_t offset = 0; memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = &cbfs_payload->segments; + while (true) { + ssize_t ret = rdev_readat(cbfs_payload, &segment, offset, + sizeof(struct cbfs_payload_segment)); + + if (ret != sizeof(struct cbfs_payload_segment)) + return 0; - for (current_segment = first_segment;; ++current_segment) { printk(BIOS_DEBUG, + "Loading segment from ROM address 0x%p\n", - current_segment); + &segment); - cbfs_decode_payload_segment(&segment, current_segment); + cbfs_decode_payload_segment(&segment, &segment); switch (segment.type) { case PAYLOAD_SEGMENT_PARAMS: @@ -268,20 +290,22 @@ static int build_self_segment_list( new->s_dstaddr = segment.load_addr; new->s_memsz = segment.mem_len; new->compression = segment.compression; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + segment.offset; - new->s_filesz = segment.len; + if (rdev_chain(&new->src, cbfs_payload, segment.offset, + segment.len) < 0) + return 0; - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx offset 0x%zx filesize 0x%zx\n", + new->s_dstaddr, new->s_memsz, + segment_file_offset(new), segment_file_sz(new)); /* Clean up the values */ - if (new->s_filesz > new->s_memsz) { - new->s_filesz = new->s_memsz; + if (segment_file_sz(new) > new->s_memsz) { + if (rdev_chain(&new->src, &new->src, 0, new->s_memsz) < 0) + return 0; + printk(BIOS_DEBUG, - " cleaned up filesize 0x%lx\n", - new->s_filesz); + " cleaned up filesize 0x%zx\n", + segment_file_sz(new)); } break; @@ -290,13 +314,11 @@ static int build_self_segment_list( (intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); - new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + segment.offset; new->s_dstaddr = segment.load_addr; new->s_memsz = segment.mem_len; new->compression = CBFS_COMPRESS_NONE; + if (rdev_chain(&new->src, cbfs_payload, segment.offset, 0) < 0) + return 0; break; case PAYLOAD_SEGMENT_ENTRY: @@ -323,14 +345,14 @@ static int build_self_segment_list( /* We have found another CODE, DATA or BSS segment */ /* Insert new segment at the end of the list */ segment_insert_before(head, new); + + offset += sizeof(struct cbfs_payload_segment); } return 1; } -static int load_self_segments( - struct segment *head, - struct prog *payload) +static int load_self_segments(struct segment *head) { struct segment *ptr; const unsigned long one_meg = (1UL << 20); @@ -378,10 +400,10 @@ static int load_self_segments( } for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src, *middle, *end; - size_t len, memsz; - printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", - ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); + unsigned char *dest, *src; + + printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016zx\n", + ptr->s_dstaddr, ptr->s_memsz, segment_file_sz(ptr)); /* Modify the segment to load onto the bounce_buffer if necessary. */ @@ -390,21 +412,26 @@ static int load_self_segments( continue; } - printk(BIOS_DEBUG, "Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", - ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); + printk(BIOS_DEBUG, "Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016zx\n", + ptr->s_dstaddr, ptr->s_memsz, segment_file_sz(ptr)); /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); - len = ptr->s_filesz; - memsz = ptr->s_memsz; - end = dest + memsz; + src = NULL; /* Copy data from the initial buffer */ + unsigned char *middle, *end; + size_t len = segment_file_sz(ptr); + size_t memsz = ptr->s_memsz; + end = dest + memsz; switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); timestamp_add_now(TS_START_ULZMA); + src = rdev_mmap_full(&ptr->src); + if (src == NULL) + return 0; + len = ulzman(src, len, dest, memsz); timestamp_add_now(TS_END_ULZMA); if (!len) /* Decompression Error. */ @@ -414,6 +441,10 @@ static int load_self_segments( case CBFS_COMPRESS_LZ4: { printk(BIOS_DEBUG, "using LZ4\n"); timestamp_add_now(TS_START_ULZ4F); + src = rdev_mmap_full(&ptr->src); + if (src == NULL) + return 0; + len = ulz4fn(src, len, dest, memsz); timestamp_add_now(TS_END_ULZ4F); if (!len) /* Decompression Error. */ @@ -422,13 +453,15 @@ static int load_self_segments( } case CBFS_COMPRESS_NONE: { printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + if (rdev_readat(&ptr->src, dest, 0, len) < 0) + return 0; break; } default: printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", ptr->compression); return -1; } + /* Calculate middle after any changes to len. */ middle = dest + len; printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", @@ -471,6 +504,11 @@ static int load_self_segments( */ prog_segment_loaded((uintptr_t)dest, ptr->s_memsz, ptr->next == head ? SEG_FINAL : 0); + + /* munmap the segment that was compressed */ + if (ptr->compression != CBFS_COMPRESS_NONE) + if (rdev_munmap(&ptr->src, src) < 0) + return 0; } return 1; @@ -480,31 +518,28 @@ void *selfload(struct prog *payload) { uintptr_t entry = 0; struct segment head; - void *data; + struct region_device *data; - data = rdev_mmap_full(prog_rdev(payload)); + data = prog_rdev(payload); if (data == NULL) - return NULL; + goto out; /* Preprocess the self segments */ if (!build_self_segment_list(&head, data, &entry)) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head)) goto out; printk(BIOS_SPEW, "Loaded segments\n"); - rdev_munmap(prog_rdev(payload), data); - /* Update the payload's area with the bounce buffer information. */ prog_set_area(payload, (void *)(uintptr_t)bounce_buffer, bounce_size); return (void *)entry; out: - rdev_munmap(prog_rdev(payload), data); return NULL; }

1 0

Patch set updated for coreboot: northbridge/amd/lx: remove unused function declaration
by Antonello Dettori 04 Sep '16

04 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16435 -gerrit commit 1be88156c05c7285e703c8404c29237ec5525fff Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 12:50:16 2016 +0200 northbridge/amd/lx: remove unused function declaration Remove an unusued function declaration that caused problems while compiling the target. Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/amd/lx/northbridge.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index 1e0e650..9a4ff29 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -19,7 +19,6 @@ #include <cpu/amd/lxdef.h> /* northbridge.c */ -unsigned int lx_scan_root_bus(device_t root, unsigned int max); int sizeram(void); /* northbridgeinit.c */

1 0

Patch set updated for coreboot: southbridge/amd/agesa/hudson: transition away from device_t
by Antonello Dettori 04 Sep '16

04 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16401 -gerrit commit 7ac8013697389d2b022a07c9012bb4e19db79179 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Sep 1 16:50:42 2016 +0200 southbridge/amd/agesa/hudson: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/agesa/hudson. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 57119f9..1cdaa05 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -28,7 +28,7 @@ void hudson_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); @@ -73,7 +73,7 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ outb(0xEC, 0xCD6); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 92058c6..d870845 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -70,7 +70,7 @@ u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

1 0

Patch set updated for coreboot: cpu/amd/family_10h-family_15h: transition away from device_t
by Antonello Dettori 04 Sep '16

04 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16436 -gerrit commit 1fece61c375f183bc0f886a88aee72f4dc96753b Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:43:20 2016 +0200 cpu/amd/family_10h-family_15h: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/family_10h-family_15h. Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 39 +++++++++++++++++---------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2eb55e8..d59f23a 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -122,7 +122,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i; nodes = get_nodes(); @@ -139,7 +139,8 @@ static void enable_fid_change(u8 fid) } } -static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { +static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) +{ // BKDG 2.4.2.8 // Fam10h revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -164,7 +165,8 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { } } -static void enableNbPState1( device_t dev ) { +static void enableNbPState1(pci_devfn_t dev) +{ uint64_t cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -184,7 +186,8 @@ static void enableNbPState1( device_t dev ) { } } -static u8 setPStateMaxVal(device_t dev) { +static u8 setPStateMaxVal(pci_devfn_t dev) +{ u8 i, maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -204,7 +207,8 @@ static u8 setPStateMaxVal(device_t dev) { return maxpstate; } -static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly(pci_devfn_t dev) +{ // BKDG 2.4.2.7 uint64_t cpuRev = mctGetLogicalCPUID(0xFF); @@ -248,7 +252,8 @@ static int vidTo100uV(u8 vid) return voltage; } -static void setVSRamp(device_t dev) { +static void setVSRamp(pci_devfn_t dev) +{ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -263,7 +268,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); } -static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -447,7 +452,8 @@ static u32 power_up_down(int node, u8 procPkg) { } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { - device_t dev = NODE_PCI(node, 3); + + pci_devfn_t dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -471,7 +477,9 @@ static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t pr } -static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) { +static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, + uint8_t procPkg) +{ /* check PVI/SVI */ uint32_t dword = pci_read_config32(dev, 0xa0); @@ -504,7 +512,8 @@ static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t pr pci_write_config32(dev, 0xa0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { +static void config_nb_syn_ptr_adj(pci_devfn_t dev, uint64_t cpuRev) +{ /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -526,7 +535,9 @@ static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) { +static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, + uint8_t procPkg) +{ if (is_fam15h()) { /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ pci_write_config32(dev, 0x80, 0xe20be281); @@ -594,7 +605,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i; /* This needs to be run before any Pstate changes are requested */ @@ -809,7 +820,7 @@ static u32 needs_NB_COF_VID_update(void) static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + pci_devfn_t dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -973,7 +984,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + pci_devfn_t dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 4405e3c..3c13e36 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -541,7 +541,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect;

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coreboot-gerrit September 2016