coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: intel/minnowmax: Enable all PCIe ports
by gerrit＠coreboot.org 04 Sep '16

04 Sep '16

the following patch was just integrated into master: commit 4551bf6dbfa28d63d657542be372bf5fb15ee5f9 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Sep 2 16:10:58 2016 -0600 intel/minnowmax: Enable all PCIe ports A recently announced Turbot system populates two Ethernet controllers. Enable the remaining disabled PCIe port. Also add a clarifying comment regarding the port associated with Function 0. Coreboot must not be allowed to disable the function which breaks PCI compatibility. Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/16429 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16429 for details. -gerrit

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Patch merged into coreboot/master: intel/minnowmax: Program GPIO for power LED
by gerrit＠coreboot.org 04 Sep '16

04 Sep '16

the following patch was just integrated into master: commit 297c5595629ddfebc15efce92b8a3b0201a1c839 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Sep 2 15:50:48 2016 -0600 intel/minnowmax: Program GPIO for power LED MinnowBoard Turbot systems have a GPIO-controlled LED that is generally used to indicate the CPU is running. Commit 2ae9cce8 changed the parameter for GPIO_NC, exposing an issue with the assumed behavior of the signal. Use a pull-down to turn on the LED. Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/16428 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16428 for details. -gerrit

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Patch set updated for coreboot: intel/gma: Fix obvious typo GMBUS0 -> GMBUS1 in edid.c
by Swift Geek 04 Sep '16

04 Sep '16

Swift Geek (swiftgeek(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16341 -gerrit commit ddf27dd5c45780ea29e2b24d2401e91f533ad610 Author: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Date: Sun Aug 28 04:28:53 2016 +0200 intel/gma: Fix obvious typo GMBUS0 -> GMBUS1 in edid.c This typo existed in code before rewriting for using defines and it's clearly visible after rewrite. Previously it was writing to reserved area of GMBUS0 register, while values are matching those of GMBUS1. Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e Signed-off-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 3902094..316e869 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -56,7 +56,7 @@ static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); write32(GMBUS2_ADDR, GMBUS_INUSE); } @@ -101,7 +101,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); wait_rdy(mmio); - write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); write32(GMBUS2_ADDR, GMBUS_INUSE); printk (BIOS_SPEW, "EDID:\n");

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Patch set updated for coreboot: intel/gma: Fix obvious typo GMBUS0 -> GMBUS1 in edid.c
by Swift Geek 04 Sep '16

04 Sep '16

Swift Geek (swiftgeek(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16341 -gerrit commit 5b6d35ca03857585154ec5f25a13246338276bc5 Author: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Date: Sun Aug 28 04:28:53 2016 +0200 intel/gma: Fix obvious typo GMBUS0 -> GMBUS1 in edid.c This typo existed in code before rewriting for using defines and it's clearly visible after rewrite. Previously it was writing to reserved area of GMBUS0 register, while values are matching those of GMBUS1. Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e Signed-off-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 3902094..316e869 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -56,7 +56,7 @@ static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); write32(GMBUS2_ADDR, GMBUS_INUSE); } @@ -101,7 +101,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); wait_rdy(mmio); - write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); write32(GMBUS2_ADDR, GMBUS_INUSE); printk (BIOS_SPEW, "EDID:\n");

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Patch set updated for coreboot: intel/gma: Use defines for registers and values in edid.c
by Swift Geek 04 Sep '16

04 Sep '16

Swift Geek (swiftgeek(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16339 -gerrit commit b923b9d051658f113f0f2ec031a08d92d7e49e67 Author: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Date: Sat Aug 27 13:24:53 2016 +0200 intel/gma: Use defines for registers and values in edid.c Replaces magic values with defines without changing any value. Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c Signed-off-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> --- src/drivers/intel/gma/edid.c | 54 ++++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 9bde9b5..3902094 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2016 Sebastian Grzywna <swiftgeek(a)gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,13 +21,19 @@ #include "i915_reg.h" #include "edid.h" +#define GMBUS0_ADDR (mmio + 4 * 0) +#define GMBUS1_ADDR (mmio + 4 * 1) +#define GMBUS2_ADDR (mmio + 4 * 2) +#define GMBUS3_ADDR (mmio + 4 * 3) +#define GMBUS5_ADDR (mmio + 4 * 8) +#define AT24_ADDR 0x50 /* EDID EEPROM */ static void wait_rdy(u8 *mmio) { unsigned try = 100; while (try--) { - if (read32(mmio + 8) & (1 << 11)) + if (read32(GMBUS2_ADDR) & GMBUS_HW_RDY) return; udelay(10); } @@ -35,19 +42,22 @@ static void wait_rdy(u8 *mmio) static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) { wait_rdy(mmio); - write32(mmio + 4 * 0, bus); + write32(GMBUS0_ADDR, bus); wait_rdy(mmio); - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x4e0400a1); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX + | GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT ) + | GMBUS_SLAVE_READ | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x80000000); - write32(mmio + 4 * 1, 0x00000000); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT); + write32(GMBUS1_ADDR, 0); wait_rdy(mmio); - write32(mmio + 4 * 1, 0x480000a0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE + | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(mmio + 4 * 0, 0x48000000); - write32(mmio + 4 * 2, 0x00008000); + write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); + write32(GMBUS2_ADDR, GMBUS_INUSE); } void intel_gmbus_stop(u8 *mmio) @@ -65,30 +75,34 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) wait_rdy(mmio); /* 100 KHz, hold 0ns, */ - write32(mmio + 4 * 0, bus); + write32(GMBUS0_ADDR, bus); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x46000000 | (slave << 1)); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX + | (slave << 1) ); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x4a000001 | (slave << 1) - | (edid_size << 16)); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT + | GMBUS_CYCLE_STOP + | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); for (i = 0; i < edid_size / 4; i++) { u32 reg32; wait_rdy(mmio); - reg32 = read32(mmio + 4 * 3); + reg32 = read32(GMBUS3_ADDR); edid[4 * i] = reg32 & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff; } wait_rdy(mmio); - write32(mmio + 4 * 1, 0x4a800000 | (slave << 1)); + write32(GMBUS1_ADDR, GMBUS_SW_RDY + | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP + | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); wait_rdy(mmio); - write32(mmio + 4 * 0, 0x48000000); - write32(mmio + 4 * 2, 0x00008000); + write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); + write32(GMBUS2_ADDR, GMBUS_INUSE); printk (BIOS_SPEW, "EDID:\n"); for (i = 0; i < 128; i++) {

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Patch set updated for coreboot: Use defines for registers and values in edid.c
by Swift Geek 04 Sep '16

04 Sep '16

Swift Geek (swiftgeek(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16339 -gerrit commit 6cbb94ef82aa356fe7a9112d1563c71ecedc762f Author: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Date: Sat Aug 27 13:24:53 2016 +0200 Use defines for registers and values in edid.c Replaces magic values with defines without changing any value. Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c Signed-off-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> --- src/drivers/intel/gma/edid.c | 54 ++++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 9bde9b5..3902094 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2016 Sebastian Grzywna <swiftgeek(a)gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,13 +21,19 @@ #include "i915_reg.h" #include "edid.h" +#define GMBUS0_ADDR (mmio + 4 * 0) +#define GMBUS1_ADDR (mmio + 4 * 1) +#define GMBUS2_ADDR (mmio + 4 * 2) +#define GMBUS3_ADDR (mmio + 4 * 3) +#define GMBUS5_ADDR (mmio + 4 * 8) +#define AT24_ADDR 0x50 /* EDID EEPROM */ static void wait_rdy(u8 *mmio) { unsigned try = 100; while (try--) { - if (read32(mmio + 8) & (1 << 11)) + if (read32(GMBUS2_ADDR) & GMBUS_HW_RDY) return; udelay(10); } @@ -35,19 +42,22 @@ static void wait_rdy(u8 *mmio) static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) { wait_rdy(mmio); - write32(mmio + 4 * 0, bus); + write32(GMBUS0_ADDR, bus); wait_rdy(mmio); - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x4e0400a1); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX + | GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT ) + | GMBUS_SLAVE_READ | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x80000000); - write32(mmio + 4 * 1, 0x00000000); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT); + write32(GMBUS1_ADDR, 0); wait_rdy(mmio); - write32(mmio + 4 * 1, 0x480000a0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE + | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(mmio + 4 * 0, 0x48000000); - write32(mmio + 4 * 2, 0x00008000); + write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); + write32(GMBUS2_ADDR, GMBUS_INUSE); } void intel_gmbus_stop(u8 *mmio) @@ -65,30 +75,34 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) wait_rdy(mmio); /* 100 KHz, hold 0ns, */ - write32(mmio + 4 * 0, bus); + write32(GMBUS0_ADDR, bus); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x46000000 | (slave << 1)); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX + | (slave << 1) ); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + 4 * 8, 0); - write32(mmio + 4 * 1, 0x4a000001 | (slave << 1) - | (edid_size << 16)); + write32(GMBUS5_ADDR, 0); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT + | GMBUS_CYCLE_STOP + | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); for (i = 0; i < edid_size / 4; i++) { u32 reg32; wait_rdy(mmio); - reg32 = read32(mmio + 4 * 3); + reg32 = read32(GMBUS3_ADDR); edid[4 * i] = reg32 & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff; } wait_rdy(mmio); - write32(mmio + 4 * 1, 0x4a800000 | (slave << 1)); + write32(GMBUS1_ADDR, GMBUS_SW_RDY + | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP + | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); wait_rdy(mmio); - write32(mmio + 4 * 0, 0x48000000); - write32(mmio + 4 * 2, 0x00008000); + write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); + write32(GMBUS2_ADDR, GMBUS_INUSE); printk (BIOS_SPEW, "EDID:\n"); for (i = 0; i < 128; i++) {

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Patch set updated for coreboot: Fix obvious typo GMBUS0 -> GMBUS1 in edid.c
by Swift Geek 04 Sep '16

04 Sep '16

Swift Geek (swiftgeek(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16341 -gerrit commit a4b4cb4e6a561f97fdb9231a21be443d4cfec580 Author: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Date: Sun Aug 28 04:28:53 2016 +0200 Fix obvious typo GMBUS0 -> GMBUS1 in edid.c This typo existed in code before rewriting for using defines and it's clearly visible after rewrite. Previously it was writing to reserved area of GMBUS0 register, while values are matching those of GMBUS1. Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e Signed-off-by: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 3902094..316e869 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -56,7 +56,7 @@ static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE | (AT24_ADDR << 1) ); wait_rdy(mmio); - write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); write32(GMBUS2_ADDR, GMBUS_INUSE); } @@ -101,7 +101,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); wait_rdy(mmio); - write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); write32(GMBUS2_ADDR, GMBUS_INUSE); printk (BIOS_SPEW, "EDID:\n");

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New patch to review for coreboot: mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPI
by Damien Zammit 04 Sep '16

04 Sep '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16497 -gerrit commit 7104a7661bb5ff7e7a84ab631dca8019fc3529f2 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Sep 5 02:39:20 2016 +1000 mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPI With this patch and the previous ones in this set, PCI express graphics is now working. 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218 [GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller]) Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl index 87719f7..eb231cb 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl @@ -20,6 +20,11 @@ Method(_PRT) { If (PICM) { Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, 0, 16 }, + Package() { 0x0001ffff, 1, 0, 17 }, + Package() { 0x0001ffff, 2, 0, 18 }, + Package() { 0x0001ffff, 3, 0, 19 }, /* Internal GFX */ Package() { 0x0002ffff, 0, 0, 16 }, Package() { 0x0002ffff, 1, 0, 17 }, @@ -46,6 +51,11 @@ Method(_PRT) }) } Else { Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, /* Internal GFX */ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },

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New patch to review for coreboot: mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
by Damien Zammit 04 Sep '16

04 Sep '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16496 -gerrit commit b859ab90bb40674a2f9f7c83c319939c3e9de25c Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Sep 5 02:38:01 2016 +1000 mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index c433387..bd80742 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -28,7 +28,6 @@ chip northbridge/intel/x4x # Northbridge device pci 0.0 on # Host Bridge subsystemid 0x1458 0x5000 end - device pci 1.0 off end # PCI Bridge to Management Engine device pci 2.0 on # Integrated graphics controller subsystemid 0x1458 0xd000 end

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New patch to review for coreboot: nb/intel/x4x: Turn on PEG graphics in device enable
by Damien Zammit 04 Sep '16

04 Sep '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16495 -gerrit commit 6b1f88781465da0640f68d0b179457d1d8f00ead Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Sep 5 02:36:02 2016 +1000 nb/intel/x4x: Turn on PEG graphics in device enable Change-Id: I389c4630362af1c1bf6d281c9d2b7fc81bea2d5d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/x4x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e02ee02..2434067 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -36,7 +36,7 @@ #define D3F2EN (1 << 8) #define D3F3EN (1 << 9) #define PEG1EN (1 << 13) -#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) #define D0F0_PCIEXBAR_LO 0x60 #define D0F0_PCIEXBAR_HI 0x64 #define D0F0_DMIBAR_LO 0x68

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coreboot-gerrit September 2016