coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

1 participants
1340 discussions

New patch to review for coreboot: lenovo: add ps2 spinup timeout to all H8S based boards
by Alexander Couzens 06 Sep '16

06 Sep '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16505 -gerrit commit 536f6ceb5e3d1a77b25b7b3daa2a1e41204c6ef8 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Sep 6 16:06:32 2016 +0200 lenovo: add ps2 spinup timeout to all H8S based boards The h8s needs around 3s to respond to ps2 commands Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/t400/Kconfig | 5 +++++ src/mainboard/lenovo/t420/Kconfig | 5 +++++ src/mainboard/lenovo/t420s/Kconfig | 5 +++++ src/mainboard/lenovo/t520/Kconfig | 5 +++++ src/mainboard/lenovo/x200/Kconfig | 5 +++++ src/mainboard/lenovo/x201/Kconfig | 5 +++++ src/mainboard/lenovo/x220/Kconfig | 5 +++++ 7 files changed, 35 insertions(+) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..194e38c 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,9 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif # BOARD_LENOVO_T400 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 04233e7..e2272b1 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -76,4 +76,9 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif # BOARD_LENOVO_T420 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index feacb51..d278ccb 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -75,4 +75,9 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index ee5dd81..4ce27f1 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -75,4 +75,9 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif # BOARD_LENOVO_T520 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7bae12d..f069fd5 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -48,4 +48,9 @@ config CBFS_SIZE hex default 0x200000 +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif # BOARD_LENOVO_X200 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 7f96cbe..7e46c33 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -49,4 +49,9 @@ config CPU_ADDR_BITS int default 36 +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 0ef6689..5367fd1 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -73,4 +73,9 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21db +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I

1 0

Patch merged into coreboot/master: vendorcode/intel/Makefile.inc: Remove extraneous underscore
by gerrit＠coreboot.org 06 Sep '16

06 Sep '16

the following patch was just integrated into master: commit ac39da44d1f8b7af9d78347b541aaf45fc0c5fa5 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 2 11:09:05 2016 -0600 vendorcode/intel/Makefile.inc: Remove extraneous underscore Commit e96543e1 (vendorcode/intel: Add UDK 2015 Bindings) had an extra underscore at the end of one of the make lines that we missed in the review. Remove it. Fixes this build warning: .../Makefile.inc:34: Extraneous text after `ifeq' directive Change-Id: I0bc76d827207b4f641ac5ff08f540a114347533b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16411 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/16411 for details. -gerrit

1 0

Patch set updated for coreboot: src/ec: Improve code formatting
by HAOUAS Elyes 06 Sep '16

06 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16503 -gerrit commit 4c876366c87879271402aa9cfe213a192468fd17 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Sep 5 19:55:34 2016 +0200 src/ec: Improve code formatting Change-Id: I93b71ca577c973046d1651d92665168b329eda1b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/ec/compal/ene932/acpi/ec.asl | 8 +- src/ec/compal/ene932/ec.c | 2 +- src/ec/google/chromeec/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/ec.asl | 258 +++++++++++++++++----------------- src/ec/lenovo/h8/acpi/lid.asl | 2 +- src/ec/lenovo/h8/acpi/sleepbutton.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 20 +-- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/quanta/it8518/ec.c | 6 +- 9 files changed, 151 insertions(+), 151 deletions(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 93ddcbe..7caf8d4 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -32,7 +32,7 @@ Device (EC0) Offset(0x00), , 1, // Reserved ; 00h.0 LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 - , 6, // Reserved ; 00h.2 ~ 00h.6 + , 6, // Reserved ; 00h.2 ~ 00h.6 HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function HTBT, 8, // HOTKEY_BUTTON_TYPE ; 02h For ABO Hot Key Function LMEN, 1, // Launch Manager enable .(1=Enable ) ; 03h.0, Lauanch manage @@ -212,9 +212,9 @@ Device (EC0) // 101 : CPT , 1, // Reserved ; C0h.7 BST0, 8, // Battery Status ; C1h - // Bit0 : Discharging - // Bit1 : Charging - // Bit2 : Discharg and Critical Low + // Bit0 : Discharging + // Bit1 : Charging + // Bit2 : Discharg and Critical Low // Bit3-7 : Reserved BRC0, 16, // Batt Remaining Capacity ; C2h, C3h BSN0, 16, // Batt Serial Number ; C4h, C5h diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 4b69e75..1587db9 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -144,7 +144,7 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(struct device *dev) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 84d5e32..db3fff7 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -448,7 +448,7 @@ Device (EC0) #endif #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT - #include "keyboard_backlight.asl" + #include "keyboard_backlight.asl" #endif #ifdef EC_ENABLE_PD_MCU_DEVICE diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 085492d..4f8d203 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -27,13 +27,13 @@ Device(EC) Field (ERAM, ByteAcc, NoLock, Preserve) { Offset (0x02), - DKR1, 1, /* Dock register 1 */ + DKR1, 1, /* Dock register 1 */ Offset (0x05), HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ Offset (0x1a), - DKR2, 1, /* Dock register 2 */ + DKR2, 1, /* Dock register 2 */ Offset (0x2a), EVNT, 8, /* write will trigger EC event */ Offset (0x3a), @@ -56,7 +56,7 @@ Device(EC) PAGE, 8, /* Information Page Selector */ Offset (0xfe), , 4, - DKR3, 1 /* Dock register 3 */ + DKR3, 1 /* Dock register 3 */ } Method (_CRS, 0) @@ -140,186 +140,186 @@ Device(EC) Store(0x50, EVNT) } - Method(_Q2A, 0, NotSerialized) - { - Notify(^LID, 0x80) - } + Method(_Q2A, 0, NotSerialized) + { + Notify(^LID, 0x80) + } - Method(_Q2B, 0, NotSerialized) - { - Notify(^LID, 0x80) - } + Method(_Q2B, 0, NotSerialized) + { + Notify(^LID, 0x80) + } - /* IBM proprietary buttons. */ + /* IBM proprietary buttons. */ - Method (_Q10, 0, NotSerialized) - { + Method (_Q10, 0, NotSerialized) + { ^HKEY.RHK (0x01) - } + } - Method (_Q11, 0, NotSerialized) - { + Method (_Q11, 0, NotSerialized) + { ^HKEY.RHK (0x02) - } + } - Method (_Q12, 0, NotSerialized) - { + Method (_Q12, 0, NotSerialized) + { ^HKEY.RHK (0x03) - } + } - Method (_Q64, 0, NotSerialized) - { + Method (_Q64, 0, NotSerialized) + { ^HKEY.RHK (0x05) - } + } - Method (_Q65, 0, NotSerialized) - { + Method (_Q65, 0, NotSerialized) + { ^HKEY.RHK (0x06) - } + } - Method (_Q17, 0, NotSerialized) - { + Method (_Q17, 0, NotSerialized) + { ^HKEY.RHK (0x08) - } + } - Method (_Q66, 0, NotSerialized) - { + Method (_Q66, 0, NotSerialized) + { ^HKEY.RHK (0x0A) - } + } - Method (_Q6A, 0, NotSerialized) - { + Method (_Q6A, 0, NotSerialized) + { ^HKEY.RHK (0x1B) - } + } - Method (_Q1A, 0, NotSerialized) - { + Method (_Q1A, 0, NotSerialized) + { ^HKEY.RHK (0x0B) - } + } - Method (_Q1B, 0, NotSerialized) - { + Method (_Q1B, 0, NotSerialized) + { ^HKEY.RHK (0x0C) - } + } - Method (_Q62, 0, NotSerialized) - { + Method (_Q62, 0, NotSerialized) + { ^HKEY.RHK (0x0D) - } + } - Method (_Q60, 0, NotSerialized) - { + Method (_Q60, 0, NotSerialized) + { ^HKEY.RHK (0x0E) - } + } - Method (_Q61, 0, NotSerialized) - { + Method (_Q61, 0, NotSerialized) + { ^HKEY.RHK (0x0F) - } + } - Method (_Q1F, 0, NotSerialized) - { + Method (_Q1F, 0, NotSerialized) + { ^HKEY.RHK (0x12) - } + } - Method (_Q67, 0, NotSerialized) - { + Method (_Q67, 0, NotSerialized) + { ^HKEY.RHK (0x13) - } + } - Method (_Q63, 0, NotSerialized) - { + Method (_Q63, 0, NotSerialized) + { ^HKEY.RHK (0x14) - } + } - Method (_Q19, 0, NotSerialized) - { + Method (_Q19, 0, NotSerialized) + { ^HKEY.RHK (0x18) - } + } - Method (_Q1C, 0, NotSerialized) - { + Method (_Q1C, 0, NotSerialized) + { ^HKEY.RHK (0x19) - } + } - Method (_Q1D, 0, NotSerialized) - { + Method (_Q1D, 0, NotSerialized) + { ^HKEY.RHK (0x1A) - } + } - Method (_Q5C, 0, NotSerialized) - { + Method (_Q5C, 0, NotSerialized) + { ^HKEY.RTAB (0xB) - } + } - Method (_Q5D, 0, NotSerialized) - { + Method (_Q5D, 0, NotSerialized) + { ^HKEY.RTAB (0xC) - } + } - Method (_Q5E, 0, NotSerialized) - { + Method (_Q5E, 0, NotSerialized) + { ^HKEY.RTAB (0x9) - } + } - Method (_Q5F, 0, NotSerialized) - { + Method (_Q5F, 0, NotSerialized) + { ^HKEY.RTAB (0xA) - } - - Device (HKEY) - { - Name (_HID, EisaId ("IBM0068")) - Name (BTN, 0) - Name (BTAB, 0) - /* MASK */ - Name (DHKN, 0x080C) - /* Effective Mask */ - Name (EMSK, 0) - /* Effective Mask for tablet */ - Name (ETAB, 0) - /* Device enabled. */ - Name (EN, 0) - Method (_STA, 0, NotSerialized) - { + } + + Device (HKEY) + { + Name (_HID, EisaId ("IBM0068")) + Name (BTN, 0) + Name (BTAB, 0) + /* MASK */ + Name (DHKN, 0x080C) + /* Effective Mask */ + Name (EMSK, 0) + /* Effective Mask for tablet */ + Name (ETAB, 0) + /* Device enabled. */ + Name (EN, 0) + Method (_STA, 0, NotSerialized) + { Return (0x0F) - } - /* Retrieve event. */ - Method (MHKP, 0, NotSerialized) - { + } + /* Retrieve event. */ + Method (MHKP, 0, NotSerialized) + { Store (BTN, Local0) If (LNotEqual (Local0, Zero)) { - Store (Zero, BTN) - Add (Local0, 0x1000, Local0) - Return (Local0) + Store (Zero, BTN) + Add (Local0, 0x1000, Local0) + Return (Local0) } Store (BTAB, Local0) If (LNotEqual (Local0, Zero)) { - Store (Zero, BTAB) - Add (Local0, 0x5000, Local0) - Return (Local0) + Store (Zero, BTAB) + Add (Local0, 0x5000, Local0) + Return (Local0) } Return (Zero) - } - /* Report event */ - Method (RHK, 1, NotSerialized) { + } + /* Report event */ + Method (RHK, 1, NotSerialized) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (And (EMSK, Local0)) { Store (Arg0, BTN) Notify (HKEY, 0x80) } - } - /* Report tablet */ - Method (RTAB, 1, NotSerialized) { + } + /* Report tablet */ + Method (RTAB, 1, NotSerialized) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (And (ETAB, Local0)) { Store (Arg0, BTAB) Notify (HKEY, 0x80) } - } - /* Enable/disable all events. */ - Method (MHKC, 1, NotSerialized) { + } + /* Enable/disable all events. */ + Method (MHKC, 1, NotSerialized) { If (Arg0) { Store (DHKN, EMSK) Store (Ones, ETAB) @@ -330,9 +330,9 @@ Device(EC) Store (Zero, ETAB) } Store (Arg0, EN) - } - /* Enable/disable event. */ - Method (MHKM, 2, NotSerialized) { + } + /* Enable/disable event. */ + Method (MHKM, 2, NotSerialized) { If (LLessEqual (Arg0, 0x20)) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (Arg1) @@ -348,18 +348,18 @@ Device(EC) Store (DHKN, EMSK) } } - } - /* Mask hotkey all. */ - Method (MHKA, 0, NotSerialized) - { + } + /* Mask hotkey all. */ + Method (MHKA, 0, NotSerialized) + { Return (0x07FFFFFF) - } - /* Version */ - Method (MHKV, 0, NotSerialized) - { + } + /* Version */ + Method (MHKV, 0, NotSerialized) + { Return (0x0100) - } - } + } + } #include "ac.asl" #include "battery.asl" diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index 10c5a98..a8e17cb 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -16,7 +16,7 @@ Field(ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x32), + Offset (0x32), , 2, WKLD, 1, Offset (0x46), diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl index 0517992..2f36c4b 100644 --- a/src/ec/lenovo/h8/acpi/sleepbutton.asl +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -25,7 +25,7 @@ Field(ERAM, ByteAcc, NoLock, Preserve) Device(SLPB) { - Name (_HID, EisaId ("PNP0C0E")) + Name (_HID, EisaId ("PNP0C0E")) Method(_PRW, 0, NotSerialized) { Return (Package() { 0x18, 0x03 }) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 3a3487d..2e95b69 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -23,11 +23,11 @@ Scope(\_TZ) Multiply(Arg0, 10, Local0) Add (Local0, 2732, Local0) if (LLessEqual(Local0, 2732)) { - Return (3000) + Return (3000) } if (LGreater(Local0, 4012)) { - Return (3000) + Return (3000) } Return (Local0) } @@ -39,10 +39,10 @@ Scope(\_TZ) } Method(_TMP) { #if defined (EC_LENOVO_H8_ME_WORKAROUND) - /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { - Return (C2K(40)) - } + /* Avoid tripping alarm if ME isn't booted at all yet */ + If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + Return (C2K(40)) + } Store (1, MEB1) #endif Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) @@ -61,10 +61,10 @@ Scope(\_TZ) Method(_TMP) { #if defined (EC_LENOVO_H8_ME_WORKAROUND) - /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) { - Return (C2K(40)) - } + /* Avoid tripping alarm if ME isn't booted at all yet */ + If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) { + Return (C2K(40)) + } Store (1, MEB2) #endif Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 5e4aa47..83768b1 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -154,7 +154,7 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(struct device *dev) diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index af0849c..643c934 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -131,10 +131,10 @@ u8 ec_it8518_get_event(void) { u8 cmd = 0; u8 status = inb(EC_SC); - if (status & SCI_EVT) { + if (status & SCI_EVT) { ec_write_cmd(QR_EC); cmd = ec_read_ob(); - } else if ( status & SMI_EVT) { + } else if (status & SMI_EVT) { ec_kbc_write_cmd(EC_KBD_SMI_EVENT); cmd = ec_kbc_read_ob(); } @@ -167,7 +167,7 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(struct device *dev)

1 0

Patch set updated for coreboot: i945/gma.c: use linux code to calculate divisors
by Arthur Heymans 06 Sep '16

06 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16504 -gerrit commit 95d07aa7a92cb3ac9bbc63a675a57927ffae8a8e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 22:35:32 2016 +0200 i945/gma.c: use linux code to calculate divisors The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which is defined by the resolution and refresh rate). This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays, like many displays found on the Lenovo T60 might work now. Some examples of T60 displays that were known to not work (in payload): Samsung LTN141XA-L01 (14.1" 1024x768) LG-Philips LP150X09 (15.1" 1024x768) IDtech N150U3-L01 (15.1" 1600x1200) IDtech IAQX10N (15.1" 2048x1536) Samsung LTN154X3-L0A (15.4" 1280x800) LG-Philips LP150E06-A5K4 (15.1" 1400x1050) Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 83 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 02caa0a..3f57e55 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -26,6 +26,7 @@ #include <string.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <commonlib/helpers.h> #include "i945.h" #include "chip.h" @@ -43,7 +44,7 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 -#define BASE_FREQUENCY 120000 +#define BASE_FREQUENCY 100000 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT @@ -85,10 +86,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u8 edid_data[128]; unsigned long temp; int hpolarity, vpolarity; - u32 candp1, candn; - u32 best_delta = 0xffffffff; + u32 err_most = 0xffffffff; u32 target_frequency; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -158,43 +159,39 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom - + BASE_FREQUENCY / 2) / BASE_FREQUENCY; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (BASE_FREQUENCY * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + /* p2 divisor must 7 for dual channel LVDS */ + /* and 14 for single channel LVDS */ + pixel_p2 = mode->lvds_dual_channel ? 7 : 14; + target_frequency = mode->pixel_clock; + + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } } } } - if (best_delta == 0xffffffff) { + if (err_most == 0xffffffff) { printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); return -1; } @@ -216,8 +213,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); @@ -242,8 +239,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + FP0(1), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS @@ -252,8 +249,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | @@ -261,8 +257,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16)

1 0

Patch set updated for coreboot: fsp_broadwell_de: Adjust printed address in SPI debug messages
by Werner Zeh 06 Sep '16

06 Sep '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16500 -gerrit commit 6b2e1eb2d1bdcb934ae00fafcfed709360d97beb Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Sep 5 08:14:23 2016 +0200 fsp_broadwell_de: Adjust printed address in SPI debug messages For an unknown reason the printed address in the SPI debug messages is modified before it is printed by subtracting the constant 0xf020 from the passed in address. What I suppose this debug code should do is to print the used register address within the SPI controller while any parts of this address that belongs to the SPI base address should be omitted. To fix that remove the subtraction of 0xf020 and adjust the address mask to 0x3ff so that only the offset to the registers inside the SPI controller will be visible in the debug messages. In addition switch to uint8_t and friends over u8 to sync up with used types in this file. Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/spi.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 57f7951..116001f 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -159,60 +159,62 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -static u8 readb_(const void *addr) +#define SPI_OFFSET_MASK 0x3ff + +static uint8_t readb_(const void *addr) { - u8 v = read8(addr); + uint8_t v = read8(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((uint32_t) addr) & SPI_OFFSET_MASK); } return v; } -static u16 readw_(const void *addr) +static uint16_t readw_(const void *addr) { - u16 v = read16(addr); + uint16_t v = read16(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((uint32_t) addr) & SPI_OFFSET_MASK); } return v; } -static u32 readl_(const void *addr) +static uint32_t readl_(const void *addr) { - u32 v = read32(addr); + uint32_t v = read32(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((uint32_t) addr) & SPI_OFFSET_MASK); } return v; } -static void writeb_(u8 b, void *addr) +static void writeb_(uint8_t b, void *addr) { write8(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((uint32_t) addr) & SPI_OFFSET_MASK); } } -static void writew_(u16 b, void *addr) +static void writew_(uint16_t b, void *addr) { write16(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((uint32_t) addr) & SPI_OFFSET_MASK); } } -static void writel_(u32 b, void *addr) +static void writel_(uint32_t b, void *addr) { write32(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((uint32_t) addr) & SPI_OFFSET_MASK); } } @@ -457,10 +459,10 @@ static int spi_setup_offset(spi_transaction *trans) * * Return the last read status value on success or -1 on failure. */ -static int ich_status_poll(u16 bitmask, int wait_til_set) +static int ich_status_poll(uint16_t bitmask, int wait_til_set) { int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; + uint16_t status = 0; while (timeout--) { status = readw_(cntlr.status);

1 0

Patch set updated for coreboot: fsp_baytrail: Refactor code for SPI debug messages
by Werner Zeh 06 Sep '16

06 Sep '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16499 -gerrit commit 6738122862a4065f8845ea1507cb46aaad139943 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Sep 5 07:40:29 2016 +0200 fsp_baytrail: Refactor code for SPI debug messages Use the config switch CONFIG_DEBUG_SPI_FLASH on compiler level rather then on preprocessor level to ensure that the code is compiled even if the switch is not selected. In addition the following two changes are introduced: 1. Prepend the debug messages with 'SPI:' to make the output more meaningful. 2. Change the address mask from 0xffff to 0x3ff and remove the subtraction of the constant value 0xf020 in order to print only the register offset within the SPI controller and avoid the visibility of any fragments from SPI base address. 3. Switch to uint8_t and friends instead of u8 to sync up with other code in the same file. Change-Id: Iaf46f29a775039007a402fe862839df06a4cbfaa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/spi.c | 72 +++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 35 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 1b85fc5..374e7f6 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Siemens AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -158,64 +159,65 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#define SPI_OFFSET_MASK 0x3ff -static u8 readb_(const void *addr) +static uint8_t readb_(const void *addr) { - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint8_t v = read8(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, (((uint32_t) addr) & SPI_OFFSET_MASK)); + } return v; } -static u16 readw_(const void *addr) +static uint16_t readw_(const void *addr) { - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint16_t v = read16(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, (((uint32_t) addr) & SPI_OFFSET_MASK)); + } return v; } -static u32 readl_(const void *addr) +static uint32_t readl_(const void *addr) { - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint32_t v = read32(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, (((uint32_t) addr) & SPI_OFFSET_MASK)); + } return v; } -static void writeb_(u8 b, void *addr) +static void writeb_(uint8_t b, void *addr) { write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, (((uint32_t) addr) & SPI_OFFSET_MASK)); + } } -static void writew_(u16 b, void *addr) +static void writew_(uint16_t b, void *addr) { write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, (((uint32_t) addr) & SPI_OFFSET_MASK)); + } } -static void writel_(u32 b, void *addr) +static void writel_(uint32_t b, void *addr) { write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, (((uint32_t) addr) & SPI_OFFSET_MASK)); + } } -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - static void write_reg(const void *value, void *dest, uint32_t size) { const uint8_t *bvalue = value; @@ -441,10 +443,10 @@ static int spi_setup_offset(spi_transaction *trans) * * Return the last read status value on success or -1 on failure. */ -static int ich_status_poll(u16 bitmask, int wait_til_set) +static int ich_status_poll(uint16_t bitmask, int wait_til_set) { int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; + uint16_t status = 0; while (timeout--) { status = readw_(cntlr.status);

1 0

Patch set updated for coreboot: i945/gma.c use linux code to calculate divisors
by Arthur Heymans 05 Sep '16

05 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16504 -gerrit commit 6b20db2d0004449aad24982c1caf093f263e4cae Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 22:35:32 2016 +0200 i945/gma.c use linux code to calculate divisors The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divors must be such "refclk *(5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which defined by the resolution and refresh rate. This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays (Lenovo T60 with 1024x786, 1400x1050, 2048x1536) might work now. Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 83 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 02caa0a..3f57e55 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -26,6 +26,7 @@ #include <string.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <commonlib/helpers.h> #include "i945.h" #include "chip.h" @@ -43,7 +44,7 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 -#define BASE_FREQUENCY 120000 +#define BASE_FREQUENCY 100000 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT @@ -85,10 +86,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u8 edid_data[128]; unsigned long temp; int hpolarity, vpolarity; - u32 candp1, candn; - u32 best_delta = 0xffffffff; + u32 err_most = 0xffffffff; u32 target_frequency; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -158,43 +159,39 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom - + BASE_FREQUENCY / 2) / BASE_FREQUENCY; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (BASE_FREQUENCY * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + /* p2 divisor must 7 for dual channel LVDS */ + /* and 14 for single channel LVDS */ + pixel_p2 = mode->lvds_dual_channel ? 7 : 14; + target_frequency = mode->pixel_clock; + + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } } } } - if (best_delta == 0xffffffff) { + if (err_most == 0xffffffff) { printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); return -1; } @@ -216,8 +213,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); @@ -242,8 +239,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + FP0(1), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS @@ -252,8 +249,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | @@ -261,8 +257,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16)

1 0

Patch set updated for coreboot: mainboard/google/reef: add baseboard nhlt configuration
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16431 -gerrit commit 26732019a871a695722ee475f44d795787fbe7d0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 20:19:59 2016 -0500 mainboard/google/reef: add baseboard nhlt configuration Move the current NHLT configuration implementation to the baseboard area such that other variants can leverage it or provide their own configuration. BUG=chrome-os-partner:56677 Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/mainboard.c | 15 +-------- .../google/reef/variants/baseboard/Makefile.inc | 1 + .../baseboard/include/baseboard/variants.h | 4 +++ .../google/reef/variants/baseboard/nhlt.c | 37 ++++++++++++++++++++++ 4 files changed, 43 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index a2421df..016c9ac 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -56,20 +56,7 @@ static unsigned long mainboard_write_acpi_tables( if (nhlt == NULL) return start_addr; - /* 2 Channel DMIC array. */ - if (!nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Added 2CH DMIC array.\n"); - - /* Dialog for Headset codec. - * Headset codec is bi-directional but uses the same configuration - * settings for render and capture endpoints. - */ - if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); - - /* MAXIM Smart Amps for left and right speakers. */ - if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) - printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); + variant_nhlt_init(nhlt); end_addr = nhlt_soc_serialize(nhlt, start_addr); diff --git a/src/mainboard/google/reef/variants/baseboard/Makefile.inc b/src/mainboard/google/reef/variants/baseboard/Makefile.inc index f024c2a..d2d344c 100644 --- a/src/mainboard/google/reef/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/reef/variants/baseboard/Makefile.inc @@ -5,5 +5,6 @@ romstage-y += memory.c ramstage-y += boardid.c ramstage-y += gpio.c +ramstage-y += nhlt.c smm-y += gpio.c diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 84e6a30..9f2ed06 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -40,4 +40,8 @@ size_t variant_memory_sku(void); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Seed the NHLT tables with the board specific information. */ +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c new file mode 100644 index 0000000..ef9ec6c --- /dev/null +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +{ + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); +}

1 0

Patch set updated for coreboot: mainboard/google/reef: add baseboard memory configuration
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16430 -gerrit commit bec328edfe58baff7b535bb9cec8e25585ebba51 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 19:53:46 2016 -0500 mainboard/google/reef: add baseboard memory configuration Move the current memory configuration implementation to the baseboard area such that other variants can leverage it. The swizzle config is exported as a global to allow duplicate swizzles to use the same structure while still allowing different memory SKUs. BUG=chrome-os-partner:56677 Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/romstage.c | 156 +------------------ .../google/reef/variants/baseboard/Makefile.inc | 1 + .../baseboard/include/baseboard/variants.h | 8 + .../google/reef/variants/baseboard/memory.c | 168 +++++++++++++++++++++ 4 files changed, 181 insertions(+), 152 deletions(-) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 6a7ed93..0e9917f 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,165 +13,17 @@ * GNU General Public License for more details. */ -#include <gpio.h> +#include <baseboard/variants.h> #include <soc/meminit.h> #include <soc/romstage.h> -#include <variant/gpio.h> - -static const struct lpddr4_swizzle_cfg board_swizzle = { - /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ - .phys[LP4_PHYS_CH0A] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 }, - }, - .phys[LP4_PHYS_CH0B] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 }, - }, - .phys[LP4_PHYS_CH1A] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 }, - }, - .phys[LP4_PHYS_CH1B] = { - /* DQA[0:7] pins of LPDDR4 module. */ - .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 }, - /* DQA[8:15] pins of LPDDR4 module. */ - .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 }, - /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 }, - /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ - .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 }, - }, -}; - -/* - * Proto boards didn't have a memory SKU id. The configuration pins use - * an internal weak pullup with stronger pulldowns for the 0 bits. As - * proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111, - * i.e. 15. - */ -#define PROTO_SKU 15 - -static const struct lpddr4_sku skus[] = { - /* - * K4F6E304HB-MGCJ - both logical channels While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate - * the deneisty as 8Gb per rank. - */ - [0] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "K4F6E304HB-MGCJ", - }, - /* K4F8E304HB-MGCJ - both logical channels */ - [1] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "K4F8E304HB-MGCJ", - }, - /* - * MT53B512M32D2NP-062WT:C - both logical channels. While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate - * the deneisty as 8Gb per rank. - */ - [2] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "MT53B512M32D2NP", - .disable_periodic_retraining = 1, - }, - /* MT53B256M32D1NP-062 WT:C - both logical channels */ - [3] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "MT53B256M32D1NP", - .disable_periodic_retraining = 1, - }, - /* - * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts - * are listed at 16Gb there are 2 ranks per channel so indicate the - * density as 8Gb per rank. - */ - [4] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch0_dual_rank = 1, - .ch1_dual_rank = 1, - .part_num = "H9HCNNNBPUMLHR", - }, - /* H9HCNNN8KUMLHR-NLE - both logical channels */ - [5] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "H9HCNNN8KUMLHR", - }, - /* K4F8E304HB-MGCH - both logical channels */ - [PROTO_SKU] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "K4F8E304HB-MGCH", - }, -}; - -static const struct lpddr4_cfg lp4cfg = { - .skus = skus, - .num_skus = ARRAY_SIZE(skus), - .swizzle_config = &board_swizzle, -}; - -static int get_mem_sku(void) -{ - gpio_t pads[] = { - [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, - [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, - }; - - /* - * Read memory SKU id with internal pullups enabled to handle - * proto boards with no SKU id pins. - */ - return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); -} void mainboard_memory_init_params(FSPM_UPD *memupd) { - int mem_sku = get_mem_sku(); - - meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); + meminit_lpddr4_by_sku(&memupd->FspmConfig, + variant_lpddr4_config(), variant_memory_sku()); } void mainboard_save_dimm_info(void) { - int mem_sku = get_mem_sku(); - - save_lpddr4_dimm_info(&lp4cfg, mem_sku); + save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku()); } diff --git a/src/mainboard/google/reef/variants/baseboard/Makefile.inc b/src/mainboard/google/reef/variants/baseboard/Makefile.inc index a2db09b..f024c2a 100644 --- a/src/mainboard/google/reef/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/reef/variants/baseboard/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += gpio.c romstage-y += boardid.c +romstage-y += memory.c ramstage-y += boardid.c ramstage-y += gpio.c diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index e1883a4..84e6a30 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -17,6 +17,7 @@ #define BASEBOARD_VARIANTS_H #include <soc/gpio.h> +#include <soc/meminit.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -29,6 +30,13 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); +/* Baseboard default swizzle. Can be reused if swizzle is same. */ +extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; +/* Return LPDDR4 configuration structure. */ +const struct lpddr4_cfg *variant_lpddr4_config(void); +/* Return memory SKU for the board. */ +size_t variant_memory_sku(void); + /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c new file mode 100644 index 0000000..a5b0364 --- /dev/null +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <variant/gpio.h> + +const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 }, + }, +}; + +/* + * Proto boards didn't have a memory SKU id. The configuration pins use + * an internal weak pullup with stronger pulldowns for the 0 bits. As + * proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111, + * i.e. 15. + */ +#define PROTO_SKU 15 + +static const struct lpddr4_sku skus[] = { + /* + * K4F6E304HB-MGCJ - both logical channels While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", + }, + /* + * MT53B512M32D2NP-062WT:C - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, + }, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + [3] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, + }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, + /* K4F8E304HB-MGCH - both logical channels */ + [PROTO_SKU] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCH", + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &baseboard_lpddr4_swizzle, +}; + +const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void) +{ + return &lp4cfg; +} + +size_t __attribute__((weak)) variant_memory_sku(void) +{ + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; + + /* + * Read memory SKU id with internal pullups enabled to handle + * proto boards with no SKU id pins. + */ + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +}

1 0

Patch set updated for coreboot: mainboard/google/reef: drop remaining proto board references
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16432 -gerrit commit 4d457c9e490947dc10f6d8c5dd8719bad4db4f88 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 20:29:39 2016 -0500 mainboard/google/reef: drop remaining proto board references The last vestige of the proto boards is the memory sku id gpios. No need for performing the memory sku read with pullups because all current and future boards don't have floating pins. BUG=chrome-os-partner:56791 Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- .../variants/baseboard/include/baseboard/gpio.h | 6 +----- .../google/reef/variants/baseboard/memory.c | 21 +-------------------- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index 90cca36..f60bfdc 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -39,11 +39,7 @@ #define GPIO_PCH_WP GPIO_75 #define GPIO_EC_IN_RW GPIO_41 -/* - * The proto boards didn't have memory SKU pins, but the same ones can be - * utilized as post proto boards because the pins used were never connected - * or no peripheral utilized the signals on proto boards. - */ +/* Memory SKU GPIOs. */ #define MEM_CONFIG3 GPIO_45 #define MEM_CONFIG2 GPIO_38 #define MEM_CONFIG1 GPIO_102 diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index a5b0364..b147253 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -62,14 +62,6 @@ const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { }, }; -/* - * Proto boards didn't have a memory SKU id. The configuration pins use - * an internal weak pullup with stronger pulldowns for the 0 bits. As - * proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111, - * i.e. 15. - */ -#define PROTO_SKU 15 - static const struct lpddr4_sku skus[] = { /* * K4F6E304HB-MGCJ - both logical channels While the parts @@ -133,13 +125,6 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "H9HCNNN8KUMLHR", }, - /* K4F8E304HB-MGCH - both logical channels */ - [PROTO_SKU] = { - .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, - .part_num = "K4F8E304HB-MGCH", - }, }; static const struct lpddr4_cfg lp4cfg = { @@ -160,9 +145,5 @@ size_t __attribute__((weak)) variant_memory_sku(void) [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, }; - /* - * Read memory SKU id with internal pullups enabled to handle - * proto boards with no SKU id pins. - */ - return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); + return gpio_base2_value(pads, ARRAY_SIZE(pads)); }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2016