Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16432
-gerrit
commit 3e7b3b037e311289092a33c0dce00225cb900f93
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 20:29:39 2016 -0500
mainboard/google/reef: drop remaining proto board references
The last vestige of the proto boards is the memory sku id
gpios. The internal pullups are still required because there's
only pulldown stuffing options available on the reef boards.
BUG=chrome-os-partner:56791
Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
.../variants/baseboard/include/baseboard/gpio.h | 6 +-----
.../google/reef/variants/baseboard/memory.c | 21 ++-------------------
2 files changed, 3 insertions(+), 24 deletions(-)
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h
index 90cca36..f60bfdc 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h
@@ -39,11 +39,7 @@
#define GPIO_PCH_WP GPIO_75
#define GPIO_EC_IN_RW GPIO_41
-/*
- * The proto boards didn't have memory SKU pins, but the same ones can be
- * utilized as post proto boards because the pins used were never connected
- * or no peripheral utilized the signals on proto boards.
- */
+/* Memory SKU GPIOs. */
#define MEM_CONFIG3 GPIO_45
#define MEM_CONFIG2 GPIO_38
#define MEM_CONFIG1 GPIO_102
diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c
index a5b0364..c4667f3 100644
--- a/src/mainboard/google/reef/variants/baseboard/memory.c
+++ b/src/mainboard/google/reef/variants/baseboard/memory.c
@@ -62,14 +62,6 @@ const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
},
};
-/*
- * Proto boards didn't have a memory SKU id. The configuration pins use
- * an internal weak pullup with stronger pulldowns for the 0 bits. As
- * proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111,
- * i.e. 15.
- */
-#define PROTO_SKU 15
-
static const struct lpddr4_sku skus[] = {
/*
* K4F6E304HB-MGCJ - both logical channels While the parts
@@ -133,13 +125,6 @@ static const struct lpddr4_sku skus[] = {
.ch1_rank_density = LP4_8Gb_DENSITY,
.part_num = "H9HCNNN8KUMLHR",
},
- /* K4F8E304HB-MGCH - both logical channels */
- [PROTO_SKU] = {
- .speed = LP4_SPEED_2400,
- .ch0_rank_density = LP4_8Gb_DENSITY,
- .ch1_rank_density = LP4_8Gb_DENSITY,
- .part_num = "K4F8E304HB-MGCH",
- },
};
static const struct lpddr4_cfg lp4cfg = {
@@ -160,9 +145,7 @@ size_t __attribute__((weak)) variant_memory_sku(void)
[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
};
- /*
- * Read memory SKU id with internal pullups enabled to handle
- * proto boards with no SKU id pins.
- */
+ /* Need internal pullups enabled as only pulldown stuffing options
+ * exist. */
return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
}
the following patch was just integrated into master:
commit d1e365ac3824bee03feab9a93d15abc224d3bc57
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 17:41:58 2016 -0500
mainboard/google/reef: consolidate gpio related defines to one place
Since multiple boards will be living within one directory move all
the macros for defining anyting related to GPIOs to the gpio.h
header file. That way, when other boards land they can override
or use them as is.
BUG=chrome-os-partner:56677
Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16421
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16421 for details.
-gerrit
the following patch was just integrated into master:
commit b64389d8408b876914acee4ecdeb54929f2ae8ef
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 17:25:35 2016 -0500
mainboard/google/reef: declare mainboard_ec_init() in each C file
There's no common EC header file in the code base, and I didn't
want to use a header file for single declaration. Therefore,
just move the declaration to each file that uses that symbol.
BUG=chrome-os-partner:56677
Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16420
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16420 for details.
-gerrit
the following patch was just integrated into master:
commit 10d67cbad5de7966de7f2f766eb44fb5d6f37272
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 16:56:03 2016 -0500
mainboard/google/reef: add variant API for board_id and gpio
Provide APIs for the board_id() and gpio table functionality.
Default and weak implementations are provided from the baseboard.
BUG=chrome-os-partner:56677
Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16419
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/16419 for details.
-gerrit
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301
-gerrit
commit 77e52a124a7b3100e0c18456951dd7f9bd2bcb6b
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 13:38:19 2016 +0530
kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.
Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/mainboard/intel/kunimitsu/Makefile.inc | 4 ++++
src/mainboard/intel/kunimitsu/ramstage.c | 2 +-
src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index cafa12c..86be420 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -34,3 +34,7 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
+endif
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..44fb9cd 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
new file mode 100644
index 0000000..10bdd21
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* TODO: Read and copy SPD and fill up Rcomp and DQ param */
+}
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 62d6fd4..0a9cb0f 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
-romstage-y += spd.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin