the following patch was just integrated into master:
commit ffa765f6eb49d242df6c74f63c4aa1e6f65143e3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Sep 1 15:50:22 2016 -0700
drivers/i2c/tpm: Add support for cr50 TPM
Add support for the cr50 TPM used in apollolake chromebooks.
This requires custom handling due to chip limitations, which
may be revisited but are needed to get things working today.
- timeouts need to be longer
- must use the older style write+wait+read read protocol
- all 4 bytes of status register must be read at once
- same limitation applies when reading burst count from status reg
- burst count max is 63 bytes, and burst count behaves
slightly differently than other I2C TPMs
- TPM expects the host to drain the full burst count (63 bytes)
from the FIFO on a read
Luckily the existing driver provides most abstraction needed to
make this work seamlessly. To maximize code re-use the support
for cr50 is added directly instead of as a separate driver and the
style is kept similar to the rest of the driver code.
This was tested with the cr50 TPM on a reef board with vboot
use of TPM for secdata storage and factory initialization.
Change-Id: I9b0bc282e41e779da8bf9184be0a11649735a101
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16396
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/16396 for details.
-gerrit
the following patch was just integrated into master:
commit efa579fdc217b92d0696b737cda76a69d1fe1433
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Aug 31 14:48:12 2016 -0700
drivers/i2c/tpm: Allow sleep durations to be set by the chip
Allow the sleep durations used by the driver to be set by the
specific chip so they can be tuned appropriately.
Since we need to read the chip id to know the values use very
conservative defaults for the first command and then set it
to the current values by default.
Change-Id: Ic64159328b18a1471eb06fa8b52b589eec1e1ca2
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16395
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16395 for details.
-gerrit
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16416
-gerrit
commit c87ef6b5a462893f2bad4d57cd61e08eba327e99
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Sep 2 14:45:53 2016 -0700
drivers/i2c/tpm: Fix error handling for tis structure not initialized
If the TPM completely fails to respond then the vendor structure may not
have assigned handlers yet, so catch that case and return error so the
boot can continue to recovery mode instead of asserting over and over.
Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/i2c/tpm/tis.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index c6173b4..ce0de89 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -114,6 +114,9 @@ static ssize_t tpm_transmit(const uint8_t *buf, size_t bufsiz)
memcpy(&ordinal, buf + TPM_CMD_ORDINAL_BYTE, sizeof(ordinal));
ordinal = be32_to_cpu(ordinal);
+ if (!chip->vendor.send || !chip->vendor.status || !chip->vendor.cancel)
+ return -1;
+
if (count == 0) {
printk(BIOS_DEBUG, "tpm_transmit: no data\n");
return -1;
the following patch was just integrated into master:
commit 40ae1706a447ca81fed31287ec30f28823504c01
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Aug 31 13:51:14 2016 -0700
drivers/i2c/tpm: Make driver safe for use in x86 pre-ram
Use CAR accessors where needed for accessing static data.
In some cases this required some minor restructuring to pass
in a variable instead of use a global one.
For the tpm_vendor_init the structure no longer has useful
defaults, which nobody was depending on anyway. This now
requires the caller to provide a non-zero address.
Tested by enabling I2C TPM on reef and compiling successfully.
Change-Id: I8e02fbcebf5fe10c4122632eda1c48b247478289
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16394 for details.
-gerrit
the following patch was just integrated into master:
commit 4a560769ad7811b9cab09325f577d389491f17ed
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Sep 1 16:09:43 2016 -0700
tpm2: Fix tlcl and marshaling code for CAR usage
Fix a few more instances of global variable usage in the tlcl
and marshaling code for tpm2.
For the tlcl case this buffer doesn't need to be static as it
isn't used after this function exits.
Change-Id: Ia739c81d79c6cee9046ae96061045fe4f7fb7c23
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16393
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/16393 for details.
-gerrit
the following patch was just integrated into master:
commit e937513352ca1f5f9ac3e0e7d554cd649f55cb5e
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Sun Sep 4 08:38:33 2016 -0600
Kconfig: Relocate DEVICETREE symbol
Place config DEVICETREE after the sourced mainboard Kconfig. This
gives the mainboard the opportunity to set a unique default value.
Change-Id: Id877e1e8f555334a99b6c0ee1782d06a4a2b7a04
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-on: https://review.coreboot.org/16493
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16493 for details.
-gerrit