Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16416
-gerrit
commit c1ce9ecbd2ec190ae246f87ac8f6fa4105f6ae4d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Sep 2 14:45:53 2016 -0700
drivers/i2c/tpm: Fix error handling for tis structure not initialized
If the TPM completely fails to respond then the vendor structure may not
have assigned handlers yet, so catch that case and return error so the
boot can continue to recovery mode instead of asserting over and over.
Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/i2c/tpm/tis.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index c6173b4..ce0de89 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -114,6 +114,9 @@ static ssize_t tpm_transmit(const uint8_t *buf, size_t bufsiz)
memcpy(&ordinal, buf + TPM_CMD_ORDINAL_BYTE, sizeof(ordinal));
ordinal = be32_to_cpu(ordinal);
+ if (!chip->vendor.send || !chip->vendor.status || !chip->vendor.cancel)
+ return -1;
+
if (count == 0) {
printk(BIOS_DEBUG, "tpm_transmit: no data\n");
return -1;
the following patch was just integrated into master:
commit 93c54704340e27ba219baaced952bc3d8bc52695
Author: Shamile Khan <shamile.khan(a)intel.com>
Date: Thu Sep 1 13:36:50 2016 -0700
google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 lines
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
on the screen. Also the interrupt count for i8042 increments
immediately in /proc/interrupts.
Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Signed-off-by: Shamile Khan <shamile.khan(a)intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/16426 for details.
-gerrit
the following patch was just integrated into master:
commit 37ddb630dd4d7c7a567302d84a814756bf36d7b4
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 20:29:39 2016 -0500
mainboard/google/reef: drop remaining proto board references
The last vestige of the proto boards is the memory sku id
gpios. The internal pullups are still required because there's
only pulldown stuffing options available on the reef boards.
BUG=chrome-os-partner:56791
Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16432
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/16432 for details.
-gerrit
the following patch was just integrated into master:
commit 8db1f8dabb6bb189388a25493e807fbce95fc72d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 20:19:59 2016 -0500
mainboard/google/reef: add baseboard nhlt configuration
Move the current NHLT configuration implementation to the baseboard
area such that other variants can leverage it or provide their
own configuration.
BUG=chrome-os-partner:56677
Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16431
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16431 for details.
-gerrit
the following patch was just integrated into master:
commit d94967dd22f66adf92a751e31e677924a9fc868d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 19:53:46 2016 -0500
mainboard/google/reef: add baseboard memory configuration
Move the current memory configuration implementation to the baseboard
area such that other variants can leverage it. The swizzle config
is exported as a global to allow duplicate swizzles to use the same
structure while still allowing different memory SKUs.
BUG=chrome-os-partner:56677
Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16430
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16430 for details.
-gerrit
the following patch was just integrated into master:
commit 475d2cb19e5e822c10239167864faf647a5d93c5
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 17:50:22 2016 -0500
mainboard/google/reef: provide cros_gpio variant API
Add support for Chrome OS gpio ACPI table information by
providing weak implementation from the baseboard.
BUG=chrome-os-partner:56677
Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16422
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16422 for details.
-gerrit
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16431
-gerrit
commit 47eea84bdc138db14e324d58abfc2261496ded3d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 2 20:19:59 2016 -0500
mainboard/google/reef: add baseboard nhlt configuration
Move the current NHLT configuration implementation to the baseboard
area such that other variants can leverage it or provide their
own configuration.
BUG=chrome-os-partner:56677
Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/reef/mainboard.c | 15 +--------
.../google/reef/variants/baseboard/Makefile.inc | 1 +
.../baseboard/include/baseboard/variants.h | 4 +++
.../google/reef/variants/baseboard/nhlt.c | 37 ++++++++++++++++++++++
4 files changed, 43 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c
index a2421df..016c9ac 100644
--- a/src/mainboard/google/reef/mainboard.c
+++ b/src/mainboard/google/reef/mainboard.c
@@ -56,20 +56,7 @@ static unsigned long mainboard_write_acpi_tables(
if (nhlt == NULL)
return start_addr;
- /* 2 Channel DMIC array. */
- if (!nhlt_soc_add_dmic_array(nhlt, 2))
- printk(BIOS_ERR, "Added 2CH DMIC array.\n");
-
- /* Dialog for Headset codec.
- * Headset codec is bi-directional but uses the same configuration
- * settings for render and capture endpoints.
- */
- if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
- printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
-
- /* MAXIM Smart Amps for left and right speakers. */
- if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
- printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
+ variant_nhlt_init(nhlt);
end_addr = nhlt_soc_serialize(nhlt, start_addr);
diff --git a/src/mainboard/google/reef/variants/baseboard/Makefile.inc b/src/mainboard/google/reef/variants/baseboard/Makefile.inc
index f024c2a..d2d344c 100644
--- a/src/mainboard/google/reef/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/reef/variants/baseboard/Makefile.inc
@@ -5,5 +5,6 @@ romstage-y += memory.c
ramstage-y += boardid.c
ramstage-y += gpio.c
+ramstage-y += nhlt.c
smm-y += gpio.c
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
index 84e6a30..9f2ed06 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
@@ -40,4 +40,8 @@ size_t variant_memory_sku(void);
/* Return ChromeOS gpio table and fill in number of entries. */
const struct cros_gpio *variant_cros_gpios(size_t *num);
+/* Seed the NHLT tables with the board specific information. */
+struct nhlt;
+void variant_nhlt_init(struct nhlt *nhlt);
+
#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c
new file mode 100644
index 0000000..ef9ec6c
--- /dev/null
+++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+{
+ /* 2 Channel DMIC array. */
+ if (!nhlt_soc_add_dmic_array(nhlt, 2))
+ printk(BIOS_ERR, "Added 2CH DMIC array.\n");
+
+ /* Dialog for Headset codec.
+ * Headset codec is bi-directional but uses the same configuration
+ * settings for render and capture endpoints.
+ */
+ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
+
+ /* MAXIM Smart Amps for left and right speakers. */
+ if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
+ printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
+}