coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

1 participants
1340 discussions

New patch to review for coreboot: gigabyte/ga-g41m-es2l: add VESA mode to Kconfig
by Arthur Heymans 05 Sep '16

05 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16501 -gerrit commit 3ba4ffd7c985ad40f2baf1efc8de2c64df9a7710 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Sep 5 12:07:57 2016 +0200 gigabyte/ga-g41m-es2l: add VESA mode to Kconfig This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and vesamode in menuconfig. Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 6452f4d..281d498 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_1024 select INTEL_EDID select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE

1 0

Patch set updated for coreboot: x4x/gma.c: Add VESA native resolution mode
by Arthur Heymans 05 Sep '16

05 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16498 -gerrit commit 6dc4b6230fab4727920b685f8106ca3df60244f3 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 4 16:01:11 2016 +0200 x4x/gma.c: Add VESA native resolution mode This patch implements native resolution, VESA mode, on the VGA output of x4x. Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 260 +++++++++++++++++++++++++++++++++------- 1 file changed, 220 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 2679026..98ed91d 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -26,24 +26,52 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <kconfig.h> +#include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" #include "chip.h" #include "x4x.h" #include <drivers/intel/gma/intel_bios.h> +#include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#define BASE_FREQUENCY 96000 + static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - u8 *mmio) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { + int i; - u32 hactive, vactive; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 target_frequency; + u32 err_most = 0xffffffff; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00040000; + vga_gr_write(0x18, 0); + /* Set up GTT */ + for (i = 0; i < 0x1000; i++) { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -73,107 +101,253 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); + udelay(1); + + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); + intel_gmbus_stop(mmio + GMBUS0); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + target_frequency = mode->pixel_clock; + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } + + u32 candn, candm1, candm2, candp1; + for (candn = 1; candn <= 4; candn++) { + for (candm1 = 23; candm1 >= 17; candm1--) { + for (candm2 = 11; candm2 >= 5; candm2--) { + for (candp1 = 3; candp1 >= 1; candp1--) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * 10; /* 10 == p2 */ + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } + } + } + } + + if (err_most == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * 4); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * 10)); mdelay(1); - write32(mmio + FP0(0), 0x31108); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + FP0(0), (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_CRT_HOTPLUG_MONITOR_COLOR | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) + ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); - - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0x80000000); + } mdelay(1); + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + write32(mmio + 0x000f000c, 0x00002040); mdelay(1); write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + VGACNTRL, 0x0); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0xc4008e); + } write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_CRT_HOTPLUG_MONITOR_COLOR | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); - vga_textmode_init(); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - /* Enable screen memory. */ + /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); /* Clear interrupts. */ write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } } static void native_init(struct device *dev) { + struct resource *lfb_res; + struct resource *pio_res; + u32 physbase; struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); struct northbridge_intel_x4x_config *conf = dev->chip_info; + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + if (gtt_res && gtt_res->base) { printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */ @@ -182,6 +356,7 @@ static void native_init(struct device *dev) static void gma_func0_init(struct device *dev) { + u16 reg16; u32 reg32; /* IGD needs to be Bus Master */ @@ -189,6 +364,11 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + /* configure GMBUSFREQ */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); + reg16 |= 0xbc; + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) native_init(dev); else

1 0

Patch set updated for coreboot: fsp_broadwell_de: Adjust printed address in SPI debug messages
by Werner Zeh 05 Sep '16

05 Sep '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16500 -gerrit commit b762ac68eeb46362c3a6dad3f655b633fab16816 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Sep 5 08:14:23 2016 +0200 fsp_broadwell_de: Adjust printed address in SPI debug messages For an unknown reason the printed address in the SPI debug messages is modified before it is printed by subtracting the constant 0xf020 from the passed in address. What I suppose this debug code should do is to print the used register address within the SPI controller while any parts of this address that belongs to the SPI base address should be omitted. To fix that remove the subtraction of 0xf020 and adjust the address mask to 0x3ff so that only the offset to the registers inside the SPI controller will be visible in the debug messages. In addition switch to uint8_t and friends over u8 to sync up with used types in this file. Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/spi.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 57f7951..f60a4fb 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -159,60 +159,60 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -static u8 readb_(const void *addr) +static uint8_t readb_(const void *addr) { - u8 v = read8(addr); + uint8_t v = read8(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, (unsigned) addr & 0x3ff); } return v; } -static u16 readw_(const void *addr) +static uint16_t readw_(const void *addr) { - u16 v = read16(addr); + uint16_t v = read16(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, (unsigned) addr & 0x3ff); } return v; } -static u32 readl_(const void *addr) +static uint32_t readl_(const void *addr) { - u32 v = read32(addr); + uint32_t v = read32(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, (unsigned) addr & 0x3ff); } return v; } -static void writeb_(u8 b, void *addr) +static void writeb_(uint8_t b, void *addr) { write8(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, (unsigned) addr & 0x3ff); } } -static void writew_(u16 b, void *addr) +static void writew_(uint16_t b, void *addr) { write16(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, (unsigned) addr & 0x3ff); } } -static void writel_(u32 b, void *addr) +static void writel_(uint32_t b, void *addr) { write32(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, (unsigned) addr & 0x3ff); } } @@ -457,10 +457,10 @@ static int spi_setup_offset(spi_transaction *trans) * * Return the last read status value on success or -1 on failure. */ -static int ich_status_poll(u16 bitmask, int wait_til_set) +static int ich_status_poll(uint16_t bitmask, int wait_til_set) { int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; + uint16_t status = 0; while (timeout--) { status = readw_(cntlr.status);

1 0

Patch set updated for coreboot: fsp_baytrail: Refactor code for SPI debug messages
by Werner Zeh 05 Sep '16

05 Sep '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16499 -gerrit commit 7f2a94eeb0486ed835661647c53308e1b66e9322 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Sep 5 07:40:29 2016 +0200 fsp_baytrail: Refactor code for SPI debug messages Use the config switch CONFIG_DEBUG_SPI_FLASH on compiler level rather then on preprocessor level to ensure that the code is compiled even if the switch is not selected. In addition the following two changes are introduced: 1. Prepend the debug messages with 'SPI:' to make the output more meaningful. 2. Change the address mask from 0xffff to 0x3ff and remove the subtraction of the constant value 0xf020 in order to print only the register offset within the SPI controller and avoid the visibility of any fragments from SPI base address. 3. Switch to uint8_t and friends instead of u8 to sync up with other code in the same file. Change-Id: Iaf46f29a775039007a402fe862839df06a4cbfaa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/spi.c | 71 ++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 36 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 1b85fc5..01cc64a 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -158,64 +158,63 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) +static uint8_t readb_(const void *addr) { - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint8_t v = read8(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0x3ff)); + } return v; } -static u16 readw_(const void *addr) +static uint16_t readw_(const void *addr) { - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint16_t v = read16(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0x3ff)); + } return v; } -static u32 readl_(const void *addr) +static uint32_t readl_(const void *addr) { - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint32_t v = read32(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0x3ff)); + } return v; } -static void writeb_(u8 b, void *addr) +static void writeb_(uint8_t b, void *addr) { write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0x3ff)); + } } -static void writew_(u16 b, void *addr) +static void writew_(uint16_t b, void *addr) { write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0x3ff)); + } } -static void writel_(u32 b, void *addr) +static void writel_(uint32_t b, void *addr) { write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0x3ff)); + } } -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - static void write_reg(const void *value, void *dest, uint32_t size) { const uint8_t *bvalue = value; @@ -441,10 +440,10 @@ static int spi_setup_offset(spi_transaction *trans) * * Return the last read status value on success or -1 on failure. */ -static int ich_status_poll(u16 bitmask, int wait_til_set) +static int ich_status_poll(uint16_t bitmask, int wait_til_set) { int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; + uint16_t status = 0; while (timeout--) { status = readw_(cntlr.status);

1 0

New patch to review for coreboot: fsp_broadwell_de: Adjust printed address in SPI debug messages
by Werner Zeh 05 Sep '16

05 Sep '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16500 -gerrit commit 67d49207e2322500f83653c963f8b07a742358c9 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Sep 5 08:14:23 2016 +0200 fsp_broadwell_de: Adjust printed address in SPI debug messages For an unknown reason the printed address in the SPI debug messages is modified before it is printed by subtracting the constant 0xf020 from the passed in address. What I suppose this debug code should do is to print the used register address within the SPI controller while any parts of this address that belongs to the SPI base address should be omitted. To fix that remove the subtraction of 0xf020 and adjust the address mask to 0x3ff so that only the offset to the registers inside the SPI controller will be visible in the debug messages. Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/spi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 57f7951..fc2eee4 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -164,7 +164,7 @@ static u8 readb_(const void *addr) u8 v = read8(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, (unsigned) addr & 0x3ff); } return v; } @@ -174,7 +174,7 @@ static u16 readw_(const void *addr) u16 v = read16(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, (unsigned) addr & 0x3ff); } return v; } @@ -184,7 +184,7 @@ static u32 readl_(const void *addr) u32 v = read32(addr); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, (unsigned) addr & 0x3ff); } return v; } @@ -194,7 +194,7 @@ static void writeb_(u8 b, void *addr) write8(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, (unsigned) addr & 0x3ff); } } @@ -203,7 +203,7 @@ static void writew_(u16 b, void *addr) write16(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, (unsigned) addr & 0x3ff); } } @@ -212,7 +212,7 @@ static void writel_(u32 b, void *addr) write32(addr, b); if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, (unsigned) addr & 0x3ff); } }

1 0

New patch to review for coreboot: fsp_baytrail: Refactor code for SPI debug messages
by Werner Zeh 05 Sep '16

05 Sep '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16499 -gerrit commit f83126988f4af27016fcb1deb9e5d83cd23d778f Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Sep 5 07:40:29 2016 +0200 fsp_baytrail: Refactor code for SPI debug messages Use the config switch CONFIG_DEBUG_SPI_FLASH on compiler level rather then on preprocessor level to ensure that the code is compiled even if the switch is not selected. In addition the following two changes are introduced: 1. Prepend the debug messages with 'SPI:' to make the output more meaningful. 2. Change the address mask from 0xffff to 0x3ff and remove the subtraction of the constant value 0xf020 in order to print only the register offset within the SPI controller and avoid the visibility of any fragments from SPI base address. Change-Id: Iaf46f29a775039007a402fe862839df06a4cbfaa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/spi.c | 67 ++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 1b85fc5..400af59 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -158,64 +158,63 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) +static uint8_t readb_(const void *addr) { - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint8_t v = read8(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0x3ff)); + } return v; } -static u16 readw_(const void *addr) +static uint16_t readw_(const void *addr) { - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint16_t v = read16(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0x3ff)); + } return v; } -static u32 readl_(const void *addr) +static uint32_t readl_(const void *addr) { - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + uint32_t v = read32(addr); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0x3ff)); + } return v; } -static void writeb_(u8 b, void *addr) +static void writeb_(uint8_t b, void *addr) { write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0x3ff)); + } } -static void writew_(u16 b, void *addr) +static void writew_(uint16_t b, void *addr) { write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0x3ff)); + } } -static void writel_(u32 b, void *addr) +static void writel_(uint32_t b, void *addr) { write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0x3ff)); + } } -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - static void write_reg(const void *value, void *dest, uint32_t size) { const uint8_t *bvalue = value;

1 0

Patch merged into coreboot/master: src/superio: Improve code formatting
by gerrit＠coreboot.org 05 Sep '16

05 Sep '16

the following patch was just integrated into master: commit a15dde0719be9f580038a6df32ff18fb017886bf Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Sep 3 08:22:15 2016 +0200 src/superio: Improve code formatting Change-Id: I8597d205ca84bee0171c3d45549a28b58a050529 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16433 Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev(a)dettori.io> See https://review.coreboot.org/16433 for details. -gerrit

1 0

Patch merged into coreboot/master: intel/minnowmax: Clean up whitespace
by gerrit＠coreboot.org 05 Sep '16

05 Sep '16

the following patch was just integrated into master: commit 96a8b54edb2cefd3a708a8850e9370f5ce556615 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Sep 2 15:49:06 2016 -0600 intel/minnowmax: Clean up whitespace Align the column of comments. Change-Id: Iec3a173af26710f8ff56519a14784344ea71d489 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/16427 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16427 for details. -gerrit

1 0

Patch set updated for coreboot: intel/minnowmax: Clean up whitespace
by Marshall Dawson 04 Sep '16

04 Sep '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16427 -gerrit commit c5fa07abb17699d7cc2a71f82d962fc9c020c335 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Sep 2 15:49:06 2016 -0600 intel/minnowmax: Clean up whitespace Align the column of comments. Change-Id: Iec3a173af26710f8ff56519a14784344ea71d489 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/intel/minnowmax/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index 228b55b..34a7503 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -178,9 +178,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/ GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ - GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ - GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ - GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ + GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ + GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ GPIO_FUNC0, /* GPIO_S5[12] - PMC_SUSCLK0 */ GPIO_FUNC1, /* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */

1 0

New patch to review for coreboot: x4x/gma.c: Add VESA native resolution mode
by Arthur Heymans 04 Sep '16

04 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16498 -gerrit commit 12e7cf948a47923089fbffff47a7c2a7ac3dea95 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 4 16:01:11 2016 +0200 x4x/gma.c: Add VESA native resolution mode This patch implement native resolution, VESA mode, on the VGA output of x4x. This patch also adds this option to the Kconfig of targets using this northbridge (gigabyte/ga-g41m-es2l). Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/northbridge/intel/x4x/gma.c | 260 +++++++++++++++++++++++----- 2 files changed, 221 insertions(+), 40 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 6452f4d..281d498 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_1024 select INTEL_EDID select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 2679026..5d0df54 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -26,24 +26,52 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <kconfig.h> +#include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" #include "chip.h" #include "x4x.h" #include <drivers/intel/gma/intel_bios.h> +#include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#define BASE_FREQUENCY 96000 + static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - u8 *mmio) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { + int i; - u32 hactive, vactive; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 target_frequency; + u32 err_most = 0xffffffff; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00040000; + vga_gr_write(0x18, 0); + /* Setup GTT */ + for (i = 0; i < 0x1000; i++) { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -73,107 +101,253 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); + udelay(1); + + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); + intel_gmbus_stop(mmio + GMBUS0); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + target_frequency = mode->pixel_clock; + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } + + u32 candn, candm1, candm2, candp1; + for (candn = 1; candn <= 4; candn++) { + for (candm1 = 23; candm1 >= 17; candm1--) { + for (candm2 = 11; candm2 >= 5; candm2--) { + for (candp1 = 3; candp1 >= 1; candp1--) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * 10; /* 10 == p2 */ + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } + } + } + } + + if (err_most == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * 4); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * 10)); mdelay(1); - write32(mmio + FP0(0), 0x31108); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + FP0(0), (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_CRT_HOTPLUG_MONITOR_COLOR | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) + ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); - - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0x80000000); + } mdelay(1); + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + write32(mmio + 0x000f000c, 0x00002040); mdelay(1); write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + VGACNTRL, 0x0); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0xc4008e); + } write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_CRT_HOTPLUG_MONITOR_COLOR | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); - vga_textmode_init(); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - /* Enable screen memory. */ + /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); /* Clear interrupts. */ write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } } static void native_init(struct device *dev) { + struct resource *lfb_res; + struct resource *pio_res; + u32 physbase; struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); struct northbridge_intel_x4x_config *conf = dev->chip_info; + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + if (gtt_res && gtt_res->base) { printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */ @@ -182,6 +356,7 @@ static void native_init(struct device *dev) static void gma_func0_init(struct device *dev) { + u16 reg16; u32 reg32; /* IGD needs to be Bus Master */ @@ -189,6 +364,11 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + /* configure GMBUSFREQ */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); + reg16 |= 0xbc; + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) native_init(dev); else

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2016