coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/google/reef: add variant API for board_id and gpio
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16419 -gerrit commit d3beda740b6204847aa66a05ed1b1b2cdd8b9b27 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 16:56:03 2016 -0500 mainboard/google/reef: add variant API for board_id and gpio Provide APIs for the board_id() and gpio table functionality. Default and weak implementations are provided from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/boardid.c | 5 +- src/mainboard/google/reef/bootblock.c | 8 +- src/mainboard/google/reef/mainboard.c | 6 +- src/mainboard/google/reef/smihandler.c | 7 +- .../google/reef/variants/baseboard/Makefile.inc | 8 + .../google/reef/variants/baseboard/boardid.c | 22 ++ .../google/reef/variants/baseboard/gpio.c | 378 +++++++++++++++++++++ .../variants/baseboard/include/baseboard/gpio.h | 342 ------------------- .../baseboard/include/baseboard/variants.h | 31 ++ 9 files changed, 459 insertions(+), 348 deletions(-) diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c index 4eb9f48..f240fca 100644 --- a/src/mainboard/google/reef/boardid.c +++ b/src/mainboard/google/reef/boardid.c @@ -14,15 +14,16 @@ * GNU General Public License for more details. */ +#include <baseboard/variants.h> #include <boardid.h> -#include <ec/google/chromeec/ec.h> +#include <stddef.h> uint8_t board_id(void) { MAYBE_STATIC int id = -1; if (id < 0) - id = google_chromeec_get_board_version(); + id = variant_board_id(); return id; } diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index 7a767ec..ab010e2 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -13,15 +13,19 @@ * GNU General Public License for more details. */ +#include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/lpc.h> #include <soc/gpio.h> #include <variant/ec.h> -#include <variant/gpio.h> void bootblock_mainboard_init(void) { + const struct pad_config *pads; + size_t num; + lpc_configure_pads(); - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); mainboard_ec_init(); } diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 832019d..7d5a7e1 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <baseboard/variants.h> #include <boardid.h> #include <console/console.h> #include <device/device.h> @@ -27,11 +28,14 @@ static void mainboard_init(void *chip_info) { int boardid; + const struct pad_config *pads; + size_t num; boardid = board_id(); printk(BIOS_INFO, "Board ID: %d\n", boardid); - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); mainboard_ec_init(); } diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index bbbdbcb..dbf9162 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -15,6 +15,7 @@ */ #include <arch/acpi.h> +#include <baseboard/variants.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <soc/pm.h> @@ -31,7 +32,11 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) void mainboard_smi_sleep(u8 slp_typ) { - gpio_configure_pads(sleep_gpio_table, ARRAY_SIZE(sleep_gpio_table)); + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(&num); + gpio_configure_pads(pads, num); if (slp_typ == ACPI_S3) enable_gpe(GPIO_TIER_1_SCI); diff --git a/src/mainboard/google/reef/variants/baseboard/Makefile.inc b/src/mainboard/google/reef/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..a2db09b --- /dev/null +++ b/src/mainboard/google/reef/variants/baseboard/Makefile.inc @@ -0,0 +1,8 @@ +bootblock-y += gpio.c + +romstage-y += boardid.c + +ramstage-y += boardid.c +ramstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/reef/variants/baseboard/boardid.c b/src/mainboard/google/reef/variants/baseboard/boardid.c new file mode 100644 index 0000000..26f1588 --- /dev/null +++ b/src/mainboard/google/reef/variants/baseboard/boardid.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + return google_chromeec_get_board_version(); +} diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c new file mode 100644 index 0000000..09a58be --- /dev/null +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -0,0 +1,378 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* WLAN */ + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */ + + /* EMMC interface */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused. */ + PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW. Pull up by 20K */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + /* No h/w write proect for uSD cards, pull down by 20K */ + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus -- unused. */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ + PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ + PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + + /* I2C0 - Audio */ + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C1 - NFC with external pulls */ + PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */ + PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */ + + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + + /* I2C3 - touch */ + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */ + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */ + + /* I2C4 - trackpad */ + PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */ + PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */ + + /* I2C5 -- pen with external pulls */ + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */ + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */ + + /* I2C6-7 -- unused. */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* Audio Amp - I2S6 */ + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */ + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */ + PAD_CFG_GPI(GPIO_148, UP_20K, DEEP), /* ISH_GPIO_2 - unused */ + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */ + + /* NFC Reset */ + PAD_CFG_GPO(GPIO_150, 1, DEEP), /* ISH_GPIO_4 */ + + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* ISH_GPIO_5 - unused */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ + + PAD_CFG_GPI(GPIO_153, UP_20K, DEEP), /* ISH_GPIO_7 - unused */ + PAD_CFG_GPI(GPIO_154, UP_20K, DEEP), /* ISH_GPIO_8 - unused */ + PAD_CFG_GPI(GPIO_155, UP_20K, DEEP), /* ISH_GPIO_9 - unused */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), /* WLAN with external pull */ + PAD_CFG_GPI(GPIO_210, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_211, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_212, UP_20K, DEEP), /* unused */ + + /* OSC_CLK_OUT_[0:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */ + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* DDI[0:1] SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, UP_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, UP_20K, DEEP), /* HV_DDI0_DDC_SCL */ + PAD_CFG_GPI(GPIO_189, UP_20K, DEEP), /* HV_DDI1_DDC_SDA */ + PAD_CFG_GPI(GPIO_190, UP_20K, DEEP), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, UP_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, UP_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control */ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */ + PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */ + PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */ + + /* Hot plug detect. */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, UP_20K, DEEP), /* MDSI_A_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP), + + /* PMIC Signals Unused signals related to an old PMIC interface */ + PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, NONE, DEEP), /* unused external pull */ + PAD_CFG_GPI(GPIO_214, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_215, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- largely unused */ + PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */ + PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 */ + PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ + PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ + + /* I2S2 -- Headset amp */ + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* AVS_I2S2_BCLK */ + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* AVS_I2S2_SW_SYNC */ + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* AVS_I2S2_SDI */ + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* AVS_I2S2_SDO */ + + /* I2S3 -- largely unused. */ + PAD_CFG_GPI(GPIO_89, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_90, UP_20K, DEEP), /* GPS_HOST_WAKE */ + PAD_CFG_GPO(GPIO_91, 1, DEEP), /* GPS_EN */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ + + /* Fast SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ + + /* SIO_SPI_0 - Used for FP */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ + + /* SIO_SPI_1 -- largely unused */ + PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */ + PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ + PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ + /* Headset interrupt */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ + PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* SIO_SPI_2_CLK */ + PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ + /* WLAN_PE_RST - default to deasserted. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ + PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), + + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ + PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ + PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ + PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ + PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ + PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ + PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ + PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ + PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ + PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ + /* Next 2 are straps. */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, UP_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, UP_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, UP_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, UP_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, UP_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, UP_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, UP_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ +}; + +const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ +}; + +const struct pad_config * __attribute__((weak)) +variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* GPIO settings before entering sleep. */ +static const struct pad_config sleep_gpio_table[] = { + PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ +}; + +const struct pad_config * __attribute__((weak)) +variant_sleep_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +} diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index d43c35f..b3581b6 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -18,347 +18,6 @@ #include <soc/gpio.h> -#ifndef __ACPI__ -/* - * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' - * table found in EDS vol 1, but some pins aren't grouped functionally in - * the table so those were moved for more logical grouping. - */ -static const struct pad_config gpio_table[] = { - /* PCIE_WAKE[0:3]_N */ - PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* WLAN */ - PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */ - - /* EMMC interface */ - PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ - PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ - PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ - PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ - PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ - PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ - PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ - PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ - PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ - PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ - - /* SDIO -- unused. */ - PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ - PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ - /* Configure SDIO to enable power gating */ - PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ - PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ - PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ - PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ - - /* SDCARD */ - /* Pull down clock by 20K */ - PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ - PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ - PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ - PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ - PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ - /* Card detect is active LOW. Pull up by 20K */ - PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ - PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ - /* CLK feedback, internal signal, needs 20K pull down */ - PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ - /* No h/w write proect for uSD cards, pull down by 20K */ - PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ - /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ - PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ - - /* SMBus -- unused. */ - PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ - PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ - PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ - - /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ - PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ - PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */ - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), /* LPC_AD1 */ - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), /* LPC_AD2 */ - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), /* LPC_AD3 */ - PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */ - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ - - /* I2C0 - Audio */ - PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ - PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ - - /* I2C1 - NFC with external pulls */ - PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */ - PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */ - - /* I2C2 - TPM */ - PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ - PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ - - /* I2C3 - touch */ - PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */ - PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */ - - /* I2C4 - trackpad */ - PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */ - PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */ - - /* I2C5 -- pen with external pulls */ - PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */ - PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */ - - /* I2C6-7 -- unused. */ - PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ - PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ - PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ - PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ - - /* Audio Amp - I2S6 */ - PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */ - PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */ - PAD_CFG_GPI(GPIO_148, UP_20K, DEEP), /* ISH_GPIO_2 - unused */ - PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */ - - /* NFC Reset */ - PAD_CFG_GPO(GPIO_150, 1, DEEP), /* ISH_GPIO_4 */ - - PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* ISH_GPIO_5 - unused */ - - /* Touch enable */ - PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ - - PAD_CFG_GPI(GPIO_153, UP_20K, DEEP), /* ISH_GPIO_7 - unused */ - PAD_CFG_GPI(GPIO_154, UP_20K, DEEP), /* ISH_GPIO_8 - unused */ - PAD_CFG_GPI(GPIO_155, UP_20K, DEEP), /* ISH_GPIO_9 - unused */ - - /* PCIE_CLKREQ[0:3]_N */ - PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), /* WLAN with external pull */ - PAD_CFG_GPI(GPIO_210, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_211, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_212, UP_20K, DEEP), /* unused */ - - /* OSC_CLK_OUT_[0:4] -- unused */ - PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP), - PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP), - - /* PMU Signals */ - PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */ - PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ - PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ - PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ - PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ - PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */ - PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ - PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ - PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ - PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ - PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ - PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ - - /* DDI[0:1] SDA and SCL -- unused */ - PAD_CFG_GPI(GPIO_187, UP_20K, DEEP), /* HV_DDI0_DDC_SDA */ - PAD_CFG_GPI(GPIO_188, UP_20K, DEEP), /* HV_DDI0_DDC_SCL */ - PAD_CFG_GPI(GPIO_189, UP_20K, DEEP), /* HV_DDI1_DDC_SDA */ - PAD_CFG_GPI(GPIO_190, UP_20K, DEEP), /* HV_DDI1_DDC_SCL */ - - /* MIPI I2C -- unused */ - PAD_CFG_GPI(GPIO_191, UP_20K, DEEP), /* MIPI_I2C_SDA */ - PAD_CFG_GPI(GPIO_192, UP_20K, DEEP), /* MIPI_I2C_SCL */ - - /* Panel 0 control */ - PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */ - PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */ - PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */ - - /* Panel 1 control -- unused */ - PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */ - PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */ - PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */ - - /* Hot plug detect. */ - PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ - PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ - - /* MDSI signals -- unused */ - PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */ - PAD_CFG_GPI(GPIO_202, UP_20K, DEEP), /* MDSI_A_TE */ - - /* USB overcurrent pins. */ - PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ - PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ - - /* PMC SPI -- almost entirely unused */ - PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), - PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */ - PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), - PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP), - PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP), - PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP), - - /* PMIC Signals Unused signals related to an old PMIC interface */ - PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */ - PAD_CFG_GPI(GPIO_213, NONE, DEEP), /* unused external pull */ - PAD_CFG_GPI(GPIO_214, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_215, UP_20K, DEEP), /* unused */ - PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */ - PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP), /* unused */ - PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ - PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ - PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ - - /* I2S1 -- largely unused */ - PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */ - PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ - PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */ - PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */ - PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */ - - /* DMIC or I2S4 */ - PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ - PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ - PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ - PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ - PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ - - /* I2S2 -- Headset amp */ - PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */ - PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* AVS_I2S2_BCLK */ - PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* AVS_I2S2_SW_SYNC */ - PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* AVS_I2S2_SDI */ - PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* AVS_I2S2_SDO */ - - /* I2S3 -- largely unused. */ - PAD_CFG_GPI(GPIO_89, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_90, UP_20K, DEEP), /* GPS_HOST_WAKE */ - PAD_CFG_GPO(GPIO_91, 1, DEEP), /* GPS_EN */ - PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ - - /* Fast SPI */ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ - PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ - PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ - PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ - PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ - PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ - - /* SIO_SPI_0 - Used for FP */ - PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ - PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ - PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ - PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ - PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ - - /* SIO_SPI_1 -- largely unused */ - PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */ - PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ - PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ - /* Headset interrupt */ - PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ - PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ - - /* SIO_SPI_2 -- unused */ - PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* SIO_SPI_2_CLK */ - PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ - PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ - PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ - /* WLAN_PE_RST - default to deasserted. */ - PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ - PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ - - /* Debug tracing. */ - PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ - PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), - - PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ - PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ - PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ - PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ - PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ - PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ - PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ - PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ - PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ - PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ - PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ - PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ - PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ - PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ - PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ - PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ - PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ - PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ - PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ - PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ - - /* LPSS_UART[0:2] */ - PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ - /* Next 2 are straps. */ - PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ - PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ - PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ - PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ - PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ - PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ - PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ - PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ - PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ - - /* Camera interface -- completely unused. */ - PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */ - PAD_CFG_GPI(GPIO_63, UP_20K, DEEP), /* GP_CAMERASB01 */ - PAD_CFG_GPI(GPIO_64, UP_20K, DEEP), /* GP_CAMERASB02 */ - PAD_CFG_GPI(GPIO_65, UP_20K, DEEP), /* GP_CAMERASB03 */ - PAD_CFG_GPI(GPIO_66, UP_20K, DEEP), /* GP_CAMERASB04 */ - PAD_CFG_GPI(GPIO_67, UP_20K, DEEP), /* GP_CAMERASB05 */ - PAD_CFG_GPI(GPIO_68, UP_20K, DEEP), /* GP_CAMERASB06 */ - PAD_CFG_GPI(GPIO_69, UP_20K, DEEP), /* GP_CAMERASB07 */ - PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ - PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ - PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ - PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ -}; - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ - /* I2C2 - TPM */ - PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ - PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ - /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ - PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ -}; - -/* GPIO settings before entering sleep. */ -static const struct pad_config sleep_gpio_table[] = { - PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ -}; - /* * The proto boards didn't have memory SKU pins, but the same ones can be * utilized as post proto boards because the pins used were never connected @@ -369,5 +28,4 @@ static const struct pad_config sleep_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 -#endif /* __ACPI__ */ #endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..d103356 --- /dev/null +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/gpio.h> +#include <stdint.h> + +/* Return the board id for the current variant board. */ +uint8_t variant_board_id(void); + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num); + +#endif /* BASEBOARD_VARIANTS_H */

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Patch set updated for coreboot: mainboard/google/reef: consolidate gpio related defines to one place
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16421 -gerrit commit 6d8f3c4c0536877114ec814c5f6f7eaf58ac4da8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 17:41:58 2016 -0500 mainboard/google/reef: consolidate gpio related defines to one place Since multiple boards will be living within one directory move all the macros for defining anyting related to GPIOs to the gpio.h header file. That way, when other boards land they can override or use them as is. BUG=chrome-os-partner:56677 Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/chromeos.c | 4 --- .../reef/variants/baseboard/include/baseboard/ec.h | 17 ------------- .../variants/baseboard/include/baseboard/gpio.h | 29 +++++++++++++++++++--- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index ea0f68e..7d7af9e 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -18,12 +18,8 @@ #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> -#include <variant/ec.h> #include <variant/gpio.h> -#define GPIO_PCH_WP GPIO_75 -#define GPIO_EC_IN_RW GPIO_41 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 5c8e306..9c8549d 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -18,23 +18,6 @@ #include <ec/google/chromeec/ec_commands.h> -/* - * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 - * which is North community - */ -#define EC_SCI_GPI GPE0_DW1_11 - -/* EC SMI */ -#define EC_SMI_GPI GPIO_49 - -/* - * On lidopen/lidclose GPIO_22 from North Community gets toggled and - * is used in _PRW to wake up device from sleep. GPIO_22 maps to - * group GPIO_GPE_N_31_0 and the pad is configured as SCI with - * EDGE_SINGLE and INVERT. - */ -#define GPE_EC_WAKE GPE0_DW1_22 - #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index b3581b6..90cca36 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -19,13 +19,34 @@ #include <soc/gpio.h> /* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 + +/* EC SMI */ +#define EC_SMI_GPI GPIO_49 + +/* + * On lidopen/lidclose GPIO_22 from North Community gets toggled and + * is used in _PRW to wake up device from sleep. GPIO_22 maps to + * group GPIO_GPE_N_31_0 and the pad is configured as SCI with + * EDGE_SINGLE and INVERT. + */ +#define GPE_EC_WAKE GPE0_DW1_22 + +/* Write Protect and indication if EC is in RW code. */ +#define GPIO_PCH_WP GPIO_75 +#define GPIO_EC_IN_RW GPIO_41 + +/* * The proto boards didn't have memory SKU pins, but the same ones can be * utilized as post proto boards because the pins used were never connected * or no peripheral utilized the signals on proto boards. */ -#define MEM_CONFIG3 GPIO_45 -#define MEM_CONFIG2 GPIO_38 -#define MEM_CONFIG1 GPIO_102 -#define MEM_CONFIG0 GPIO_101 +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 #endif /* BASEBOARD_GPIO_H */

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Patch set updated for coreboot: mainboard/google/reef: declare mainboard_ec_init() in each C file
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16420 -gerrit commit df144ae2beebfe394d4be558ee8b6f5246654c32 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 17:25:35 2016 -0500 mainboard/google/reef: declare mainboard_ec_init() in each C file There's no common EC header file in the code base, and I didn't want to use a header file for single declaration. Therefore, just move the declaration to each file that uses that symbol. BUG=chrome-os-partner:56677 Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/bootblock.c | 2 ++ src/mainboard/google/reef/ec.c | 2 ++ src/mainboard/google/reef/mainboard.c | 2 ++ src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h | 4 ---- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index ab010e2..da66009 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -19,6 +19,8 @@ #include <soc/gpio.h> #include <variant/ec.h> +void mainboard_ec_init(void); + void bootblock_mainboard_init(void) { const struct pad_config *pads; diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index 612708e..e1832fd 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -20,6 +20,8 @@ #include <soc/lpc.h> #include <variant/ec.h> +void mainboard_ec_init(void); + static void ramstage_ec_init(void) { printk(BIOS_ERR, "mainboard: EC init\n"); diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 7d5a7e1..a2421df 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -25,6 +25,8 @@ #include <variant/ec.h> #include <variant/gpio.h> +void mainboard_ec_init(void); + static void mainboard_init(void *chip_info) { int boardid; diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 7763630..5c8e306 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -70,8 +70,4 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) -#ifndef __ACPI__ -extern void mainboard_ec_init(void); -#endif - #endif

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Patch set updated for coreboot: mainboard/google/reef: provide cros_gpio variant API
by Aaron Durbin 05 Sep '16

05 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16422 -gerrit commit 297d0ed1dfe6f0884b6351c91c4c34711f5a1aeb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 2 17:50:22 2016 -0500 mainboard/google/reef: provide cros_gpio variant API Add support for Chrome OS gpio ACPI table information by providing weak implementation from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/chromeos.c | 12 ++++++------ src/mainboard/google/reef/variants/baseboard/gpio.c | 11 +++++++++++ .../reef/variants/baseboard/include/baseboard/variants.h | 4 ++++ 3 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 7d7af9e..58c2cd8 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <baseboard/variants.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> @@ -67,12 +68,11 @@ int get_write_protect_state(void) return gpio_get(GPIO_PCH_WP); } -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), -}; - void mainboard_chromeos_acpi_generate(void) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); } diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 09a58be..828fc34 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -376,3 +376,14 @@ variant_sleep_gpio_table(size_t *num) *num = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +}; + +const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index d103356..e1883a4 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -18,6 +18,7 @@ #include <soc/gpio.h> #include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Return the board id for the current variant board. */ uint8_t variant_board_id(void); @@ -28,4 +29,7 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + #endif /* BASEBOARD_VARIANTS_H */

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Patch set updated for coreboot: i945/gma.c use latest linux code to calculate divisors
by Arthur Heymans 05 Sep '16

05 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16504 -gerrit commit 12c5d98f2b230dbc8793ff0cf96cca7332c6ec2e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 22:35:32 2016 +0200 i945/gma.c use latest linux code to calculate divisors The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divors must be such "refclk *(5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which defined by the resolution and refresh rate. This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays (Lenovo T60 with 1024x786, 1400x1050, 2048x1536) might work now. Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 83 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 02caa0a..3f57e55 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -26,6 +26,7 @@ #include <string.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <commonlib/helpers.h> #include "i945.h" #include "chip.h" @@ -43,7 +44,7 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 -#define BASE_FREQUENCY 120000 +#define BASE_FREQUENCY 100000 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT @@ -85,10 +86,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u8 edid_data[128]; unsigned long temp; int hpolarity, vpolarity; - u32 candp1, candn; - u32 best_delta = 0xffffffff; + u32 err_most = 0xffffffff; u32 target_frequency; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -158,43 +159,39 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom - + BASE_FREQUENCY / 2) / BASE_FREQUENCY; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (BASE_FREQUENCY * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + /* p2 divisor must 7 for dual channel LVDS */ + /* and 14 for single channel LVDS */ + pixel_p2 = mode->lvds_dual_channel ? 7 : 14; + target_frequency = mode->pixel_clock; + + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } } } } - if (best_delta == 0xffffffff) { + if (err_most == 0xffffffff) { printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); return -1; } @@ -216,8 +213,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); @@ -242,8 +239,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + FP0(1), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS @@ -252,8 +249,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | @@ -261,8 +257,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16)

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New patch to review for coreboot: i945/gma.c use latest linux code to calculate divisors.
by Arthur Heymans 05 Sep '16

05 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16504 -gerrit commit f09ce5870025a98b6e497fd232adffde468c735a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 22:35:32 2016 +0200 i945/gma.c use latest linux code to calculate divisors. The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. This patch also fixes reference frequency. This patch reuses linux code to correctly compute divisors. The result is that some previously not working displays (Lenovo T60 with 1024x786, 1400x1050, 2048x1536) TESTED on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 02caa0a..d1d68d4 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -26,6 +26,8 @@ #include <string.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <commonlib/helpers.h> + #include "i945.h" #include "chip.h" @@ -43,7 +45,7 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 -#define BASE_FREQUENCY 120000 +#define BASE_FREQUENCY 100000 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT @@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u8 edid_data[128]; unsigned long temp; int hpolarity, vpolarity; - u32 candp1, candn; - u32 best_delta = 0xffffffff; + u32 err_most = 0xffffffff; u32 target_frequency; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom - + BASE_FREQUENCY / 2) / BASE_FREQUENCY; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (BASE_FREQUENCY * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + pixel_p2 = mode->lvds_dual_channel ? 7 : 14; + target_frequency = mode->pixel_clock; + + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } } } } - if (best_delta == 0xffffffff) { + if (err_most == 0xffffffff) { printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); return -1; } @@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); @@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + FP0(1), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS @@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | @@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16)

1 0

New patch to review for coreboot: src/ec: Improve code formatting
by HAOUAS Elyes 05 Sep '16

05 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16503 -gerrit commit 363aa07626ede88a01fbd84aa5300f76f70eb146 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Sep 5 19:55:34 2016 +0200 src/ec: Improve code formatting Change-Id: I93b71ca577c973046d1651d92665168b329eda1b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/ec/compal/ene932/acpi/ec.asl | 6 +- src/ec/compal/ene932/ec.c | 2 +- src/ec/google/chromeec/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/ec.asl | 258 +++++++++++++++++----------------- src/ec/lenovo/h8/acpi/lid.asl | 2 +- src/ec/lenovo/h8/acpi/sleepbutton.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 20 +-- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/quanta/it8518/ec.c | 2 +- 9 files changed, 148 insertions(+), 148 deletions(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 93ddcbe..8ecfd2b 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -212,9 +212,9 @@ Device (EC0) // 101 : CPT , 1, // Reserved ; C0h.7 BST0, 8, // Battery Status ; C1h - // Bit0 : Discharging - // Bit1 : Charging - // Bit2 : Discharg and Critical Low + // Bit0 : Discharging + // Bit1 : Charging + // Bit2 : Discharg and Critical Low // Bit3-7 : Reserved BRC0, 16, // Batt Remaining Capacity ; C2h, C3h BSN0, 16, // Batt Serial Number ; C4h, C5h diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 4b69e75..1587db9 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -144,7 +144,7 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(struct device *dev) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 84d5e32..db3fff7 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -448,7 +448,7 @@ Device (EC0) #endif #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT - #include "keyboard_backlight.asl" + #include "keyboard_backlight.asl" #endif #ifdef EC_ENABLE_PD_MCU_DEVICE diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 085492d..4f8d203 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -27,13 +27,13 @@ Device(EC) Field (ERAM, ByteAcc, NoLock, Preserve) { Offset (0x02), - DKR1, 1, /* Dock register 1 */ + DKR1, 1, /* Dock register 1 */ Offset (0x05), HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ Offset (0x1a), - DKR2, 1, /* Dock register 2 */ + DKR2, 1, /* Dock register 2 */ Offset (0x2a), EVNT, 8, /* write will trigger EC event */ Offset (0x3a), @@ -56,7 +56,7 @@ Device(EC) PAGE, 8, /* Information Page Selector */ Offset (0xfe), , 4, - DKR3, 1 /* Dock register 3 */ + DKR3, 1 /* Dock register 3 */ } Method (_CRS, 0) @@ -140,186 +140,186 @@ Device(EC) Store(0x50, EVNT) } - Method(_Q2A, 0, NotSerialized) - { - Notify(^LID, 0x80) - } + Method(_Q2A, 0, NotSerialized) + { + Notify(^LID, 0x80) + } - Method(_Q2B, 0, NotSerialized) - { - Notify(^LID, 0x80) - } + Method(_Q2B, 0, NotSerialized) + { + Notify(^LID, 0x80) + } - /* IBM proprietary buttons. */ + /* IBM proprietary buttons. */ - Method (_Q10, 0, NotSerialized) - { + Method (_Q10, 0, NotSerialized) + { ^HKEY.RHK (0x01) - } + } - Method (_Q11, 0, NotSerialized) - { + Method (_Q11, 0, NotSerialized) + { ^HKEY.RHK (0x02) - } + } - Method (_Q12, 0, NotSerialized) - { + Method (_Q12, 0, NotSerialized) + { ^HKEY.RHK (0x03) - } + } - Method (_Q64, 0, NotSerialized) - { + Method (_Q64, 0, NotSerialized) + { ^HKEY.RHK (0x05) - } + } - Method (_Q65, 0, NotSerialized) - { + Method (_Q65, 0, NotSerialized) + { ^HKEY.RHK (0x06) - } + } - Method (_Q17, 0, NotSerialized) - { + Method (_Q17, 0, NotSerialized) + { ^HKEY.RHK (0x08) - } + } - Method (_Q66, 0, NotSerialized) - { + Method (_Q66, 0, NotSerialized) + { ^HKEY.RHK (0x0A) - } + } - Method (_Q6A, 0, NotSerialized) - { + Method (_Q6A, 0, NotSerialized) + { ^HKEY.RHK (0x1B) - } + } - Method (_Q1A, 0, NotSerialized) - { + Method (_Q1A, 0, NotSerialized) + { ^HKEY.RHK (0x0B) - } + } - Method (_Q1B, 0, NotSerialized) - { + Method (_Q1B, 0, NotSerialized) + { ^HKEY.RHK (0x0C) - } + } - Method (_Q62, 0, NotSerialized) - { + Method (_Q62, 0, NotSerialized) + { ^HKEY.RHK (0x0D) - } + } - Method (_Q60, 0, NotSerialized) - { + Method (_Q60, 0, NotSerialized) + { ^HKEY.RHK (0x0E) - } + } - Method (_Q61, 0, NotSerialized) - { + Method (_Q61, 0, NotSerialized) + { ^HKEY.RHK (0x0F) - } + } - Method (_Q1F, 0, NotSerialized) - { + Method (_Q1F, 0, NotSerialized) + { ^HKEY.RHK (0x12) - } + } - Method (_Q67, 0, NotSerialized) - { + Method (_Q67, 0, NotSerialized) + { ^HKEY.RHK (0x13) - } + } - Method (_Q63, 0, NotSerialized) - { + Method (_Q63, 0, NotSerialized) + { ^HKEY.RHK (0x14) - } + } - Method (_Q19, 0, NotSerialized) - { + Method (_Q19, 0, NotSerialized) + { ^HKEY.RHK (0x18) - } + } - Method (_Q1C, 0, NotSerialized) - { + Method (_Q1C, 0, NotSerialized) + { ^HKEY.RHK (0x19) - } + } - Method (_Q1D, 0, NotSerialized) - { + Method (_Q1D, 0, NotSerialized) + { ^HKEY.RHK (0x1A) - } + } - Method (_Q5C, 0, NotSerialized) - { + Method (_Q5C, 0, NotSerialized) + { ^HKEY.RTAB (0xB) - } + } - Method (_Q5D, 0, NotSerialized) - { + Method (_Q5D, 0, NotSerialized) + { ^HKEY.RTAB (0xC) - } + } - Method (_Q5E, 0, NotSerialized) - { + Method (_Q5E, 0, NotSerialized) + { ^HKEY.RTAB (0x9) - } + } - Method (_Q5F, 0, NotSerialized) - { + Method (_Q5F, 0, NotSerialized) + { ^HKEY.RTAB (0xA) - } - - Device (HKEY) - { - Name (_HID, EisaId ("IBM0068")) - Name (BTN, 0) - Name (BTAB, 0) - /* MASK */ - Name (DHKN, 0x080C) - /* Effective Mask */ - Name (EMSK, 0) - /* Effective Mask for tablet */ - Name (ETAB, 0) - /* Device enabled. */ - Name (EN, 0) - Method (_STA, 0, NotSerialized) - { + } + + Device (HKEY) + { + Name (_HID, EisaId ("IBM0068")) + Name (BTN, 0) + Name (BTAB, 0) + /* MASK */ + Name (DHKN, 0x080C) + /* Effective Mask */ + Name (EMSK, 0) + /* Effective Mask for tablet */ + Name (ETAB, 0) + /* Device enabled. */ + Name (EN, 0) + Method (_STA, 0, NotSerialized) + { Return (0x0F) - } - /* Retrieve event. */ - Method (MHKP, 0, NotSerialized) - { + } + /* Retrieve event. */ + Method (MHKP, 0, NotSerialized) + { Store (BTN, Local0) If (LNotEqual (Local0, Zero)) { - Store (Zero, BTN) - Add (Local0, 0x1000, Local0) - Return (Local0) + Store (Zero, BTN) + Add (Local0, 0x1000, Local0) + Return (Local0) } Store (BTAB, Local0) If (LNotEqual (Local0, Zero)) { - Store (Zero, BTAB) - Add (Local0, 0x5000, Local0) - Return (Local0) + Store (Zero, BTAB) + Add (Local0, 0x5000, Local0) + Return (Local0) } Return (Zero) - } - /* Report event */ - Method (RHK, 1, NotSerialized) { + } + /* Report event */ + Method (RHK, 1, NotSerialized) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (And (EMSK, Local0)) { Store (Arg0, BTN) Notify (HKEY, 0x80) } - } - /* Report tablet */ - Method (RTAB, 1, NotSerialized) { + } + /* Report tablet */ + Method (RTAB, 1, NotSerialized) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (And (ETAB, Local0)) { Store (Arg0, BTAB) Notify (HKEY, 0x80) } - } - /* Enable/disable all events. */ - Method (MHKC, 1, NotSerialized) { + } + /* Enable/disable all events. */ + Method (MHKC, 1, NotSerialized) { If (Arg0) { Store (DHKN, EMSK) Store (Ones, ETAB) @@ -330,9 +330,9 @@ Device(EC) Store (Zero, ETAB) } Store (Arg0, EN) - } - /* Enable/disable event. */ - Method (MHKM, 2, NotSerialized) { + } + /* Enable/disable event. */ + Method (MHKM, 2, NotSerialized) { If (LLessEqual (Arg0, 0x20)) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (Arg1) @@ -348,18 +348,18 @@ Device(EC) Store (DHKN, EMSK) } } - } - /* Mask hotkey all. */ - Method (MHKA, 0, NotSerialized) - { + } + /* Mask hotkey all. */ + Method (MHKA, 0, NotSerialized) + { Return (0x07FFFFFF) - } - /* Version */ - Method (MHKV, 0, NotSerialized) - { + } + /* Version */ + Method (MHKV, 0, NotSerialized) + { Return (0x0100) - } - } + } + } #include "ac.asl" #include "battery.asl" diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index 10c5a98..a8e17cb 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -16,7 +16,7 @@ Field(ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x32), + Offset (0x32), , 2, WKLD, 1, Offset (0x46), diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl index 0517992..2f36c4b 100644 --- a/src/ec/lenovo/h8/acpi/sleepbutton.asl +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -25,7 +25,7 @@ Field(ERAM, ByteAcc, NoLock, Preserve) Device(SLPB) { - Name (_HID, EisaId ("PNP0C0E")) + Name (_HID, EisaId ("PNP0C0E")) Method(_PRW, 0, NotSerialized) { Return (Package() { 0x18, 0x03 }) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 3a3487d..2e95b69 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -23,11 +23,11 @@ Scope(\_TZ) Multiply(Arg0, 10, Local0) Add (Local0, 2732, Local0) if (LLessEqual(Local0, 2732)) { - Return (3000) + Return (3000) } if (LGreater(Local0, 4012)) { - Return (3000) + Return (3000) } Return (Local0) } @@ -39,10 +39,10 @@ Scope(\_TZ) } Method(_TMP) { #if defined (EC_LENOVO_H8_ME_WORKAROUND) - /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { - Return (C2K(40)) - } + /* Avoid tripping alarm if ME isn't booted at all yet */ + If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + Return (C2K(40)) + } Store (1, MEB1) #endif Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) @@ -61,10 +61,10 @@ Scope(\_TZ) Method(_TMP) { #if defined (EC_LENOVO_H8_ME_WORKAROUND) - /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) { - Return (C2K(40)) - } + /* Avoid tripping alarm if ME isn't booted at all yet */ + If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) { + Return (C2K(40)) + } Store (1, MEB2) #endif Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 5e4aa47..83768b1 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -154,7 +154,7 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(struct device *dev) diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index af0849c..276f9c6 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -167,7 +167,7 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(struct device *dev)

1 0

Patch set updated for coreboot: src/arch: Improve code formatting
by HAOUAS Elyes 05 Sep '16

05 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16434 -gerrit commit 1f9c639cb4e2493ec1a05351405404ab2b546a65 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Sep 3 08:28:48 2016 +0200 src/arch: Improve code formatting Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/arch/arm/armv7/mmu.c | 90 ++++++++++++------------ src/arch/arm/armv7/thread.c | 4 +- src/arch/arm/include/armv7/arch/cpu.h | 6 +- src/arch/arm64/transition_asm.S | 4 +- src/arch/riscv/include/arch/cpu.h | 6 +- src/arch/riscv/include/arch/hlt.h | 2 +- src/arch/x86/acpigen.c | 126 +++++++++++++++++----------------- 7 files changed, 119 insertions(+), 119 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index b1c1aac..6c085e9 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -280,53 +280,53 @@ void mmu_init(void) for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES) table[0] = ATTR_UNUSED; - if (CONFIG_ARM_LPAE) { - pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB); - pte_t *pmd = ttb_buff; - int i; + if (CONFIG_ARM_LPAE) { + pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB); + pte_t *pmd = ttb_buff; + int i; - printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", + printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", ttb_buff); - ASSERT((read_mmfr0() & 0xf) >= 5); - - /* - * Set MAIR - * See B4.1.104 of ARMv7 Architecture Reference Manual - */ - write_mair0( - 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered, - * Non-Cacheable */ - 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru, - * Read-Allocate */ - 0xff << (MAIR_INDX_WB*8) /* Write-Back, - * Read/Write-Allocate */ - ); - - /* - * Set up L1 table - * Once set here, L1 table won't be modified by coreboot. - * See B3.6.1 of ARMv7 Architecture Reference Manual - */ - for (i = 0; i < 4; i++) { - pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | - ATTR_NEXTLEVEL; - pmd += BLOCK_SIZE / PAGE_SIZE; - } - - /* - * Set TTBR0 - */ - write_ttbr0((uintptr_t)pgd_buff); - } else { - printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff); - - /* - * Translation table base 0 address is in bits 31:14-N, where N - * is given by bits 2:0 in TTBCR (which we set to 0). All lower - * bits in this register should be zero for coreboot. - */ - write_ttbr0((uintptr_t)ttb_buff); - } + ASSERT((read_mmfr0() & 0xf) >= 5); + + /* + * Set MAIR + * See B4.1.104 of ARMv7 Architecture Reference Manual + */ + write_mair0( + 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered, + * Non-Cacheable */ + 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru, + * Read-Allocate */ + 0xff << (MAIR_INDX_WB*8) /* Write-Back, + * Read/Write-Allocate */ + ); + + /* + * Set up L1 table + * Once set here, L1 table won't be modified by coreboot. + * See B3.6.1 of ARMv7 Architecture Reference Manual + */ + for (i = 0; i < 4; i++) { + pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | + ATTR_NEXTLEVEL; + pmd += BLOCK_SIZE / PAGE_SIZE; + } + + /* + * Set TTBR0 + */ + write_ttbr0((uintptr_t)pgd_buff); + } else { + printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff); + + /* + * Translation table base 0 address is in bits 31:14-N, where N + * is given by bits 2:0 in TTBCR (which we set to 0). All lower + * bits in this register should be zero for coreboot. + */ + write_ttbr0((uintptr_t)ttb_buff); + } /* * Set TTBCR diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index 53ca2b3..a3b1d0c 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -55,7 +55,7 @@ void arch_prepare_thread(struct thread *t, * hunting for (e.g.) misaligned stacks or other such * weirdness. The -1 is because we already pushed lr. */ - for (i = 0; i < sizeof(struct pushed_regs)/sizeof(u32)-1; i++) + for (i = 0; i < sizeof(struct pushed_regs) / sizeof(u32) - 1; i++) stack = push_stack(stack, poison++); t->stack_current = stack; @@ -103,7 +103,7 @@ switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack) * | R4 | <-- sp + 0x00 * +------------+ */ - asm volatile ( + asm volatile ( /* save context. */ "push {r4-r11,lr}\n\t" /* Save the current stack */ diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 73ae89f..d70622f 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -39,9 +39,9 @@ struct cpu_info { }; struct cpuinfo_arm { - uint8_t arm; /* CPU family */ - uint8_t arm_vendor; /* CPU vendor */ - uint8_t arm_model; + uint8_t arm; /* CPU family */ + uint8_t arm_vendor; /* CPU vendor */ + uint8_t arm_model; }; #endif diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 8fd629a..8e61246 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -124,8 +124,8 @@ ENDPROC(exc_prologue) * x0 = regs structure */ ENTRY(trans_switch) - msr SPSel, #SPSR_USE_L - b exc_exit + msr SPSel, #SPSR_USE_L + b exc_exit ENDPROC(trans_switch) /* diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 7e8ec63..bc7b196 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -37,9 +37,9 @@ struct cpu_info { }; struct cpuinfo_riscv { - uint8_t riscv; /* CPU family */ - uint8_t riscv_vendor; /* CPU vendor */ - uint8_t riscv_model; + uint8_t riscv; /* CPU family */ + uint8_t riscv_vendor; /* CPU vendor */ + uint8_t riscv_model; }; #endif diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h index de2f25c..da02778 100644 --- a/src/arch/riscv/include/arch/hlt.h +++ b/src/arch/riscv/include/arch/hlt.h @@ -13,5 +13,5 @@ static inline __attribute__((always_inline)) void hlt(void) { - while(1); + while (1); } diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 6b9c091..c55611b 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -339,8 +339,8 @@ void acpigen_write_scope(const char *name) void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* - Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) - { + Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) + { */ char pscope[16]; /* processor op */ @@ -359,26 +359,26 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) void acpigen_write_empty_PCT(void) { /* - Name (_PCT, Package (0x02) - { - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - }, - - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - } - }) + Name (_PCT, Package (0x02) + { + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } + }) */ static char stream[] = { 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */ @@ -395,26 +395,26 @@ void acpigen_write_empty_PCT(void) void acpigen_write_empty_PTC(void) { /* - Name (_PTC, Package (0x02) - { - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - }, - - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - } - }) + Name (_PTC, Package (0x02) + { + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } + }) */ acpi_addr_t addr = { .space_id = ACPI_ADDRESS_SPACE_FIXED, @@ -478,10 +478,10 @@ void acpigen_write_STA(uint8_t status) void acpigen_write_PPC(u8 nr) { /* - Method (_PPC, 0, NotSerialized) - { - Return (nr) - } + Method (_PPC, 0, NotSerialized) + { + Return (nr) + } */ acpigen_write_method("_PPC", 0); /* return */ @@ -498,10 +498,10 @@ void acpigen_write_PPC(u8 nr) void acpigen_write_PPC_NVS(void) { /* - Method (_PPC, 0, NotSerialized) - { - Return (PPCM) - } + Method (_PPC, 0, NotSerialized) + { + Return (PPCM) + } */ acpigen_write_method("_PPC", 0); /* return */ @@ -514,12 +514,12 @@ void acpigen_write_PPC_NVS(void) void acpigen_write_TPC(const char *gnvs_tpc_limit) { /* - // Sample _TPC method - Method (_TPC, 0, NotSerialized) - { - Return (\TLVL) - } - */ + // Sample _TPC method + Method (_TPC, 0, NotSerialized) + { + Return (\TLVL) + } +*/ acpigen_write_method("_TPC", 0); acpigen_emit_byte(0xa4); /* ReturnOp */ acpigen_emit_namestring(gnvs_tpc_limit); @@ -611,13 +611,13 @@ void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u3 void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) { /* - Sample _TSS package with 100% and 50% duty cycles - Name (_TSS, Package (0x02) - { - Package(){100, 1000, 0, 0x00, 0) - Package(){50, 520, 0, 0x18, 0) - }) - */ + Sample _TSS package with 100% and 50% duty cycles + Name (_TSS, Package (0x02) + { + Package(){100, 1000, 0, 0x00, 0) + Package(){50, 520, 0, 0x18, 0) + }) +*/ int i; acpi_tstate_t *tstate = tstate_list;

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Patch set updated for coreboot: commonlib: move DIV_ROUND macros from nvidia/tegra
by Arthur Heymans 05 Sep '16

05 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16415 -gerrit commit 08032ee6eddcd0fe8b8ae09ce71fea90668d7136 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 23:14:54 2016 +0200 commonlib: move DIV_ROUND macros from nvidia/tegra DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other architectures. This patch moves them from soc/nvidia/tegra/types.h to commonlib/include/commonlib/helpers.h . Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/commonlib/include/commonlib/helpers.h | 16 ++++++++++++++++ src/soc/nvidia/tegra/types.h | 18 ------------------ src/soc/nvidia/tegra210/addressmap.c | 1 + src/soc/nvidia/tegra210/dsi.c | 1 + 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index 0318e44..1be1fbb 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -34,6 +34,22 @@ #define ABS(a) (((a) < 0) ? (-(a)) : (a)) #define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) +#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) +/* + * Divide positive or negative dividend by positive divisor and round + * to closest integer. Result is undefined for negative divisors and + * for negative dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) /* Standard units. */ #define KiB (1<<10) diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h index dab474d..bfeebae 100644 --- a/src/soc/nvidia/tegra/types.h +++ b/src/soc/nvidia/tegra/types.h @@ -51,22 +51,4 @@ (type *)( (char *)__mptr - offsetof(type,member) );}) #endif -#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) - -/* - * Divide positive or negative dividend by positive divisor and round - * to closest integer. Result is undefined for negative divisors and - * for negative dividends if the divisor variable type is unsigned. - */ -#define DIV_ROUND_CLOSEST(x, divisor)( \ -{ \ - typeof(x) __x = x; \ - typeof(divisor) __d = divisor; \ - (((typeof(x))-1) > 0 || \ - ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ - (((__x) + ((__d) / 2)) / (__d)) : \ - (((__x) - ((__d) / 2)) / (__d)); \ -} \ -) - #endif /* __TEGRA_MISC_TYPES_H__ */ diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index e803e1b..18bb081 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -15,6 +15,7 @@ #include <assert.h> #include <arch/io.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/id.h> diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 3b771c9..5504b4d 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -32,6 +32,7 @@ #include <soc/tegra_dsi.h> #include <soc/mipi-phy.h> #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" +#include <commonlib/helpers.h> struct tegra_mipi_device mipi_device_data[NUM_DSI];

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Patch merged into coreboot/master: src/include: Improve code formatting
by gerrit＠coreboot.org 05 Sep '16

05 Sep '16

the following patch was just integrated into master: commit 8ffd050cf0ecfbeb647cf985c60f67c24faab181 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 1 19:01:41 2016 +0200 src/include: Improve code formatting Change-Id: Ic8ffd26e61c0c3f27872699bb6aa9c39204155b7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16390 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16390 for details. -gerrit

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coreboot-gerrit September 2016