coreboot-gerrit August 2016

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Patch set updated for coreboot: soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
by Ravishankar Sarawadi 17 Aug '16

17 Aug '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16238 -gerrit commit 9ee0c937c83b00cbf94dfd7fe0b9522b1ef8efb5 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Tue Aug 16 16:55:02 2016 -0700 soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB Read FSP produced memory HOB and use it to populate DIMM info. DIMM 'part_num' info is stored statically based on memory/SKU id. BUG = chrome-os-partner:55505 Test = 'dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: I7fa4fe6f99d4b3d68aaf10245af8484f7051aa25 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 14 ++- src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/mainboard/google/reef/romstage.c | 111 +++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/meminit.h | 1 + src/soc/intel/apollolake/include/soc/romstage.h | 1 + src/soc/intel/apollolake/romstage.c | 8 ++ 6 files changed, 131 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 0dd4a52..17adf46 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -45,8 +45,13 @@ const uint8_t fsp_reserved_memory_guid[16] = { }; const uint8_t fsp_nv_storage_guid[16] = { - 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c, - 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 + 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c, + 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 +}; + +const uint8_t smbios_memory_info_guid[16] = { + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 }; /* @@ -218,3 +223,8 @@ const void *fsp_find_nv_storage_data(size_t *size) { return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); } + +const void *fsp_find_smbios_memory_info(size_t *size) +{ + return fsp_find_extension_hob_by_guid(smbios_memory_info_guid, size); +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ba465ea..269bb02 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -61,6 +61,7 @@ const void *fsp_get_hob_list(void); void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); +const void *fsp_find_smbios_memory_info(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); int fsp_find_reserved_memory(struct range_entry *re); diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index f9743b5..e9a2bfc 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,9 +13,16 @@ * GNU General Public License for more details. */ +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> #include <gpio.h> +#include <memory_info.h> +#include <smbios.h> +#include <soc/fsp/FspmUpd.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include <string.h> #include "gpio.h" static const struct lpddr4_swizzle_cfg board_swizzle = { @@ -82,12 +89,14 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", }, /* K4F8E304HB-MGCJ - both logical channels */ [1] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", }, /* * MT53B512M32D2NP-062WT:C - both logical channels. While the parts @@ -100,18 +109,21 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCH", }, }; @@ -121,9 +133,8 @@ static const struct lpddr4_cfg lp4cfg = { .swizzle_config = &board_swizzle, }; -void mainboard_memory_init_params(struct FSPM_UPD *memupd) +static int get_mem_sku(void) { - int mem_sku; gpio_t pads[] = { [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, @@ -133,7 +144,101 @@ void mainboard_memory_init_params(struct FSPM_UPD *memupd) * Read memory SKU id with internal pullups enabled to handle * proto boards with no SKU id pins. */ - mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +} + +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + int mem_sku = get_mem_sku(); meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); } + +void mainboard_save_dimm_info(void) +{ + int channel, dimm, dimm_max, index, mem_sku; + size_t hob_size; + struct DIMM_INFO *dimm_info; + struct memory_info *mem_info; + struct CHANNEL_INFO *channel_info; + struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + mem_sku = get_mem_sku(); + if (mem_sku >= lp4cfg.num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + mem_sku, lp4cfg.num_skus); + return; + } + + memory_info_hob = (struct FSP_SMBIOS_MEMORY_INFO *) + fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &memory_info_hob->ChannelInfo[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + dimm_info = &channel_info->DimmInfo[dimm]; + + /* Populate the DIMM information */ + if (dimm_info->SizeInMb) { + mem_info->dimm[index].dimm_size = + dimm_info->SizeInMb; + mem_info->dimm[index].ddr_type = + memory_info_hob->MemoryType; + mem_info->dimm[index].ddr_frequency = + memory_info_hob->MemoryFrequencyInMHz; + mem_info->dimm[index].channel_num = + channel_info->ChannelId; + mem_info->dimm[index].dimm_num = + dimm_info->DimmId; + memcpy(mem_info->dimm[index].module_part_number, + lp4cfg.skus[mem_sku].part_num, + sizeof(mem_info->dimm[index].module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_8; + break; + + case 16: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_16; + break; + + case 32: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_32; + break; + + case 64: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_64; + break; + + case 128: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_128; + break; + + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index a7da1ac..037e7f4 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -101,6 +101,7 @@ struct lpddr4_sku { int ch1_rank_density; int ch0_dual_rank; int ch1_dual_rank; + const char *part_num; }; struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index e7ee335..5b76f65 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -22,5 +22,6 @@ #include <fsp/api.h> void mainboard_memory_init_params(struct FSPM_UPD *mupd); +void mainboard_save_dimm_info(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8f17fdd..d631192 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -118,6 +118,8 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + mainboard_save_dimm_info(); + /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache @@ -169,6 +171,12 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } +__attribute__ ((weak)) +void mainboard_save_dimm_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + int get_sw_write_protect_state(void) { uint8_t status;

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add NVM driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16161 -gerrit commit 755b8c160fa246ded52d8588d47d4da9a2814dc1 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:54:38 2016 -0700 soc/marvell/mvmap2315: Add NVM driver This driver uses BootROM callback to read and write to the nvm using I2C. Testing: booted successfully. Change-Id: I8639af3e004f6631d7e596507c106159835f979f Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/include/soc/nvm.h | 25 +++++++ src/soc/marvell/mvmap2315/nvm.c | 105 ++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 0d1ef2b..e16286b 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -27,6 +27,7 @@ bootblock-y += gpio.c bootblock-y += flash.c bootblock-y += load_validate.c bootblock-y += media.c +bootblock-y += nvm.c bootblock-y += pinmux.c bootblock-y += pmic.c bootblock-y += reset.c diff --git a/src/soc/marvell/mvmap2315/include/soc/nvm.h b/src/soc/marvell/mvmap2315/include/soc/nvm.h new file mode 100644 index 0000000..ede0d97 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/nvm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_NVM_H__ +#define __SOC_MARVELL_MVMAP2315_NVM_H__ + +#define MVMAP2315_NVM_LOCKDOWN_FLAG BIT(0) + +u32 nvm_init(void); +u32 nvm_read(u32 offset, u32 *buffer, u32 size); +u32 nvm_write(u32 offset, u32 *buffer, u32 size); +void nvm_lockdown(void); + +#endif /* __SOC_MARVELL_MVMAP2315_NVM_H__ */ diff --git a/src/soc/marvell/mvmap2315/nvm.c b/src/soc/marvell/mvmap2315/nvm.c new file mode 100644 index 0000000..7e33e98 --- /dev/null +++ b/src/soc/marvell/mvmap2315/nvm.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/bdb.h> +#include <soc/clock.h> +#include <soc/flash.h> +#include <soc/load_validate.h> +#include <soc/nvm.h> + +struct flash_ops nvm_callbacks = { + .init = (void *)MVMAP2315_FLASH_INIT, + .read = (void *)MVMAP2315_FLASH_READ, + .write = (void *)MVMAP2315_FLASH_WRITE, +}; + +static void set_nvm_parameters(struct flash_params *eeprom_info, u32 offset, + u32 *buffer, u32 size) +{ + eeprom_info->offset = offset; + eeprom_info->buff = (u32)buffer; + eeprom_info->size = size; + eeprom_info->id = 0x0; + eeprom_info->partition = 0x0; +} + +u32 nvm_init(void) +{ + int rc; + + clrbits_le32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, + MVMAP2315_SDMMC_CLK_RSTN); + setbits_le32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, + MVMAP2315_SDMMC_CLK_RSTN); + + rc = nvm_callbacks.init(MVMAP2315_EEPROM, 0, 0); + + if (rc) + printk(BIOS_DEBUG, "nvm_init failed with rc=%x.\n", rc); + + return rc; +} + +u32 nvm_read(u32 offset, u32 *buffer, u32 size) +{ + struct flash_params eeprom_read_info; + u32 rc; + + set_nvm_parameters(&eeprom_read_info, offset, buffer, size); + + rc = nvm_init(); + + if (rc) + return rc; + + rc = nvm_callbacks.read(MVMAP2315_EEPROM, 0, &eeprom_read_info); + + if (rc) + printk(BIOS_INFO, "nvm_read callback failed, rc=%x\n", rc); + + return rc; +} + +u32 nvm_write(u32 offset, u32 *buffer, u32 size) +{ + struct flash_params eeprom_read_info; + u32 rc; + + set_nvm_parameters(&eeprom_read_info, offset, buffer, size); + + rc = nvm_init(); + + if (rc) + return rc; + + rc = nvm_callbacks.write(MVMAP2315_EEPROM, 0, &eeprom_read_info); + + if (rc) + printk(BIOS_INFO, "nvm_write callback failed, rc=%x\n", rc); + + return rc; +} + +void nvm_lockdown(void) +{ + setbits_le32(&mvmap2315_mcu_secconfig->boot_hw_lockdown_nvm, + MVMAP2315_NVM_LOCKDOWN_FLAG); +}

1 0

Patch set updated for coreboot: arch/arm: Add armv7-r configuration
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335 -gerrit commit c8d3b4bf51b1db7a0b5d5b64b3c765a52959df7e Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:44:27 2016 -0700 arch/arm: Add armv7-r configuration This change adds armv7-r support for all stages. armv7-r is an ARM processor based on the Cortex-R series. Currently, there is support for armv7-a and armv7-m and armv7-a files has been modfied to accommodate armv7-r by adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants to src/include/rules.h. armv7-r exceptions support will added in a later time. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/arch/arm/armv7/Kconfig | 16 +++++++++++ src/arch/arm/armv7/Makefile.inc | 59 +++++++++++++++++++++++++++++++++++++-- src/arch/arm/armv7/cpu.S | 12 ++++++++ src/arch/arm/armv7/exception_m.c | 36 ------------------------ src/arch/arm/armv7/exception_mr.c | 36 ++++++++++++++++++++++++ src/include/rules.h | 13 +++++++++ util/xcompile/xcompile | 2 +- 7 files changed, 134 insertions(+), 40 deletions(-) diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 0ab3542..3734426 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -19,3 +19,19 @@ config ARCH_BOOTBLOCK_ARMV7_M config ARCH_VERSTAGE_ARMV7_M def_bool n select ARCH_VERSTAGE_ARM + +config ARCH_BOOTBLOCK_ARMV7_R + def_bool n + select ARCH_BOOTBLOCK_ARM + +config ARCH_VERSTAGE_ARMV7_R + def_bool n + select ARCH_VERSTAGE_ARM + +config ARCH_ROMSTAGE_ARMV7_R + def_bool n + select ARCH_ROMSTAGE_ARM + +config ARCH_RAMSTAGE_ARMV7_R + def_bool n + select ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2e9c49c..d978f00 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -16,10 +16,12 @@ ############################################################################### armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 -armv7-a_flags = -march=armv7-a $(armv7_flags) -armv7-m_flags = -march=armv7-m $(armv7_flags) +armv7-a_flags = -march=armv7-a $(armv7_flags) -D__COREBOOT_ARM_V7_A__ +armv7-m_flags = -march=armv7-m $(armv7_flags) -D__COREBOOT_ARM_V7_M__ +armv7-r_flags = -march=armv7-r $(armv7_flags) -D__COREBOOT_ARM_V7_R__ armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated +armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags) ############################################################################### # bootblock @@ -46,9 +48,22 @@ bootblock-S-ccopts += $(armv7_asm_flags) ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock_m.S endif -bootblock-y += exception_m.c +bootblock-y += exception_mr.c bootblock-y += cache_m.c +else ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV7_R),y) +bootblock-generic-ccopts += $(armv7-r_flags) +bootblock-S-ccopts += $(armv7-r_asm_flags) + +ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) +bootblock-y += bootblock.S +endif + +bootblock-y += cache.c +bootblock-y += cpu.S +bootblock-y += exception_mr.c +bootblock-y += mmu.c + endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 ################################################################################ @@ -73,6 +88,17 @@ libverstage-S-ccopts += $(armv7_asm_flags) verstage-generic-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y) +libverstage-generic-ccopts += $(armv7-r_flags) +libverstage-S-ccopts += $(armv7-r_asm_flags) +verstage-generic-ccopts += $(armv7-r_flags) +verstage-S-ccopts += $(armv7-r_asm_flags) + +verstage-y += cache.c +verstage-y += cpu.S +verstage-y += exception_mr.c +verstage-y += mmu.c + endif # CONFIG_ARCH_VERSTAGE_ARMV7_M ################################################################################ @@ -91,6 +117,18 @@ romstage-S-ccopts += $(armv7_asm_flags) rmodules_arm-generic-ccopts += $(armv7-a_flags) rmodules_arm-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y) +romstage-y += cache.c +romstage-y += cpu.S +romstage-y += exception_mr.c +romstage-y += mmu.c + +romstage-generic-ccopts += $(armv7-r_flags) +romstage-S-ccopts += $(armv7-r_asm_flags) + +rmodules_arm-generic-ccopts += $(armv7-r_flags) +rmodules_arm-S-ccopts += $(armv7-r_asm_flags) + endif # CONFIG_ARCH_ROMSTAGE_ARMV7 ############################################################################### @@ -111,4 +149,19 @@ ramstage-S-ccopts += $(armv7_asm_flags) # All rmodule code is armv7 if ramstage is armv7. rmodules_arm-generic-ccopts += $(armv7-a_flags) rmodules_arm-S-ccopts += $(armv7_asm_flags) + +else ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7_R),y) + +ramstage-y += cache.c +ramstage-y += cpu.S +ramstage-y += exception_mr.c +ramstage-y += mmu.c + +ramstage-generic-ccopts += $(armv7-r_flags) +ramstage-S-ccopts += $(armv7-r_asm_flags) + +# All rmodule code is armv7 if ramstage is armv7. +rmodules_arm-generic-ccopts += $(armv7-r_flags) +rmodules_arm-S-ccopts += $(armv7-r_asm_flags) + endif # CONFIG_ARCH_RAMSTAGE_ARMV7 diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 6c00f62..21a16d2 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -31,6 +31,7 @@ */ #include <arch/asm.h> +#include <rules.h> /* * Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0] @@ -126,6 +127,7 @@ ENTRY(arm_init_caches) /* Flush and invalidate dcache in ascending order */ bl dcache_invalidate_all +#if ENV_ARMV7_A /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ and r4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) mcr p15, 0, r4, c1, c0, 0 @@ -133,6 +135,16 @@ ENTRY(arm_init_caches) /* Invalidate icache and TLB for good measure */ mcr p15, 0, r0, c7, c5, 0 mcr p15, 0, r0, c8, c7, 0 +#endif + +#if ENV_ARMV7_R + /* Deactivate Alignment Check (1) and DCache (2) */ + and r4, # ~(1 << 1) & ~(1 << 2) + mcr p15, 0, r4, c1, c0, 0 + + /* Invalidate icache for good measure */ + mcr p15, 0, r0, c7, c5, 0 +#endif dsb isb diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c deleted file mode 100644 index d76cc6a..0000000 --- a/src/arch/arm/armv7/exception_m.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/exception.h> -#include <console/console.h> - -void exception_init(void) -{ - printk(BIOS_DEBUG, "Exception handlers not installed.\n"); -} diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c new file mode 100644 index 0000000..d76cc6a --- /dev/null +++ b/src/arch/arm/armv7/exception_mr.c @@ -0,0 +1,36 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/exception.h> +#include <console/console.h> + +void exception_init(void) +{ + printk(BIOS_DEBUG, "Exception handlers not installed.\n"); +} diff --git a/src/include/rules.h b/src/include/rules.h index 89fdd21..a632804 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -131,6 +131,19 @@ #elif __COREBOOT_ARM_ARCH__ == 7 #define ENV_ARMV4 0 #define ENV_ARMV7 1 +#if defined(__COREBOOT_ARM_V7_A__) +#define ENV_ARMV7_A 1 +#define ENV_ARMV7_M 0 +#define ENV_ARMV7_R 0 +#elif defined(__COREBOOT_ARM_V7_M__) +#define ENV_ARMV7_A 0 +#define ENV_ARMV7_M 1 +#define ENV_ARMV7_R 0 +#elif defined(__COREBOOT_ARM_V7_R__) +#define ENV_ARMV7_A 0 +#define ENV_ARMV7_M 0 +#define ENV_ARMV7_R 1 +#endif #else #define ENV_ARMV4 0 #define ENV_ARMV7 0 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 6c75da6..37e6404 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -316,7 +316,7 @@ arch_config_arm() { TBFDARCHS="littlearm" TCLIST="armv7-a armv7a arm" TWIDTH="32" - TSUPP="arm armv4 armv7 armv7_m" + TSUPP="arm armv4 armv7 armv7_m armv7_r" TABI="eabi" }

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add APMU driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15518 -gerrit commit c35d06d761db17f1a812e9ffd2c6653f31f94b5e Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:53:04 2016 -0700 soc/marvell/mvmap2315: Add APMU driver APMU is the AP power management unit. It is a separate processor that handles enabling individual power rails. This driver handles sending and receiving commands from/to APMU. Testing: booted successfully. Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/apmu.c | 131 ++++++++ src/soc/marvell/mvmap2315/bootblock.c | 3 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/apmu.h | 368 +++++++++++++++++++++ 5 files changed, 505 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 85c526e..69733bf 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOC_MARVELL_MVMAP2315),y) +bootblock-y += apmu.c bootblock-y += bootblock.c bootblock-y += bdb.c bootblock-y += clock.c diff --git a/src/soc/marvell/mvmap2315/apmu.c b/src/soc/marvell/mvmap2315/apmu.c new file mode 100644 index 0000000..d6cbc7f --- /dev/null +++ b/src/soc/marvell/mvmap2315/apmu.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/apmu.h> +#include <soc/clock.h> + +void apmu_start(void) +{ + u32 reg; + + printk(BIOS_DEBUG, "APMU init...\n"); + + /* TODO: remove in real silicon */ + write32(&mvmap2315_apmu_pwrctl->scratch0, 0x900dc0de); + + /* Dedicate LCM area to the APMU */ + reg = MVMAP2315_LCM_START_BANK | + MVMAP2315_LCM_END_BANK | + MVMAP2315_LCM_DIRACCESS_EN; + write32(&mvmap2315_lcm_regs->lcm_access, reg); + + /* Taking APMU out of reset */ + setbits_le32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig, + MVMAP2315_APMU_CLK_EN); + + setbits_le32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig, + MVMAP2315_APMU_CLK_RSTN); +} + +static int apmu_sending_cmd(u32 cmd) +{ + int success; + u32 timeout = 0; + + printk(BIOS_DEBUG, "sending cmd: %x\n", cmd); + + /* Send a sync command */ + write32(&mvmap2315_apmu_pwrctl->pwrcmdfifo, + cmd | MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ); + + while (!(read32(&mvmap2315_apmu_pwrctl->intstatus) & + (MVMAP2315_APMU_ISTCLR_DONE | + MVMAP2315_APMU_ISTCLR_ERROR)) && + (timeout < MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT)) + timeout++; + + if (timeout >= MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT) { + printk(BIOS_DEBUG, "cmd Timed out\n"); + success = -2; + } + + if (read32(&mvmap2315_apmu_pwrctl->intstatus) & + MVMAP2315_APMU_ISTCLR_DONE) { + printk(BIOS_DEBUG, "Completed cmd: %x\n", + read32(&mvmap2315_apmu_pwrctl->doneirq)); + + setbits_le32(&mvmap2315_apmu_pwrctl->intstatusclear, + MVMAP2315_APMU_ISTCLR_DONE); + success = 0; + + } else if (read32(&mvmap2315_apmu_pwrctl->intstatus) & + MVMAP2315_APMU_ISTCLR_ERROR) { + printk(BIOS_DEBUG, "Error cmd: %x\n", + read32(&mvmap2315_apmu_pwrctl->errorirq)); + + setbits_le32(&mvmap2315_apmu_pwrctl->intstatusclear, + MVMAP2315_APMU_ISTCLR_ERROR); + + success = -1; + } + + return success; +} + +int apmu_set_dev(u32 dev, u32 state) +{ + u32 cmd; + + cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + cmd |= MVMAP2315_APMU_OPCODE_PWRST << MVMAP2315_APMU_OPCODE_SHIFT; + cmd |= state << MVMAP2315_APMU_DEV_STATE_SHIFT; + cmd |= dev << MVMAP2315_APMU_DEV_OBJECT_SHIFT; + + return apmu_sending_cmd(cmd); +} + +int apmu_set_pll(u32 dev, u32 state, u32 freq) +{ + u32 cmd; + + cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + cmd |= MVMAP2315_APMU_OPCODE_PWRST << MVMAP2315_APMU_OPCODE_SHIFT; + cmd |= freq << MVMAP2315_APMU_DEV_FREQ_SHIFT; + cmd |= state << MVMAP2315_APMU_DEV_STATE_SHIFT; + cmd |= dev << MVMAP2315_APMU_DEV_OBJECT_SHIFT; + + return apmu_sending_cmd(cmd); +} + + +int apmu_set_clk(u32 clk, u32 state, u32 div, u32 src) +{ + u32 cmd; + + cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + cmd |= MVMAP2315_APMU_OPCODE_CLKST << MVMAP2315_APMU_OPCODE_SHIFT; + cmd |= state << MVMAP2315_APMU_CLK_STATE_SHIFT; + cmd |= div << MVMAP2315_APMU_CLK_DIV_SHIFT; + cmd |= src << MVMAP2315_APMU_CLK_SOURCE_SHIFT; + cmd |= clk << MVMAP2315_APMU_CLK_OBJECT_SHIFT; + + return apmu_sending_cmd(cmd); +} diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index c02d1e5..8ad2eed 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <timestamp.h> #include <console/uart.h> +#include <soc/apmu.h> #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> @@ -46,6 +47,8 @@ void bootblock_soc_init(void) printk(BIOS_DEBUG, "loading and validating APMU firmware.\n"); load_and_validate(&bdb_info, APMU_FIRMWARE); + apmu_start(); + printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); load_and_validate(&bdb_info, MCU_FIRMWARE); diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index fb3b05f..31f895f 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -34,6 +34,8 @@ #define MVMAP2315_GENTIMER_BASE 0xE0137000 #define MVMAP2315_MPMU_CLK_BASE 0xEF000800 #define MVMAP2315_MCU_SECCONFIG_BASE 0xED600000 +#define MVMAP2315_APMU_PWRCTL_BASE 0xE012C000 +#define MVMAP2315_LCM_REGS_BASE 0xE0130000 #define MVMAP2315_RAM_BASE 0x00000000 #define MVMAP2315_DEVICE_BASE 0x80000000 diff --git a/src/soc/marvell/mvmap2315/include/soc/apmu.h b/src/soc/marvell/mvmap2315/include/soc/apmu.h new file mode 100644 index 0000000..b29b061 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/apmu.h @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_APMU_H__ +#define __SOC_MARVELL_MVMAP2315_APMU_H__ + +#include <soc/addressmap.h> +#include <types.h> + +enum pll_t { + CPU_PLL = 93, + MC_PLL = 94, + MCFLC_PLL = 95, + A2_PLL = 96, + MAIN_PLL = 97, + GPU_PLL0 = 98, + GPU_PLL1 = 99, + MIPI_PLL = 100, + DISPLAY_PLL = 101, + APLL0 = 102, +}; + +enum apll_freq_t { + APLL_NOCHANGE = 0, + APLL_589P824 = 1, + APLL_541P9008 = 2, + APLL_451P584 = 3 +}; + +enum dev_statet_t { + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D3WAKEINT = 11 +}; + +enum dev_t { + APCPU_0 = 0, + APCPU_L2 = 4, + A2 = 5, + MC = 6, + DDRPHY_0 = 7, + DDRPHY_1 = 8, + DDRPHY_2 = 9, + DDRPHY_3 = 10, + MCFLC = 11, + SDMMC = 50, + AES256 = 54, + AP_AXI_HS = 55, + AP_UART0 = 56, + AP_UART1 = 57, + AP_M2M = 65, + AP_APB = 66, + AP_GIC = 67, +}; + +enum clk_t { + M4CLK = 124, +}; + +enum clk_src_t { + SRCSEL_NO_CHANGE = 0, + SRCSEL_CPU_PLL = 1, + SRCSEL_MC_PLL = 2, + SRCSEL_MCFLC_PLL = 3, + SRCSEL_A2_PLL = 4, + SRCSEL_MAIN_PLL = 5, + SRCSEL_GPU_PLL0 = 6, + SRCSEL_GPU_PLL1 = 7, + SRCSEL_MIPI_PLL = 8, + SRCSEL_DISPLAY_PLL = 9, + SRCSEL_APLL0 = 10, + SRCSEL_APLL1 = 11, +}; + +enum clk_state_t { + NOCHANGE = 0, + GATED = 1, + RUNNING = 2 +}; + +#define MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT 0x5000 +#define MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ BIT(27) +#define MVMAP2315_APMU_ISTCLR_DONE BIT(30) +#define MVMAP2315_APMU_ISTCLR_ERROR BIT(31) + +#define MVMAP2315_APMU_OPCODE_CLKST 1 +#define MVMAP2315_APMU_OPCODE_PWRST 2 +#define MVMAP2315_APMU_OPCODE_SHIFT 28 + +#define MVMAP2315_APMU_DEV_FREQ_SHIFT 12 +#define MVMAP2315_APMU_DEV_STATE_SHIFT 8 +#define MVMAP2315_APMU_DEV_OBJECT_SHIFT 0 + +#define MVMAP2315_APMU_CLK_STATE_SHIFT 25 +#define MVMAP2315_APMU_CLK_DIV_SHIFT 12 +#define MVMAP2315_APMU_CLK_SOURCE_SHIFT 8 +#define MVMAP2315_APMU_CLK_OBJECT_SHIFT 0 + +struct mvmap2315_apmu_pwrctl_regs { + u32 pwrcmdfifo; + u32 pwrcmdfifostatus; + u8 _reserved0[0x08]; + u32 intstatusset; + u32 intstatusclear; + u32 intstatus; + u8 _reserved1[0x04]; + u32 doneirq; + u32 errorirq; + u32 scratch0; + u32 scratch1; + u8 _reserved2[0x10]; + u32 pmp_spci_rx_int_status; + u32 pmp_spci_rx_int_set; + u32 pmp_spci_rx_int_clear; + u8 _reserved3[0x04]; + u32 pmp_spci_tx_int_status; + u32 pmp_spci_tx_int_set; + u32 pmp_spci_tx_int_clear; + u8 _reserved4[0xa4]; + u32 global_pwrstate; + u8 _reserved5[0x0c]; + u32 a72core0_pwrstate; + u8 _reserved6[0x0c]; + u32 a72core1_pwrstate; + u8 _reserved7[0x0c]; + u32 a72core2_pwrstate; + u8 _reserved8[0x0c]; + u32 a72core3_pwrstate; + u8 _reserved9[0x0c]; + u32 a72l2_pwrstate; + u8 _reserved10[0x0c]; + u32 a2fab_pwrstate; + u8 _reserved11[0x0c]; + u32 mc_pwrstate; + u8 _reserved12[0x0c]; + u32 mc_phy0_pwrstate; + u8 _reserved13[0x0c]; + u32 mc_phy1_pwrstate; + u8 _reserved14[0x0c]; + u32 mc_phy2_pwrstate; + u8 _reserved15[0x0c]; + u32 mc_phy3_pwrstate; + u8 _reserved16[0x0c]; + u32 mcflc_pwrstate; + u8 _reserved17[0x0c]; + u32 mcflc_phy0_pwrstate; + u8 _reserved18[0x0c]; + u32 mcflc_phy1_pwrstate; + u8 _reserved19[0x0c]; + u32 mcflc_phy2_pwrstate; + u8 _reserved20[0x0c]; + u32 mcflc_phy3_pwrstate; + u8 _reserved21[0x0c]; + u32 gpu3dcore0_pwrstate; + u8 _reserved22[0x0c]; + u32 gpu3dcore1_pwrstate; + u8 _reserved23[0x0c]; + u32 gpu3dcore2_pwrstate; + u8 _reserved24[0x0c]; + u32 gpu3dcore3_pwrstate; + u8 _reserved25[0x0c]; + u32 gpu3dl2_pwrstate; + u8 _reserved26[0x0c]; + u32 smmu_pwrstate; + u8 _reserved27[0x0c]; + u32 vpudec_pwrstate; + u8 _reserved28[0x0c]; + u32 jpeg_pwrstate; + u8 _reserved29[0x0c]; + u32 decoder_pwrstate; + u8 _reserved30[0x0c]; + u32 vpuenc_pwrstate; + u8 _reserved31[0x0c]; + u32 vp8_pwrstate; + u8 _reserved32[0x0c]; + u32 vp9_pwrstate; + u8 _reserved33[0x0c]; + u32 zram_pwrstate; + u8 _reserved34[0x0c]; + u32 gpu2d_pwrstate; + u8 _reserved35[0x0c]; + u32 edisplay_pwrstate; + u8 _reserved36[0x0c]; + u32 edp_phy_pwrstate; + u8 _reserved37[0x0c]; + u32 dsi_phy0_pwrstate; + u8 _reserved38[0x0c]; + u32 dsi_phy1_pwrstate; + u8 _reserved39[0x0c]; + u32 display_pwrstate; + u8 _reserved40[0x0c]; + u32 mci_x40_pwrstate; + u8 _reserved41[0x0c]; + u32 mci_x4_phy0_pwrstate; + u8 _reserved42[0x0c]; + u32 mci_x41_pwrstate; + u8 _reserved43[0x0c]; + u32 mci_x4_phy1_pwrstate; + u8 _reserved44[0x0c]; + u32 mci_x42_pwrstate; + u8 _reserved45[0x0c]; + u32 mci_x4_phy2_pwrstate; + u8 _reserved46[0x0c]; + u32 mci_x2_pwrstate; + u8 _reserved47[0x0c]; + u32 mci_x2_phy_pwrstate; + u8 _reserved48[0x0c]; + u32 mci_x10_pwrstate; + u8 _reserved49[0x0c]; + u32 mci_x1_phy0_pwrstate; + u8 _reserved50[0x0c]; + u32 mci_x11_pwrstate; + u8 _reserved51[0x0c]; + u32 mci_x1_phy1_pwrstate; + u8 _reserved52[0x0c]; + u32 mci_x12_pwrstate; + u8 _reserved53[0x0c]; + u32 mci_x1_phy2_pwrstate; + u8 _reserved54[0x0c]; + u32 mci_x13_pwrstate; + u8 _reserved55[0x0c]; + u32 mci_x1_phy3_pwrstate; + u8 _reserved56[0x2c]; + u32 sdmmc_pwrstate; + u8 _reserved57[0x0c]; + u32 emmc_phy_pwrstate; + u8 _reserved58[0x0c]; + u32 sdio_phy0_pwrstate; + u8 _reserved59[0x0c]; + u32 sdio_phy1_pwrstate; + u8 _reserved60[0x0c]; + u32 aes256_pwrstate; + u8 _reserved61[0x0c]; + u32 ap_axi_pwrstate; + u8 _reserved62[0x1c]; + u32 ap_uart0_pwrstate; + u8 _reserved63[0x0c]; + u32 ap_uart1_pwrstate; + u8 _reserved64[0x0c]; + u32 ap_ssp0_pwrstate; + u8 _reserved65[0x0c]; + u32 ap_ssp1_pwrstate; + u8 _reserved66[0x0c]; + u32 ap_i2c0_pwrstate; + u8 _reserved67[0x0c]; + u32 ap_i2c1_pwrstate; + u8 _reserved68[0x0c]; + u32 ap_i2c2_pwrstate; + u8 _reserved69[0x0c]; + u32 ap_i2c3_pwrstate; + u8 _reserved70[0x0c]; + u32 ap_i2c4_pwrstate; + u8 _reserved71[0x0c]; + u32 ap_lcm_pwrstate; + u8 _reserved72[0x0c]; + u32 ap_m2m_pwrstate; + u8 _reserved73[0x0c]; + u32 ap_apb_pwrstate; + u8 _reserved74[0x0c]; + u32 bcm_r4_pwrstate; + u8 _reserved75[0x0c]; + u32 apmu_m4_pwrstate; + u8 _reserved76[0x0c]; + u32 ap_gic_pwrstate; + u8 _reserved77[0x4c]; + u32 cpu_pll_pwrstate; + u8 _reserved78[0x0c]; + u32 mc_pll_pwrstate; + u8 _reserved79[0x0c]; + u32 mcflc_pll_pwrstate; + u8 _reserved80[0x0c]; + u32 a2_pll_pwrstate; + u8 _reserved81[0x0c]; + u32 main_pll_pwrstate; + u8 _reserved82[0x0c]; + u32 gpu_pll0_pwrstate; + u8 _reserved83[0x0c]; + u32 gpu_pll1_pwrstate; + u8 _reserved84[0x0c]; + u32 mipi_pll_pwrstate; + u8 _reserved85[0x0c]; + u32 display_pll_pwrstate; + u8 _reserved86[0x0c]; + u32 avs_vmain_pwrstate; + u8 _reserved87[0x0c]; + u32 avs_vcpu_pwrstate; + u8 _reserved88[0x0c]; + u32 avs_vgpu_pwrstate; + u8 _reserved89[0x0c]; + u32 ap_tsene_pwrstate; + u8 _reserved90[0x0c]; + u32 rng_pwrstate; + u8 _reserved91[0x3c]; + u32 padgroup29_pwrstate; + u8 _reserved92[0x0c]; + u32 padgroup30_pwrstate; + u8 _reserved93[0x0c]; + u32 padgroup31_pwrstate; + u8 _reserved94[0x0c]; + u32 padgroup32_pwrstate; + u8 _reserved95[0x0c]; + u32 padgroup33_pwrstate; +}; + +check_member(mvmap2315_apmu_pwrctl_regs, padgroup33_pwrstate, 0x750); +static struct mvmap2315_apmu_pwrctl_regs * const mvmap2315_apmu_pwrctl + = (void *)MVMAP2315_APMU_PWRCTL_BASE; + +#define MVMAP2315_LCM_DIRACCESS_EN BIT(0) +#define MVMAP2315_LCM_START_BANK BIT(6) +#define MVMAP2315_LCM_END_BANK (BIT(8) | BIT(10)) +struct mvmap2315_lcm_regs { + u32 lcm_scfg; + u32 lcm_access; + u8 _reserved0[0x08]; + u32 lcm_ctrl_bank_mstr_id_wr0; + u32 lcm_ctrl_bank_mstr_id_wr1; + u32 lcm_ctrl_bank_mstr_id_wr2; + u32 lcm_ctrl_bank_mstr_id_wr3; + u32 lcm_ctrl_bank_mstr_id_wr4; + u32 lcm_ctrl_bank_mstr_id_wr5; + u8 _reserved1[0x28]; + u32 lcm_ctrl_bank_mask_id_wr0; + u32 lcm_ctrl_bank_mask_id_wr1; + u32 lcm_ctrl_bank_mask_id_wr2; + u32 lcm_ctrl_bank_mask_id_wr3; + u32 lcm_ctrl_bank_mask_id_wr4; + u32 lcm_ctrl_bank_mask_id_wr5; + u8 _reserved2[0x28]; + u32 lcm_ctrl_bank_mstr_id_rd0; + u32 lcm_ctrl_bank_mstr_id_rd1; + u32 lcm_ctrl_bank_mstr_id_rd2; + u32 lcm_ctrl_bank_mstr_id_rd3; + u32 lcm_ctrl_bank_mstr_id_rd4; + u32 lcm_ctrl_bank_mstr_id_rd5; + u8 _reserved3[0x28]; + u32 lcm_ctrl_bank_mask_id_rd0; + u32 lcm_ctrl_bank_mask_id_rd1; + u32 lcm_ctrl_bank_mask_id_rd2; + u32 lcm_ctrl_bank_mask_id_rd3; + u32 lcm_ctrl_bank_mask_id_rd4; + u32 lcm_ctrl_bank_mask_id_rd5; +}; + +check_member(mvmap2315_lcm_regs, lcm_ctrl_bank_mask_id_rd5, 0xe4); +static struct mvmap2315_lcm_regs * const mvmap2315_lcm_regs + = (void *)MVMAP2315_LCM_REGS_BASE; + +void apmu_start(void); +int apmu_set_pll(u32 dev, u32 state, u32 freq); +int apmu_set_dev(u32 dev, u32 state); +int apmu_set_clk(u32 clk, u32 state, u32 div, u32 src); + +#endif /* __SOC_MARVELL_MVMAP2315_APMU_H__ */

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add WDT driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15519 -gerrit commit 61885ec3aaaf454d44c8a4fa570cbcf92b757c6f Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:55:05 2016 -0700 soc/marvell/mvmap2315: Add WDT driver Testing: booted successfully. Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 3 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/wdt.h | 53 ++++++++++++++++ src/soc/marvell/mvmap2315/wdt.c | 74 ++++++++++++++++++++++ 4 files changed, 132 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index e16286b..b1f7751 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -34,6 +34,7 @@ bootblock-y += reset.c bootblock-y += timer.c bootblock-y += sdram.c bootblock-y += uart.c +bootblock-y += wdt.c ramstage-y += cbmem.c ramstage-y += gpio.c @@ -43,6 +44,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-y += sdram.c ramstage-y += uart.c +ramstage-y += wdt.c romstage-y += cbmem.c romstage-y += clock.c @@ -55,6 +57,7 @@ romstage-y += romstage.c romstage-y += sdram.c romstage-y += timer.c romstage-y += uart.c +romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 318bfc0..aefb5b8 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -25,6 +25,8 @@ #define MVMAP2315_GPIOF_BASE 0xE0142000 #define MVMAP2315_GPIOG_BASE 0xE0142100 #define MVMAP2315_GPIOH_BASE 0xE0142200 +#define MVMAP2315_WDT0_BASE 0XE1010000 +#define MVMAP2315_WDT1_BASE 0XE1020000 #define MVMAP2315_A2BUS_BANKED_BASE 0xF0000000 #define MVMAP2315_A2BUS_ALIAS6_BASE 0xF0002000 diff --git a/src/soc/marvell/mvmap2315/include/soc/wdt.h b/src/soc/marvell/mvmap2315/include/soc/wdt.h new file mode 100644 index 0000000..4c08b9c --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/wdt.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_WDT_H__ +#define __SOC_MARVELL_MVMAP2315_WDT_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_R4_WDT 0 +#define MVMAP2315_AP_WDT 1 + +#define MVMAP2315_WDT_CR_RPL_SHIFT 2 +#define MVMAP2315_WDT_CR_RMOD BIT(1) +#define MVMAP2315_WDT_CR_EN BIT(0) +#define MVMAP2315_WDT_TORR_TOP_SHIFT 0 +#define MVMAP2315_WDT_CRR_SHIFT 0 +struct mvmap2315_wdt_regs { + u32 wdt_cr; + u32 wdt_torr; + u32 wdt_ccvr; + u32 wdt_crr; + u32 wdt_stat; + u32 wdt_eoi; + u8 _reserved0[0xcc]; + u32 wdt_comp_params_5; + u32 wdt_comp_params_4; + u32 wdt_comp_params_3; + u32 wdt_comp_params_2; + u32 wdt_comp_params_1; + u32 wdt_comp_version; + u32 wdt_comp_type; +}; + +check_member(mvmap2315_wdt_regs, wdt_comp_type, 0xfc); + + +void enable_sp_watchdog(u32 timer, u32 timeout_value); +void reset_sp_watchdog(u32 timer, u32 timeout_value); + +#endif /* __SOC_MARVELL_MVMAP2315_WDT_H__ */ diff --git a/src/soc/marvell/mvmap2315/wdt.c b/src/soc/marvell/mvmap2315/wdt.c new file mode 100644 index 0000000..8c643b7 --- /dev/null +++ b/src/soc/marvell/mvmap2315/wdt.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/wdt.h> + +struct mvmap2315_wdt_regs *mvmap2315_wdts[] = { + (struct mvmap2315_wdt_regs *)MVMAP2315_WDT0_BASE, + (struct mvmap2315_wdt_regs *)MVMAP2315_WDT1_BASE, +}; + +void enable_sp_watchdog(u32 timer, u32 timeout_value) +{ + u32 reg; + + reg = read32(&mvmap2315_wdts[timer]->wdt_cr); + + /* set watchdog Reset pulse length to the highest value + * (256 Pclk cycles) + */ + reg |= 7 << MVMAP2315_WDT_CR_RPL_SHIFT; + + /* set the watchdog timer to generate a system reset */ + reg &= ~MVMAP2315_WDT_CR_RMOD; + + write32(&mvmap2315_wdts[timer]->wdt_cr, reg); + + /* enable the watchdog timer */ + setbits_le32(&mvmap2315_wdts[timer]->wdt_cr, MVMAP2315_WDT_CR_EN); + + /* set watchdog Timeout Range Register */ + reg = timeout_value << MVMAP2315_WDT_TORR_TOP_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_torr, reg); + + /* reset the timer */ + reg = 0x76 << MVMAP2315_WDT_CRR_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_crr, reg); +} + +void reset_sp_watchdog(u32 timer, u32 timeout_value) +{ + u32 reg; + + /* set watchdog Timeout Range Register */ + reg = timeout_value << MVMAP2315_WDT_TORR_TOP_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_torr, reg); + + if (read32(&mvmap2315_wdts[timer]->wdt_cr) & MVMAP2315_WDT_CR_EN) { + /* reset the timer */ + reg = 0x76 << MVMAP2315_WDT_CRR_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_crr, reg); + } else { + /* enable the watchdog timer */ + setbits_le32(&mvmap2315_wdts[timer]->wdt_cr, + MVMAP2315_WDT_CR_EN); + } +}

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add PMIC driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16149 -gerrit commit 31b6d9ef0830e5b6d57e402a19c600c2f61c0579 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:53:32 2016 -0700 soc/marvell/mvmap2315: Add PMIC driver Testing: booted successfully. Change-Id: I168206585f403d2259efe424e563982be661df0b Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/bootblock.c | 29 ++- src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/pmic.h | 194 +++++++++++++++++++++ src/soc/marvell/mvmap2315/pmic.c | 125 +++++++++++++ 5 files changed, 349 insertions(+), 2 deletions(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 69733bf..1e0cdac 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -27,6 +27,7 @@ bootblock-y += flash.c bootblock-y += load_validate.c bootblock-y += media.c bootblock-y += pinmux.c +bootblock-y += pmic.c bootblock-y += reset.c bootblock-y += timer.c bootblock-y += sdram.c diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 8ad2eed..4b2fd2100 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <stdlib.h> +#include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> #include <timestamp.h> @@ -25,6 +26,7 @@ #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> +#include <soc/pmic.h> #include <soc/uart.h> void bootblock_soc_early_init(void) @@ -41,6 +43,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { struct bdb_pointer bdb_info; + u32 boot_path; set_bdb_pointers((u8 *)MVMAP2315_BDB_LCM_BASE, &bdb_info); @@ -49,8 +52,30 @@ void bootblock_soc_init(void) apmu_start(); - printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); - load_and_validate(&bdb_info, MCU_FIRMWARE); + if (!(read32((void *)MVMAP2315_LOWPWR_REG) & MVMAP2315_LOWPWR_FLAG)) { + printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); + load_and_validate(&bdb_info, MCU_FIRMWARE); + mcu_start(); + boot_path = get_boot_path(); + } else { + printk(BIOS_DEBUG, "Low power restart. Skip MCU code load.\n"); + boot_path = get_boot_path(); + } + + switch (boot_path) { + case NO_BOOT: + no_boot(); + break; + case CHARGING_SCREEN: + charging_screen(); + break; + case FULL_BOOT: + full_boot(); + break; + } + + printk(BIOS_DEBUG, "Powering up the AP core0.\n"); + ap_start((void *)0xE0010000); /* initializing UART1 to free UART0 to be used by romstage */ uart_num = 1; diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 31f895f..e3ee304 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -36,10 +36,12 @@ #define MVMAP2315_MCU_SECCONFIG_BASE 0xED600000 #define MVMAP2315_APMU_PWRCTL_BASE 0xE012C000 #define MVMAP2315_LCM_REGS_BASE 0xE0130000 +#define MVMAP2315_CPU_BASE 0xF0410000 #define MVMAP2315_RAM_BASE 0x00000000 #define MVMAP2315_DEVICE_BASE 0x80000000 #define MVMAP2315_FLASH_BASE 0xFE000000 #define MVMAP2315_LCM_BASE 0xE0000000 +#define MVMAP2315_LOWPWR_REG 0xE0002000 #endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/pmic.h b/src/soc/marvell/mvmap2315/include/soc/pmic.h new file mode 100644 index 0000000..01a6040 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/pmic.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_PMIC_H__ +#define __SOC_MARVELL_MVMAP2315_PMIC_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_LOWPWR_FLAG BIT(4) + +#define MVMAP2315_APGENCFG_SYSBARDISABLE BIT(1) +#define MVMAP2315_APGENCFG_BROADCASTINNER BIT(2) +#define MVMAP2315_APGENCFG_BROADCASTOUTER BIT(3) +#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINT BIT(4) +#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU BIT(5) +#define MVMAP2315_APCORECFG0_AA64NAA32 BIT(4) +struct mvmap2315_cpu_regs { + u32 fuse00; + u32 fuse01; + u32 fuse02; + u32 fuse03; + u32 fuse04; + u32 fuse05; + u32 fuse06; + u32 fuse07; + u32 fuse10; + u32 fuse11; + u32 fuse12; + u32 fuse13; + u32 fuse14; + u32 fuse15; + u32 fuse16; + u32 fuse17; + u8 _reserved0[0x20]; + u32 fuse20; + u32 fuse21; + u32 fuse22; + u32 fuse23; + u32 fuse24; + u32 fuse25; + u32 fuse26; + u32 fuse27; + u32 fuse30; + u32 fuse31; + u32 fuse32; + u32 fuse33; + u32 fuse34; + u32 fuse35; + u32 fuse36; + u32 fuse37; + u32 fuse40; + u32 fuse41; + u32 fuse42; + u32 fuse43; + u32 fuse44; + u32 fuse45; + u32 fuse46; + u32 fuse47; + u32 fuse50; + u32 fuse51; + u32 fuse52; + u32 fuse53; + u32 fuse54; + u32 fuse55; + u32 fuse56; + u32 fuse57; + u32 fuse60; + u32 fuse61; + u32 fuse62; + u32 fuse63; + u32 fuse64; + u32 fuse65; + u32 fuse66; + u32 fuse67; + u32 fuse70; + u32 fuse71; + u32 fuse72; + u32 fuse73; + u32 fuse74; + u32 fuse75; + u32 fuse76; + u32 fuse77; + u32 fuse80; + u32 fuse81; + u32 fuse82; + u32 fuse83; + u32 fuse84; + u32 fuse85; + u32 fuse86; + u32 fuse87; + u32 fuse90; + u32 fuse91; + u32 fuse92; + u32 fuse93; + u32 fuse94; + u32 fuse95; + u32 fuse96; + u32 fuse97; + u32 fuse100; + u32 fuse101; + u32 fuse102; + u32 fuse103; + u32 fuse104; + u32 fuse105; + u32 fuse106; + u32 fuse107; + u32 fuse110; + u32 fuse111; + u32 fuse112; + u32 fuse113; + u32 fuse114; + u32 fuse115; + u32 fuse116; + u32 fuse117; + u32 fuse120; + u32 fuse121; + u32 fuse122; + u32 fuse123; + u32 fuse124; + u32 fuse125; + u32 fuse126; + u32 fuse127; + u32 fuse130; + u32 fuse131; + u32 fuse132; + u32 fuse133; + u32 fuse134; + u32 fuse135; + u32 fuse136; + u32 fuse137; + u32 fuse140; + u32 fuse141; + u32 fuse142; + u32 fuse143; + u32 fuse144; + u32 fuse145; + u32 fuse146; + u32 fuse147; + u32 fuse150; + u32 fuse151; + u32 fuse152; + u32 fuse153; + u32 fuse154; + u32 fuse155; + u32 fuse156; + u32 fuse157; + u32 apgencfg; + u32 apcorecfg0; + u32 apcorecfg1; + u32 apcorecfg2; + u32 apcorecfg3; + u32 rvbaraddr_low0; + u32 rvbaraddr_low1; + u32 rvbaraddr_low2; + u32 rvbaraddr_low3; + u8 _reserved1[0x10]; + u32 rvbaraddr_high0; + u32 rvbaraddr_high1; + u32 rvbaraddr_high2; + u32 rvbaraddr_high3; + u32 highvecremap; +}; + +check_member(mvmap2315_cpu_regs, highvecremap, 0x264); +static struct mvmap2315_cpu_regs * const mvmap2315_cpu + = (void *)MVMAP2315_CPU_BASE; + +enum boot_options { + NO_BOOT = 0, + CHARGING_SCREEN = 1, + FULL_BOOT = 2 +}; + +void no_boot(void); +void full_boot(void); +void charging_screen(void); +void mcu_start(void); +void ap_start(void *entry); +u32 get_boot_path(void); + +#endif /* __SOC_MARVELL_MVMAP2315_PMIC_H__ */ diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c new file mode 100644 index 0000000..f263804 --- /dev/null +++ b/src/soc/marvell/mvmap2315/pmic.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <soc/apmu.h> +#include <soc/clock.h> +#include <soc/pmic.h> + +static void syspwr_init(void) +{ + int result = 0; + + /* Start the PLLs */ + result |= apmu_set_pll(MAIN_PLL, D0, 2000); + result |= apmu_set_pll(CPU_PLL, D0, 2400); + result |= apmu_set_pll(MC_PLL, D0, 3200); + result |= apmu_set_pll(MCFLC_PLL, D0, 2133); + result |= apmu_set_pll(A2_PLL, D0, 1800); + result |= apmu_set_pll(GPU_PLL0, D0, 2000); + result |= apmu_set_pll(GPU_PLL1, D0, 2400); + result |= apmu_set_pll(MIPI_PLL, D0, 2000); + result |= apmu_set_pll(DISPLAY_PLL, D0, 1800); + + /* Start the peripheral devices */ + result |= apmu_set_dev(SDMMC, D0); + result |= apmu_set_dev(AES256, D0); + result |= apmu_set_dev(AP_AXI_HS, D0); + result |= apmu_set_dev(AP_UART0, D0); + result |= apmu_set_dev(AP_UART1, D0); + result |= apmu_set_dev(AP_M2M, D0); + result |= apmu_set_dev(AP_APB, D0); + result |= apmu_set_dev(AP_GIC, D0); + result |= apmu_set_dev(A2, D0); + result |= apmu_set_dev(MC, D0); + result |= apmu_set_dev(DDRPHY_0, D0); + result |= apmu_set_dev(DDRPHY_1, D0); + result |= apmu_set_dev(DDRPHY_2, D0); + result |= apmu_set_dev(DDRPHY_3, D0); + + if (result) + assert("ERRORS DURING system POWER-on"); +} + +void ap_start(void *entry) +{ + int result = 0; + + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTINNER); + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTOUTER); + clrbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTCACHEMAINT); + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU); + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_SYSBARDISABLE); + + result |= apmu_set_dev(APCPU_L2, D0); + + setbits_le32(&mvmap2315_cpu->apcorecfg0, + MVMAP2315_APCORECFG0_AA64NAA32); + + write32(&mvmap2315_cpu->rvbaraddr_low0, ((uintptr_t)entry) >> 2); + + write32(&mvmap2315_cpu->rvbaraddr_high0, 0); + + result |= apmu_set_dev(APCPU_0, D0); + + if (result) + assert("ERRORS DURING AP POWER-on"); +} + +void no_boot(void) +{ + /*TODO: impelement no_boot */ +} + +void charging_screen(void) +{ + /*TODO: impelement charging_screen */ +} + +void full_boot(void) +{ + printk(BIOS_DEBUG, "Powering up the system.\n"); + syspwr_init(); +} + +void mcu_start(void) +{ + int result = 0; + + result |= apmu_set_pll(APLL0, D0, APLL_589P824); + result |= apmu_set_clk(M4CLK, NOCHANGE, 4, SRCSEL_APLL0); + + if (result) + assert("ERRORS DURING MCU POWER-on"); + + clrbits_le32(&mvmap2315_mpmu_clk->resetmcu, MVMAP2315_MCU_RST_EN); + setbits_le32(&mvmap2315_mpmu_clk->resetmcu, MVMAP2315_MCU_RST_EN); +} + +u32 get_boot_path(void) +{ + return FULL_BOOT; +}

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add MCU driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15529 -gerrit commit 55b529441ef222aa866dd446b58bf69156700b07 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:55:34 2016 -0700 soc/marvell/mvmap2315: Add MCU driver Testing: booted successfully. Change-Id: I003f6929b00476d46be931773cd35418fe6622a6 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/bootblock.c | 8 ++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/mcu.h | 116 ++++++++++++++++++ src/soc/marvell/mvmap2315/mcu.c | 130 +++++++++++++++++++++ src/soc/marvell/mvmap2315/pmic.c | 9 +- 6 files changed, 265 insertions(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index b1f7751..4b8a53f 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -26,6 +26,7 @@ bootblock-y += gic.c bootblock-y += gpio.c bootblock-y += flash.c bootblock-y += load_validate.c +bootblock-y += mcu.c bootblock-y += media.c bootblock-y += nvm.c bootblock-y += pinmux.c diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 7a8919c..04f2436 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -27,6 +27,7 @@ #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> +#include <soc/mcu.h> #include <soc/pmic.h> #include <soc/uart.h> @@ -60,6 +61,13 @@ void bootblock_soc_init(void) boot_path = get_boot_path(); } else { printk(BIOS_DEBUG, "Low power restart. Skip MCU code load.\n"); + + sned_hash_msg(GET_HASH); + receive_hash_msg_respond(); + + printk(BIOS_DEBUG, + "MCU hash validation not currently implemented\n"); + boot_path = get_boot_path(); } diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index aefb5b8..33541c8 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -27,6 +27,8 @@ #define MVMAP2315_GPIOH_BASE 0xE0142200 #define MVMAP2315_WDT0_BASE 0XE1010000 #define MVMAP2315_WDT1_BASE 0XE1020000 +#define MVMAP2315_SP_IPC_BASE 0xED0C2000 +#define MVMAP2315_MCU_MSG_BUFF_BASE 0xEE03FF8C #define MVMAP2315_A2BUS_BANKED_BASE 0xF0000000 #define MVMAP2315_A2BUS_ALIAS6_BASE 0xF0002000 diff --git a/src/soc/marvell/mvmap2315/include/soc/mcu.h b/src/soc/marvell/mvmap2315/include/soc/mcu.h new file mode 100644 index 0000000..1d4014c --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/mcu.h @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MCU_H__ +#define __SOC_MARVELL_MVMAP2315_MCU_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_MCU_MSG_OFFSET 0xCE000000 + +enum { + GET_HASH = 0x0, + ABORT_HASH = 0x1, + START_HASH = 0x2, + SYNC_HASH = 0x3, +}; + +enum { + ABORT = 0x0, + FINISHED = 0x1, + BUSY = 0x2 +}; + +enum { + MSG_READY = 1, + MSG_RECEIVED = 8, + MSG_READY_RECEIVED = 9, +}; + +struct sp_hash_request_msg { + u8 protocol_version; + u8 csum; + u16 cmd_id; + u8 cmd_version; + u8 reserved0; + u16 length; + u8 hash_subcmd; + u8 hash_type; + u8 nonce_size; + u8 reserved1; + u32 offset; + u32 size; + u8 nonce_data[64]; +}; + +check_member(sp_hash_request_msg, nonce_data, 0x14); +static struct sp_hash_request_msg * const mvmap2315_mcu_msg_buff + = (void *)MVMAP2315_MCU_MSG_BUFF_BASE; + +struct mcu_hash_msg { + u8 protocol_version; + u8 csum; + u16 result; + u16 length; + u8 status; + u8 type; + u8 digest_size; + u8 reserved0; + u32 offset; + u32 size; + u8 digest_data[64]; +}; + +struct mcu_pwr_status_msg { + u8 protocol_version; + u8 csum; + u16 cmd_id; + u8 cmd_version; + u8 reserved; + u16 length; + u8 status; +}; + +#define MVMAP2315_IPC_IRQSET_MSGSENT BIT(0) +#define MVMAP2315_IPC_IRQCLR_MSGREADY BIT(0) +#define MVMAP2315_IPC_IRQCLR_MSGRECEIVED BIT(3) +#define MVMAP2315_IPC_IRQACK BIT(3) +#define MVMAP2315_MCU_IPC_IRQ BIT(6) +struct mvmap2315_ipc_regs { + u32 isrr; + u32 wdr0; + u32 wdr1; + u32 isrw; + u32 icr; + u32 iir; + u32 rdr0; + u32 rdr1; + u32 maj_mid_rev; + u32 cfg_rev; + u32 dummy; +}; + +check_member(mvmap2315_ipc_regs, dummy, 0x28); +static struct mvmap2315_ipc_regs * const mvmap2315_sp_ipc + = (void *)MVMAP2315_SP_IPC_BASE; + +void mcu_irq(void); +void send_mcu_msg(void *msg, u32 size); +void *receive_mcu_msg(void); +void sned_hash_msg(u8 subcmd); +void *receive_hash_msg_respond(void); + +#endif /* __SOC_MARVELL_MVMAP2315_MCU_H__ */ diff --git a/src/soc/marvell/mvmap2315/mcu.c b/src/soc/marvell/mvmap2315/mcu.c new file mode 100644 index 0000000..c334cda --- /dev/null +++ b/src/soc/marvell/mvmap2315/mcu.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/gic.h> +#include <soc/mcu.h> + +static u8 mvmap2315_calc_checksum(const void *data, u32 size) +{ + u8 csum; + const u8 *bytes = data; + int i; + + for (i = csum = 0; i < size; i++) + csum += bytes[i]; + + return (~csum) && 0xFF; +} + +void mcu_irq(void) +{ + printk(BIOS_DEBUG, "waiting for MCU msg...\n"); + while (!(read32(&mvmap2315_bcm_gicd->ispendr2) & + MVMAP2315_MCU_IPC_IRQ)) + ; +} + +void send_mcu_msg(void *msg, u32 size) +{ + printk(BIOS_DEBUG, "sending msg to MCU...\n"); + write32(&mvmap2315_sp_ipc->wdr0, (u32)msg); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQSET_MSGSENT); +} + +void *receive_mcu_msg(void) +{ + void *msg; + + printk(BIOS_DEBUG, "receiving msg to MCU...\n"); + + write32(&mvmap2315_sp_ipc->dummy, 0xA5A5A5A5); + + switch (read32(&mvmap2315_sp_ipc->iir)) { + case MSG_READY: + msg = (void *)(read32(&mvmap2315_sp_ipc->rdr0) + + MVMAP2315_MCU_MSG_OFFSET); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGREADY); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQACK); + break; + case MSG_RECEIVED: + msg = NULL; + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGRECEIVED); + break; + case MSG_READY_RECEIVED: + msg = (void *)(read32(&mvmap2315_sp_ipc->rdr0) + + MVMAP2315_MCU_MSG_OFFSET); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGREADY); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGRECEIVED); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQACK); + + break; + default: + msg = NULL; + write32(&mvmap2315_sp_ipc->icr, read32(&mvmap2315_sp_ipc->iir)); + break; + } + + return msg; +} + +void sned_hash_msg(u8 subcmd) +{ + printk(BIOS_DEBUG, "requesting MCU hash...\n"); + + mvmap2315_mcu_msg_buff->protocol_version = 0x3; + mvmap2315_mcu_msg_buff->cmd_id = 0x2A; + mvmap2315_mcu_msg_buff->reserved0 = 0x0; + mvmap2315_mcu_msg_buff->length = 76; + mvmap2315_mcu_msg_buff->csum = 0; + mvmap2315_mcu_msg_buff->hash_subcmd = subcmd; + mvmap2315_mcu_msg_buff->hash_type = 0; + mvmap2315_mcu_msg_buff->nonce_size = 0; + mvmap2315_mcu_msg_buff->reserved1 = 0; + mvmap2315_mcu_msg_buff->offset = 0; + mvmap2315_mcu_msg_buff->size = 32; + mvmap2315_mcu_msg_buff->csum = mvmap2315_calc_checksum( + (void *)mvmap2315_mcu_msg_buff, + sizeof(struct sp_hash_request_msg)); + + send_mcu_msg((void *)mvmap2315_mcu_msg_buff, + sizeof(struct sp_hash_request_msg)); +} + +void *receive_hash_msg_respond(void) +{ + struct mcu_hash_msg *mvmap2315_hash_msg_response; + + printk(BIOS_DEBUG, "waiting for MCU hash response msg...\n"); + + mcu_irq(); + + mvmap2315_hash_msg_response = receive_mcu_msg(); + + mcu_irq(); + + receive_mcu_msg(); + + return mvmap2315_hash_msg_response; +} diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c index f263804..89ea5eb 100644 --- a/src/soc/marvell/mvmap2315/pmic.c +++ b/src/soc/marvell/mvmap2315/pmic.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <soc/apmu.h> #include <soc/clock.h> +#include <soc/mcu.h> #include <soc/pmic.h> static void syspwr_init(void) @@ -121,5 +122,11 @@ void mcu_start(void) u32 get_boot_path(void) { - return FULL_BOOT; + struct mcu_pwr_status_msg *msg; + + mcu_irq(); + + msg = receive_mcu_msg(); + + return msg->status; }

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add load_validate driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16148 -gerrit commit adf68d0eb7f3a639430f9620aedcaf7f66ac31bb Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:52:21 2016 -0700 soc/marvell/mvmap2315: Add load_validate driver Load_validate: it loads and validates images from flash using hash values stored in the BDB. Testing: booted successfully. Change-Id: I0b00e8c60ed76622d03cb232d5c4273b4077aae7 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 3 + src/soc/marvell/mvmap2315/bdb.c | 79 +++++++++++++ src/soc/marvell/mvmap2315/bootblock.c | 12 ++ src/soc/marvell/mvmap2315/digest.c | 64 +++++++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 1 + src/soc/marvell/mvmap2315/include/soc/bdb.h | 125 +++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/digest.h | 35 ++++++ .../marvell/mvmap2315/include/soc/load_validate.h | 66 +++++++++++ src/soc/marvell/mvmap2315/load_validate.c | 123 ++++++++++++++++++++ 9 files changed, 508 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index c97ac01..85c526e 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -16,11 +16,14 @@ ifeq ($(CONFIG_SOC_MARVELL_MVMAP2315),y) bootblock-y += bootblock.c +bootblock-y += bdb.c bootblock-y += clock.c +bootblock-y += digest.c bootblock-y += fiq.S bootblock-y += gic.c bootblock-y += gpio.c bootblock-y += flash.c +bootblock-y += load_validate.c bootblock-y += media.c bootblock-y += pinmux.c bootblock-y += reset.c diff --git a/src/soc/marvell/mvmap2315/bdb.c b/src/soc/marvell/mvmap2315/bdb.c new file mode 100644 index 0000000..6be414c --- /dev/null +++ b/src/soc/marvell/mvmap2315/bdb.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/bdb.h> + +void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in) +{ + bdb_in->bdb_h + = (struct bdb_header *)start_addr; + + bdb_in->bdb_k + = (struct bdb_key *)(start_addr + + (bdb_in->bdb_h->struct_size)); + + bdb_in->bdb_oem_0 + = (u8 *)((u32)(bdb_in->bdb_k) + + (bdb_in->bdb_k->struct_size)); + + bdb_in->sub_k + = (struct bdb_key *)((u32)(bdb_in->bdb_oem_0) + + (bdb_in->bdb_h->oem_area_0_size)); + + bdb_in->bdb_h_s + = (struct bdb_sig *)((u32)(bdb_in->bdb_oem_0) + + (bdb_in->bdb_h->signed_size)); + + bdb_in->bdb_d + = (struct bdb_data *)((u32)(bdb_in->bdb_h_s) + + (bdb_in->bdb_h_s->struct_size)); + + bdb_in->oem_1 + = (u8 *)((u32)(bdb_in->bdb_d) + + (bdb_in->bdb_d->struct_size)); + + bdb_in->bdb_hash + = (struct bdb_hash *)((u32)(bdb_in->oem_1) + + (bdb_in->bdb_d->oem_area_1_size)); + + bdb_in->bdb_s + = (struct bdb_sig *)((u32)(bdb_in->bdb_d) + + (bdb_in->bdb_d->signed_size)); +} + +struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, u32 image_type) +{ + int i; + + if (!bdb_info) { + printk(BIOS_DEBUG, "can't find BDB\n"); + return NULL; + } + + for (i = 0; i < bdb_info->bdb_d->num_hashes; i++) { + if (bdb_info->bdb_hash[i].type == image_type) + return &bdb_info->bdb_hash[i]; + } + + printk(BIOS_DEBUG, "can't find image with type %d in the BDB\n", + image_type); + return NULL; +} diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 5aa9eb5..c02d1e5 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -21,7 +21,9 @@ #include <console/console.h> #include <timestamp.h> #include <console/uart.h> +#include <soc/bdb.h> #include <soc/gic.h> +#include <soc/load_validate.h> #include <soc/uart.h> void bootblock_soc_early_init(void) @@ -37,6 +39,16 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + struct bdb_pointer bdb_info; + + set_bdb_pointers((u8 *)MVMAP2315_BDB_LCM_BASE, &bdb_info); + + printk(BIOS_DEBUG, "loading and validating APMU firmware.\n"); + load_and_validate(&bdb_info, APMU_FIRMWARE); + + printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); + load_and_validate(&bdb_info, MCU_FIRMWARE); + /* initializing UART1 to free UART0 to be used by romstage */ uart_num = 1; uart_init(uart_num); diff --git a/src/soc/marvell/mvmap2315/digest.c b/src/soc/marvell/mvmap2315/digest.c new file mode 100644 index 0000000..35cd5b1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/digest.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/digest.h> +#include <string.h> + +struct digest_ops digest_callbacks = { + .init = (security_init_F) MVMAP2315_DIGEST_INIT, + .sha_hash = (sha_hash_F) MVMAP2315_DIGEST_SHA_HASH, +}; + +u32 digest_init(void) +{ + int rc; + + rc = digest_callbacks.init(0); + + if (rc) + printk(BIOS_DEBUG, "digest_init failed with rc=%x.\n", rc); + + return rc; +} + +u32 digest_sha_hash(const u8 *msg, u32 msg_len, u8 *digest, u32 digest_len) +{ + int rc; + + rc = digest_callbacks.sha_hash(msg, msg_len, digest, digest_len); + + if (rc) + printk(BIOS_DEBUG, "digest_sha_hash failed with rc=%x.\n", rc); + + return rc; +} + +u32 digest_cmp(const u8 *msg, u8 *digest, u32 digest_len) +{ + int rc; + + rc = memcmp(msg, digest, digest_len); + + if (rc) + printk(BIOS_DEBUG, "image hash doesn't match BDB expected"); + + return rc; +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index b78257e..fb3b05f 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -33,6 +33,7 @@ #define MVMAP2315_APMU_CLK_BASE 0xE0125400 #define MVMAP2315_GENTIMER_BASE 0xE0137000 #define MVMAP2315_MPMU_CLK_BASE 0xEF000800 +#define MVMAP2315_MCU_SECCONFIG_BASE 0xED600000 #define MVMAP2315_RAM_BASE 0x00000000 #define MVMAP2315_DEVICE_BASE 0x80000000 diff --git a/src/soc/marvell/mvmap2315/include/soc/bdb.h b/src/soc/marvell/mvmap2315/include/soc/bdb.h new file mode 100644 index 0000000..71489ee --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/bdb.h @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_BDB_H__ +#define __SOC_MARVELL_MVMAP2315_BDB_H__ + +#define MVMAP2315_BDB_LCM_BASE 0xE0000000 + +enum { + BDB_RESERVED = 0, + SP_RW_FIRMWARE = 1, + AP_RW_FIRMWARE = 2, + MCU_FIRMWARE = 3, + APMU_FIRMWARE = 4, + KERNEL_IMAGE = 128, + KERNEL_COMMAND_LINE = 129, + SIXTEEN_BIT_VMLINUX_HEADER = 130 +}; + +#pragma pack(push, 1) +struct bdb_header { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u64 bdb_load_address; + u32 bdb_size; + u32 signed_size; + u32 oem_area_0_size; + u8 reserved0[8]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_key { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u8 hash_alg; + u8 sig_alg; + u8 reserved0[2]; + u32 key_version; + char description[128]; + u8 key_data[]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_sig { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u8 hash_alg; + u8 sig_alg; + u8 reserved0[2]; + u32 signed_size; + char description[128]; + u8 sig_SOC_MARVELL_MVMAP2315_data[]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_data { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u32 data_version; + u32 oem_area_1_size; + u8 num_hashes; + u8 hash_entry_size; + u8 reserved0[2]; + u32 signed_size; + u8 reserved1[8]; + char description[128]; +}; + +#pragma pack(pop) + +#pragma pack(push, 1) +struct bdb_hash { + u64 offset; + u32 size; + u8 partition; + u8 type; + u8 reserved0[2]; + u64 load_address; + u8 digest[32]; +}; + +#pragma pack(pop) + +struct bdb_pointer { + struct bdb_header *bdb_h; + struct bdb_key *bdb_k; + u8 *bdb_oem_0; + struct bdb_key *sub_k; + struct bdb_sig *bdb_h_s; + struct bdb_data *bdb_d; + u8 *oem_1; + struct bdb_hash *bdb_hash; + struct bdb_sig *bdb_s; +}; + +void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in); +struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, u32 image_type); + +#endif /* __SOC_MARVELL_MVMAP2315_BDB_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/digest.h b/src/soc/marvell/mvmap2315/include/soc/digest.h new file mode 100644 index 0000000..961dbd6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/digest.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_DIGEST_H__ +#define __SOC_MARVELL_MVMAP2315_DIGEST_H__ + +#define MVMAP2315_DIGEST_INIT 0xFFE00040 +#define MVMAP2315_DIGEST_SHA_HASH 0xFFE00044 + +typedef u32 (*security_init_F)(u32 adv_ver); +typedef u32 (*sha_hash_F)(const u8 *msg, u32 msg_len, u8 *digest, + u32 digest_len); + +struct digest_ops { + security_init_F init; + sha_hash_F sha_hash; +}; + +u32 digest_init(void); +u32 digest_sha_hash(const u8 *msg, u32 msg_len, u8 *digest, u32 digest_len); +u32 digest_cmp(const u8 *msg, u8 *digest, u32 digest_len); + +#endif /* __SOC_MARVELL_MVMAP2315_DIGEST_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/load_validate.h b/src/soc/marvell/mvmap2315/include/soc/load_validate.h new file mode 100644 index 0000000..b8912f5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/load_validate.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ +#define __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ + +#include <soc/addressmap.h> +#include <types.h> + +enum { + PRIMARY_BDB = 0, + ALTERNATE_BDB = 1, + RECOVERY_BDB = 2, +}; + +#define MVMAP2315_BDB_TYPE (BIT(0) | BIT(1)) +struct mvmap2315_bootrom_info { + u32 sp_ro_status; + u32 flash_media; +}; + +struct mvmap2315_mcu_secconfig_regs { + u8 _reserved0[0x04]; + u32 strap_override_sec_cfg; + u32 sec_mcu_cfg_sec_cfg; + u32 lcm_mcu_cfg_sec_cfg0; + u32 lcm_mcu_cfg_sec_cfg1; + u32 lcm_mcu_cfg_sec_cfg2; + u8 _reserved1[0xe8]; + u32 dap_debug_disable; + u32 boot_avs_status; + u32 pwr_clr_in; + u32 pwr_clr_recovery; + u32 pwr_clr_bdb; + u32 pwr_clr_fail_a; + u32 pwr_clr_fail_b; + u32 rst_clr_dev; + u32 rst_clr_wp1; + u32 rst_clr_wp2; + u32 rst_clr_lp; + u32 boot_gpio_out; + u32 boot_gpio_in; + u32 boot_hw_lockdown_nvm; + u32 boot_hw_lockdown_pinmux; + u32 boot_callback_pointer; +}; + +check_member(mvmap2315_mcu_secconfig_regs, boot_callback_pointer, 0x13c); +static struct mvmap2315_mcu_secconfig_regs * const mvmap2315_mcu_secconfig + = (void *)MVMAP2315_MCU_SECCONFIG_BASE; + +void load_and_validate(struct bdb_pointer *bdb_info, u32 image_type); + +#endif /* __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ */ diff --git a/src/soc/marvell/mvmap2315/load_validate.c b/src/soc/marvell/mvmap2315/load_validate.c new file mode 100644 index 0000000..422c57f --- /dev/null +++ b/src/soc/marvell/mvmap2315/load_validate.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/bdb.h> +#include <soc/digest.h> +#include <soc/flash.h> +#include <soc/load_validate.h> +#include <soc/reset.h> + +static void set_flash_parameters(struct flash_params *flash_info, + struct bdb_hash *image_info) +{ + (*flash_info).offset + = (u32)(image_info->offset); + (*flash_info).buff + = (u32)(image_info->load_address); + (*flash_info).size = image_info->size; + (*flash_info).id = 0x0; + (*flash_info).partition = (u32)image_info->partition; +} + +static void image_failure(void) +{ + struct mvmap2315_bootrom_info *bootrom_info + = (void *)read32( + &mvmap2315_mcu_secconfig->boot_callback_pointer); + + printk(BIOS_DEBUG, "Resetting system!!\n"); + + if ((bootrom_info->sp_ro_status & MVMAP2315_BDB_TYPE) + == PRIMARY_BDB) { + write32(&mvmap2315_mcu_secconfig->pwr_clr_fail_a, 1); + + if (read32( + &mvmap2315_mcu_secconfig->pwr_clr_fail_b)) { + printk(BIOS_DEBUG, "primary & ALT BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting to recovery mode...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_recovery, 1); + } else { + printk(BIOS_DEBUG, "primary BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting using AlT BDB...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_bdb, 1); + } + } else if ((bootrom_info->sp_ro_status & MVMAP2315_BDB_TYPE) + == ALTERNATE_BDB) { + write32(&mvmap2315_mcu_secconfig->pwr_clr_fail_b, 1); + + if (read32( + &mvmap2315_mcu_secconfig->pwr_clr_fail_a)) { + printk(BIOS_DEBUG, "primary & ALT BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting to recovery mode...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_recovery, 1); + } else { + printk(BIOS_DEBUG, "AlT BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting using primary BDB...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_bdb, 0); + } + } else if ((bootrom_info->sp_ro_status & MVMAP2315_BDB_TYPE) + == RECOVERY_BDB) { + printk(BIOS_DEBUG, "Recovery image has errors!!!\n"); + printk(BIOS_DEBUG, "Re-entering recovery mode...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_recovery, 1); + } + + mvmap2315_reset(); +} + +void load_and_validate(struct bdb_pointer *bdb_info, u32 image_type) +{ + struct bdb_hash *image_info; + struct flash_params flash_info; + struct mvmap2315_bootrom_info *bootrom_info + = (void *)read32( + &mvmap2315_mcu_secconfig->boot_callback_pointer); + u8 image_digest[32]; + + image_info = find_bdb_image(bdb_info, image_type); + + if (!image_info) + image_failure(); + + set_flash_parameters(&flash_info, image_info); + + if (flash_init(bootrom_info->flash_media, MVMAP2315_MMC_CLK_MHZ)) + image_failure(); + + if (flash_partition(bootrom_info->flash_media, &flash_info)) + image_failure(); + + if (flash_read(bootrom_info->flash_media, &flash_info)) + image_failure(); + + if (flash_shutdown(bootrom_info->flash_media)) + image_failure(); + + if (digest_init()) + image_failure(); + + if (digest_sha_hash(((u8 *)(flash_info.buff)), image_info->size, + &image_digest[0], 32)) + image_failure(); + + if (digest_cmp(&image_digest[0], &image_info->digest[0], 32)) + image_failure(); +}

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Patch set updated for coreboot: soc/marvell/mvmap2315: Add gpio driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15508 -gerrit commit 282232c8bb3c8b38127ee706859fccf7a49f3559 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:51:28 2016 -0700 soc/marvell/mvmap2315: Add gpio driver Testing: booted successfully. Change-Id: I89dee1bbf8b68460897f64bf673b328533e70cd4 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 3 + src/soc/marvell/mvmap2315/gpio.c | 71 ++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 3 + src/soc/marvell/mvmap2315/include/soc/gpio.h | 97 ++++++++++++++++++++++ 4 files changed, 174 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index a2686b6..9467a35 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += fiq.S bootblock-y += gic.c +bootblock-y += gpio.c bootblock-y += media.c bootblock-y += pinmux.c bootblock-y += reset.c @@ -27,6 +28,7 @@ bootblock-y += sdram.c bootblock-y += uart.c ramstage-y += cbmem.c +ramstage-y += gpio.c ramstage-y += media.c ramstage-y += reset.c ramstage-y += soc.c @@ -36,6 +38,7 @@ ramstage-y += uart.c romstage-y += cbmem.c romstage-y += clock.c +romstage-y += gpio.c romstage-y += media.c romstage-y += mmu_operations.c romstage-y += reset.c diff --git a/src/soc/marvell/mvmap2315/gpio.c b/src/soc/marvell/mvmap2315/gpio.c new file mode 100644 index 0000000..6a5b885 --- /dev/null +++ b/src/soc/marvell/mvmap2315/gpio.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <gpio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/pinmux.h> + +struct mvmap2315_gpio_regs *gpio_banks[] = { + (struct mvmap2315_gpio_regs *)MVMAP2315_GPIOF_BASE, + (struct mvmap2315_gpio_regs *)MVMAP2315_GPIOG_BASE, + (struct mvmap2315_gpio_regs *)MVMAP2315_GPIOH_BASE, +}; + +int gpio_get(gpio_t gpio) +{ + return (read32(&gpio_banks[gpio.bank]->plr) >> gpio.idx) & 0x1; +} + +void gpio_set(gpio_t gpio, int value) +{ + if (value) + setbits_le32(&gpio_banks[gpio.bank]->psr, 1 << gpio.idx); + else + setbits_le32(&gpio_banks[gpio.bank]->pcr, 1 << gpio.idx); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + set_pinmux(PINMUX(GET_GPIO_PAD(gpio), 0, 1, 0, 0, PULLDOWN)); + clrbits_le32(&gpio_banks[gpio.bank]->pdr, 1 << gpio.idx); +} + +void gpio_input_pullup(gpio_t gpio) +{ + set_pinmux(PINMUX(GET_GPIO_PAD(gpio), 0, 1, 0, 0, PULLUP)); + clrbits_le32(&gpio_banks[gpio.bank]->pdr, 1 << gpio.idx); +} + +void gpio_input(gpio_t gpio) +{ + set_pinmux(PINMUX(GET_GPIO_PAD(gpio), 0, 1, 0, 0, PULLNONE)); + clrbits_le32(&gpio_banks[gpio.bank]->pdr, 1 << gpio.idx); +} + +void gpio_output(gpio_t gpio, int value) +{ + setbits_le32(&gpio_banks[gpio.bank]->pdr, 1 << gpio.idx); + + if (value) + setbits_le32(&gpio_banks[gpio.bank]->psr, 1 << gpio.idx); + else + setbits_le32(&gpio_banks[gpio.bank]->pcr, 1 << gpio.idx); +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 4b16c59..b78257e 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -22,6 +22,9 @@ #define MVMAP2315_PINMUX_BASE 0xE0140000 #define MVMAP2315_TIMER0_BASE 0xE1020000 +#define MVMAP2315_GPIOF_BASE 0xE0142000 +#define MVMAP2315_GPIOG_BASE 0xE0142100 +#define MVMAP2315_GPIOH_BASE 0xE0142200 #define MVMAP2315_BCM_GICD_BASE 0xE0111000 #define MVMAP2315_BCM_GICC_BASE 0xE0112000 diff --git a/src/soc/marvell/mvmap2315/include/soc/gpio.h b/src/soc/marvell/mvmap2315/include/soc/gpio.h new file mode 100644 index 0000000..d0c4b7d --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/gpio.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + + * This program is free software; + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_GPIO_H__ +#define __SOC_MARVELL_MVMAP2315_GPIO_H__ + +#include <types.h> + +#define GPIO(b, i) ((gpio_t){.bank = GPIO_##b, .idx = i}) +#define GET_GPIO_PAD(gpio) ((gpio.bank * 32) + gpio.idx + 160) + +struct mvmap2315_gpio_regs { + u32 plr; + u32 pdr; + u32 psr; + u32 pcr; + u32 hripr; + u32 lfipr; + u32 isr; + u32 sdr; + u32 cdr; + u32 shripr; + u32 chripr; + u32 slfipr; + u32 clfipr; + u32 olr; + u32 dwer; + u32 imr; + u32 rev0; + u32 rev1; + u32 simr; + u32 cimr; + u32 iter0; + u32 iter1; + u32 iter2; + u32 iter3; + u32 iter4; + u32 iter5; + u32 iter6; + u32 iter7; + u32 iter8; + u32 iter9; + u32 iter10; + u32 iter11; + u32 iter12; + u32 iter13; + u32 iter14; + u32 iter15; + u32 iter16; + u32 iter17; + u32 iter18; + u32 iter19; + u32 iter20; + u32 iter21; + u32 iter22; + u32 iter23; +}; + +check_member(mvmap2315_gpio_regs, iter23, 0xac); + +typedef union { + u32 raw; + struct { + u16 port; + union { + struct { + u16 num : 5; + u16 reserved1 : 11; + }; + struct { + u16 idx : 3; + u16 bank : 2; + u16 reserved2 : 11; + }; + }; + }; +} gpio_t; + +enum { + GPIO_F = 0, + GPIO_G = 1, + GPIO_H = 2, +}; + +#endif /* __SOC_MARVELL_MVMAP2315_GPIO_H__ */

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Patch set updated for coreboot: soc/marvell/mvmap2315: Add flash driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15509 -gerrit commit ea5ce068bd7834aab47d4a399fe20d33714b9d56 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 13:51:57 2016 -0700 soc/marvell/mvmap2315: Add flash driver Testing: booted successfully. Change-Id: Iaeff9f01dbfad7f313aa237e8c71c36c4ed1e06f Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/flash.c | 96 +++++++++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/flash.h | 55 +++++++++++++++ 3 files changed, 152 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 9467a35..c97ac01 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += clock.c bootblock-y += fiq.S bootblock-y += gic.c bootblock-y += gpio.c +bootblock-y += flash.c bootblock-y += media.c bootblock-y += pinmux.c bootblock-y += reset.c diff --git a/src/soc/marvell/mvmap2315/flash.c b/src/soc/marvell/mvmap2315/flash.c new file mode 100644 index 0000000..44936e4 --- /dev/null +++ b/src/soc/marvell/mvmap2315/flash.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/clock.h> +#include <soc/flash.h> + +struct flash_ops flash_callbacks = { + .init = (void *)MVMAP2315_FLASH_INIT, + .read = (void *)MVMAP2315_FLASH_READ, + .write = (void *)MVMAP2315_FLASH_WRITE, + .shutdown = (void *)MVMAP2315_FLASH_SHUTDOWN, + .set_partition = (void *)MVMAP2315_FLASH_SET_PARTITION, +}; + +u32 flash_init(u32 media, u32 clock_input_mhz) +{ + int rc; + + clrbits_le32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, + MVMAP2315_SDMMC_CLK_RSTN); + setbits_le32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, + MVMAP2315_SDMMC_CLK_RSTN); + + rc = flash_callbacks.init(media, 0, clock_input_mhz); + + if (rc) + printk(BIOS_DEBUG, "flash_init failed with rc=%x.\n", rc); + + return rc; +} + +u32 flash_partition(u32 media, struct flash_params *flash_image_info) +{ + int rc; + + rc = flash_callbacks.set_partition(media, 0, flash_image_info); + + if (rc) + printk(BIOS_DEBUG, "flash_partition failed with rc=%x.\n", rc); + + return rc; +} + +u32 flash_read(u32 media, struct flash_params *flash_image_info) +{ + int rc; + + rc = flash_callbacks.read(media, 0, flash_image_info); + + if (rc) + printk(BIOS_DEBUG, "flash_read failed with rc=%x.\n", rc); + + return rc; +} + +u32 flash_write(u32 media, struct flash_params *flash_image_info) +{ + int rc; + + rc = flash_callbacks.write(media, 0, flash_image_info); + + if (rc) + printk(BIOS_DEBUG, "flash_write failed with rc=%x.\n", rc); + + return rc; +} + +u32 flash_shutdown(u32 media) +{ + int rc; + + rc = flash_callbacks.shutdown(media, 0, 0); + + if (rc) + printk(BIOS_DEBUG, "flash_shutdown failed with rc=%x.\n", rc); + + return rc; +} diff --git a/src/soc/marvell/mvmap2315/include/soc/flash.h b/src/soc/marvell/mvmap2315/include/soc/flash.h new file mode 100644 index 0000000..5329e8b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/flash.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_FLASH_H__ +#define __SOC_MARVELL_MVMAP2315_FLASH_H__ + +#define MVMAP2315_FLASH_INIT 0xFFE00084 +#define MVMAP2315_FLASH_READ 0xFFE00088 +#define MVMAP2315_FLASH_WRITE 0xFFE0008C +#define MVMAP2315_FLASH_SHUTDOWN 0xFFE00098 +#define MVMAP2315_FLASH_SET_PARTITION 0xFFE00094 + +#define MVMAP2315_MMC_CLK_MHZ 0x00000019 + +enum { + MVMAP2315_SD = 7, + MVMAP2315_EMMC = 8, + MVMAP2315_EEPROM = 27, +}; + +struct flash_params { + u32 offset; + u32 buff; + u32 size; + u32 id; + u32 partition; +}; + +struct flash_ops { + u32 (*init)(u32 media, u32 context, u32 clock_input_mhz); + u32 (*read)(u32 media, u32 context, struct flash_params *); + u32 (*write)(u32 media, u32 context, struct flash_params *); + u32 (*shutdown)(u32 media, u32 context, struct flash_params *); + u32 (*set_partition)(u32 media, u32 context, struct flash_params *); +}; + +u32 flash_init(u32 media, u32 clock_input_mhz); +u32 flash_read(u32 media, struct flash_params *flash_image_info); +u32 flash_write(u32 media, struct flash_params *flash_image_info); +u32 flash_shutdown(u32 media); +u32 flash_partition(u32 media, struct flash_params *flash_image_info); + +#endif /* __SOC_MARVELL_MVMAP2315_FLASH_H__ */

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coreboot-gerrit August 2016