coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

1 participants
1551 discussions

Patch merged into coreboot/master: soc/intel/skylake: Correct Cache as ram size
by gerrit＠coreboot.org 18 Aug '16

18 Aug '16

the following patch was just integrated into master: commit 3ad63565a54f5ea3cdd866cbc6c70c67ad2757fe Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sun Aug 14 15:48:33 2016 +0530 soc/intel/skylake: Correct Cache as ram size DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000 is used to calculate the _car_region_end in car.ld. If the FSP CAR requirement is greater than or even close to DCACHE_RAM_SIZE then, the CAR region for FSP will be determined to be below the overall CAR region boundary i.e, out of CAR memory range. This is working with FSP 1.1 because we provide the FspCarSize and FspCarBase explicitly in a UPD. Hence, FSP is still able to use the upper region of CAR memory for its purpose. However, it will be a problem in case of FSP2.0 where FSP usable CAR is calculated using _car_region_end. So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB) Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/16236 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16236 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/skylake: Move bootblock specific code from skylake/romstage
by gerrit＠coreboot.org 18 Aug '16

18 Aug '16

the following patch was just integrated into master: commit ecd9a94213216f2f50e501e6b27ee390928e0dbf Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Aug 11 14:56:28 2016 +0530 soc/intel/skylake: Move bootblock specific code from skylake/romstage There is a lot of code that is being referred to in bootblock but resides under skylake/romstage folder. Hence move this code into skylake/bootblock, and update the relevant header files and Makefiles. TEST=Build and Boot kunimitsu. Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/16225 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16225 for details. -gerrit

1 0

Patch set updated for coreboot: soc/intel/skylake: Move bootblock specific code from skylake/romstage
by Rizwan Qureshi 18 Aug '16

18 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16225 -gerrit commit d3f0e1999879a0f5fbc4152dbb998f7edd91e3a9 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Aug 11 14:56:28 2016 +0530 soc/intel/skylake: Move bootblock specific code from skylake/romstage There is a lot of code that is being referred to in bootblock but resides under skylake/romstage folder. Hence move this code into skylake/bootblock, and update the relevant header files and Makefiles. TEST=Build and Boot kunimitsu. Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 5 +- src/soc/intel/skylake/bootblock/bootblock.c | 1 - src/soc/intel/skylake/bootblock/cpu.c | 26 +++ src/soc/intel/skylake/bootblock/i2c.c | 109 +++++++++++ src/soc/intel/skylake/bootblock/pch.c | 205 +++++++++++++++++++- src/soc/intel/skylake/bootblock/report_platform.c | 222 ++++++++++++++++++++++ src/soc/intel/skylake/bootblock/smbus.c | 47 +++++ src/soc/intel/skylake/include/soc/bootblock.h | 9 +- src/soc/intel/skylake/include/soc/romstage.h | 5 - src/soc/intel/skylake/romstage/Makefile.inc | 10 - src/soc/intel/skylake/romstage/cpu.c | 52 ----- src/soc/intel/skylake/romstage/i2c.c | 109 ----------- src/soc/intel/skylake/romstage/pch.c | 221 --------------------- src/soc/intel/skylake/romstage/report_platform.c | 222 ---------------------- src/soc/intel/skylake/romstage/smbus.c | 51 ----- 15 files changed, 618 insertions(+), 676 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 7b27c57..98f2718 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -12,16 +12,19 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += bootblock/smbus.c bootblock-y += bootblock/systemagent.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c bootblock-y += monotonic_timer.c bootblock-y += pch.c bootblock-y += pcr.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index f644d1f..b00fcf7 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -15,7 +15,6 @@ #include <bootblock_common.h> #include <soc/bootblock.h> -#include <soc/romstage.h> void asmlinkage bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 8c1e58a..3cea8bd 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -17,9 +17,11 @@ #include <stdint.h> #include <delay.h> #include <arch/io.h> +#include <console/console.h> #include <cpu/intel/microcode/microcode.c> #include <reset.h> #include <soc/bootblock.h> +#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -105,3 +107,27 @@ void bootblock_cpu_init(void) set_flex_ratio_to_tdp_nominal(); intel_update_microcode_from_cbfs(); } + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c new file mode 100644 index 0000000..64b1fb5 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/i2c.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/bootblock.h> +#include <soc/serialio.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + int devfn; + pci_devfn_t dev; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return 0; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + pci_devfn_t dev; + int devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return; + + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) + return; + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config) + return; + if (!config->i2c[bus].early_init) + return; + + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + SIO_REG_PPR_RESETS); + value = read32(reg); + value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(reg, value); + + /* Initialize the controller */ + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { + sptr = &config->i2c[bus].speed_config[value]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } +} + +void i2c_early_init(void) +{ + int bus; + + /* Initialize I2C controllers that are enabled in devicetree */ + for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) + i2c_early_init_bus(bus); +} diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index e7f414b..22df198 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -15,13 +15,22 @@ * GNU General Public License for more details. */ #include <arch/io.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/p2sb.h> +#include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr.h> -#include <soc/spi.h> +#include <soc/pm.h> +#include <soc/pmc.h> +#include <soc/smbus.h> + +/* Max PXRC registers in ITSS*/ +#define MAX_PXRC_CONFIG 0x08 /* * Enable Prefetching and Caching. @@ -65,7 +74,6 @@ static void enable_p2sbbar(void) /* Enable P2SB MSE */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* * Enable decoding for HPET memory address range. * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode @@ -81,3 +89,196 @@ void bootblock_pch_early_init(void) enable_spi_prefetch(); enable_p2sbbar(); } + +static void pch_enable_lpc(void) +{ + /* Lookup device tree in romstage */ + const struct device *dev; + const config_t *config; + u16 lpc_en; + + /* IO Decode Range */ + lpc_en = COMA_RANGE | (COMB_RANGE << 4); + pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); + + /* IO Decode Enable */ + lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + /* Set in PCI generic decode range registers */ + pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); + + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); +} + +static void pch_interrupt_init(void) +{ + const struct device *dev; + const config_t *config; + u8 index = 0; + u8 pch_interrupt_routing[MAX_PXRC_CONFIG]; + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pch_interrupt_routing[0] = config->pirqa_routing; + pch_interrupt_routing[1] = config->pirqb_routing; + pch_interrupt_routing[2] = config->pirqc_routing; + pch_interrupt_routing[3] = config->pirqd_routing; + pch_interrupt_routing[4] = config->pirqe_routing; + pch_interrupt_routing[5] = config->pirqf_routing; + pch_interrupt_routing[6] = config->pirqg_routing; + pch_interrupt_routing[7] = config->pirqh_routing; + + for (index = 0; index < MAX_PXRC_CONFIG; index++) { + if (pch_interrupt_routing[index] < 16 && + pch_interrupt_routing[index] > 2 && + pch_interrupt_routing[index] != 8 && + pch_interrupt_routing[index] != 13) { + pcr_write8(PID_ITSS, + (R_PCH_PCR_ITSS_PIRQA_ROUT + index), + pch_interrupt_routing[index]); + } + } +} + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); +} + +static void soc_config_pwrmbase(void) +{ + uint32_t reg32; + + /* Disable PWRMBASE in PMC Device first before changing Base address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable PWRM in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); + + /* + * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] + * to the same value programmed in PMC PCI Offset 48h bit[31:16], + * this has an implication of making sure the PWRMBASE to be + * 64KB aligned. + * + * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] + * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an + * implication of making sure the memory allocated to PWRMBASE to be 64KB + * in size. + */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, + ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | + (PCH_PWRM_BASE_ADDRESS >> 16))); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); +} + +static void soc_config_tco(void) +{ + uint32_t reg32 = 0; + uint16_t tcobase; + uint16_t tcocnt; + + /* Disable TCO in SMBUS Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); + reg32 &= ~SMBUS_TCO_EN; + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); + + /* Program TCO Base */ + pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); + + /* Enable TCO in SMBUS */ + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); + + /* + * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] + * to [SMBUS PCI offset 50h[15:5], 1]. + */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, + (TCO_BASE_ADDDRESS | (1 << 1))); + + /* Program TCO timer halt */ + tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); + tcobase &= ~0x1f; + tcocnt = inw(tcobase + TCO1_CNT); + tcocnt |= TCO_TMR_HLT; + outw(tcocnt, tcobase + TCO1_CNT); +} + +static void soc_config_rtc(void) +{ + /* Enable upper 128 bytes of CMOS */ + pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, + B_PCH_PCR_RTC_CONF_UCMOS_EN); +} + +void pch_early_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + soc_config_tco(); + + /* + * Interrupt Configuration Register Programming + * PIRQx to IRQ Programming + */ + pch_interrupt_init(); + + /* Program generic IO Decode Range */ + pch_enable_lpc(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + enable_smbus(); + + soc_config_rtc(); +} diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c new file mode 100644 index 0000000..2610940 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci.h> +#include <soc/bootblock.h> +#include <soc/cpu.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> +#include <string.h> + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_SKYLAKE_C0, "Skylake C0" }, + { CPUID_SKYLAKE_D0, "Skylake D0" }, + { CPUID_KABYLAKE_G0, "Kabylake G0" }, + { CPUID_KABYLAKE_H0, "Kabylake H0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { MCH_SKYLAKE_ID_U, "Skylake-U" }, + { MCH_SKYLAKE_ID_Y, "Skylake-Y" }, + { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" }, + { MCH_KABYLAKE_ID_U, "Kabylake-U" }, + { MCH_KABYLAKE_ID_Y, "Kabylake-Y" }, +}; + +static struct { + u16 lpcid; + const char *name; +} pch_table[] = { + { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, + { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, + { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, + { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, + { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, + { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, + { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, + { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, +}; + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index; + char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + const char *mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + } else { + u32 *p = (u32 *) cpu_string; + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + *p++ = cpuidr.eax; + *p++ = cpuidr.ebx; + *p++ = cpuidr.ecx; + *p++ = cpuidr.edx; + } + } + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ') + cpu_name++; + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(0x8B, microcode_ver); + cpuidr = cpuid(1); + microcode_ver = rdmsr(0x8b); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpuidr.eax) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpuidr.eax, cpu_type, microcode_ver.hi); + + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); + u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + u16 lpcid = pch_type(); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].lpcid == lpcid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + lpcid, pch_revision(), pch_type); +} + +static void report_igd_info(void) +{ + int i; + u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c new file mode 100644 index 0000000..bb305d5 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/smbus.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <soc/bootblock.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/smbus.h> + +static const struct reg_script smbus_init_script[] = { + /* Set SMBUS I/O base address */ + REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), + /* Set SMBUS enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +void enable_smbus(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} + diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index e57c369..bacbef8 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -26,9 +26,14 @@ inline void bootblock_fsp_temp_ram_init(void) {} void bootblock_cpu_init(void); void bootblock_pch_early_init(void); void bootblock_systemagent_early_init(void); - void pch_uart_init(void); + /* Bootblock post console init programing */ -void pch_enable_lpc(void); +void enable_smbus(void); +void i2c_early_init(void); +void pch_early_init(void); +void report_platform_info(void); +void report_memory_config(void); +void set_max_freq(void); #endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 71887aa..6c40bd6 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,13 +19,8 @@ #include <fsp/romstage.h> -void i2c_early_init(void); void systemagent_early_init(void); -void pch_early_init(void); void intel_early_me_status(void); -void report_platform_info(void); -void set_max_freq(void); - void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7a13084..31a452f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,17 +1,7 @@ -bootblock-y += cpu.c -bootblock-y += i2c.c -bootblock-y += pch.c -bootblock-y += report_platform.c -bootblock-y += smbus.c verstage-y += power_state.c -romstage-y += cpu.c -romstage-y += i2c.c -romstage-y += pch.c romstage-y += power_state.c -romstage-y += report_platform.c romstage-y += romstage.c -romstage-y += smbus.c romstage-y += spi.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/cpu.c b/src/soc/intel/skylake/romstage/cpu.c deleted file mode 100644 index 1b5db73..0000000 --- a/src/soc/intel/skylake/romstage/cpu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <stdlib.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/romstage.h> - -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -void set_max_freq(void) -{ - msr_t msr, perf_ctl, platform_info; - - /* Check for configurable TDP option */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - - if ((platform_info.hi >> 1) & 3) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - - perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); -} diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c deleted file mode 100644 index f6d1384..0000000 --- a/src/soc/intel/skylake/romstage/i2c.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <commonlib/helpers.h> -#include <device/device.h> -#include <device/i2c.h> -#include <device/pci_def.h> -#include <soc/intel/common/lpss_i2c.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/serialio.h> -#include "chip.h" - -uintptr_t lpss_i2c_base_address(unsigned bus) -{ - int devfn; - pci_devfn_t dev; - - /* Find device+function for this controller */ - devfn = i2c_bus_to_devfn(bus); - if (devfn < 0) - return 0; - - /* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - /* Read the first base address for this device */ - return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); -} - -static void i2c_early_init_bus(unsigned bus) -{ - ROMSTAGE_CONST struct soc_intel_skylake_config *config; - ROMSTAGE_CONST struct device *tree_dev; - const struct lpss_i2c_speed_config *sptr; - enum i2c_speed speed; - pci_devfn_t dev; - int devfn; - uintptr_t base; - uint32_t value; - void *reg; - - /* Find the PCI device for this bus controller */ - devfn = i2c_bus_to_devfn(bus); - if (devfn < 0) - return; - - /* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = dev_find_slot(0, devfn); - if (!tree_dev || !tree_dev->enabled) - return; - - /* Skip if not enabled for early init */ - config = tree_dev->chip_info; - if (!config) - return; - if (!config->i2c[bus].early_init) - return; - - /* Prepare early base address for access before memory */ - base = EARLY_I2C_BASE(bus); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Take device out of reset */ - reg = (void *)(base + SIO_REG_PPR_RESETS); - value = read32(reg); - value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | - SIO_REG_PPR_RESETS_IDMA; - write32(reg, value); - - /* Initialize the controller */ - speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; - lpss_i2c_init(bus, speed); - - /* Apply custom speed config if it has been set by the board */ - for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { - sptr = &config->i2c[bus].speed_config[value]; - if (sptr->speed == speed) { - lpss_i2c_set_speed_config(bus, sptr); - break; - } - } -} - -void i2c_early_init(void) -{ - int bus; - - /* Initialize I2C controllers that are enabled in devicetree */ - for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) - i2c_early_init_bus(bus); -} diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c deleted file mode 100644 index dd52b40..0000000 --- a/src/soc/intel/skylake/romstage/pch.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <chip.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/pmc.h> -#include <soc/romstage.h> -#include <soc/smbus.h> - -/* Max PXRC registers in ITSS*/ -#define MAX_PXRC_CONFIG 0x08 - -static const u8 pch_interrupt_routing[] = { - 11, /* PARC: PIRQA -> IRQ11 */ - 10, /* PBRC: PIRQB -> IRQ10 */ - 11, /* PCRC: PIRQC -> IRQ11 */ - 11, /* PDRC: PIRQD -> IRQ11 */ - 11, /* PERC: PIRQE -> IRQ11 */ - 11, /* PFRC: PIRQF -> IRQ11 */ - 11, /* PGRC: PIRQG -> IRQ11 */ - 11 /* PHRC: PIRQH -> IRQ11 */ -}; - -static void pch_enable_lpc(void) -{ - /* Lookup device tree in romstage */ - const struct device *dev; - const config_t *config; - u16 lpc_en; - - /* IO Decode Range */ - lpc_en = COMA_RANGE | (COMB_RANGE << 4); - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); - - /* IO Decode Enable */ - lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); - - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; - - /* Set in PCI generic decode range registers */ - pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); - - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); -} - -static void pch_interrupt_init(void) -{ - u8 index = 0; - - for (index = 0; index < MAX_PXRC_CONFIG; index++) { - if (pch_interrupt_routing[index] < 16 && - pch_interrupt_routing[index] > 2 && - pch_interrupt_routing[index] != 8 && - pch_interrupt_routing[index] != 13) { - pcr_write8(PID_ITSS, - (R_PCH_PCR_ITSS_PIRQA_ROUT + index), - pch_interrupt_routing[index]); - } - } -} - -static void soc_config_acpibase(void) -{ - uint32_t reg32; - - /* Disable ABASE in PMC Device first before changing Base Address*/ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); - - /* Program ACPI Base */ - pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); - - /* Enable ACPI in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); - - /* - * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] - * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] - */ - reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); -} - -static void soc_config_pwrmbase(void) -{ - uint32_t reg32; - - /* Disable PWRMBASE in PMC Device first before changing Base address */ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); - - /* Program PWRM Base */ - pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); - - /* Enable PWRM in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); - - /* - * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] - * to the same value programmed in PMC PCI Offset 48h bit[31:16], - * this has an implication of making sure the PWRMBASE to be - * 64KB aligned. - * - * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] - * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an - * implication of making sure the memory allocated to PWRMBASE to be 64KB - * in size. - */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, - ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | - (PCH_PWRM_BASE_ADDRESS >> 16))); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); -} - -static void soc_config_tco(void) -{ - uint32_t reg32 = 0; - uint16_t tcobase; - uint16_t tcocnt; - - /* Disable TCO in SMBUS Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~SMBUS_TCO_EN; - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); - - /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); - - /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); - - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - * to [SMBUS PCI offset 50h[15:5], 1]. - */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, - (TCO_BASE_ADDDRESS | (1 << 1))); - - /* Program TCO timer halt */ - tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - tcobase &= ~0x1f; - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - outw(tcocnt, tcobase + TCO1_CNT); -} - -static void soc_config_rtc(void) -{ - /* Enable upper 128 bytes of CMOS */ - pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, - B_PCH_PCR_RTC_CONF_UCMOS_EN); -} - -void pch_early_init(void) -{ - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ - soc_config_acpibase(); - - /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ - soc_config_pwrmbase(); - - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - soc_config_tco(); - - /* - * Interrupt Configuration Register Programming - * PIRQx to IRQ Programming - */ - pch_interrupt_init(); - - /* Program generic IO Decode Range */ - pch_enable_lpc(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - enable_smbus(); - - soc_config_rtc(); -} diff --git a/src/soc/intel/skylake/romstage/report_platform.c b/src/soc/intel/skylake/romstage/report_platform.c deleted file mode 100644 index e841359..0000000 --- a/src/soc/intel/skylake/romstage/report_platform.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <device/pci.h> -#include <soc/cpu.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> -#include <string.h> - -static struct { - u32 cpuid; - const char *name; -} cpu_table[] = { - { CPUID_SKYLAKE_C0, "Skylake C0" }, - { CPUID_SKYLAKE_D0, "Skylake D0" }, - { CPUID_KABYLAKE_G0, "Kabylake G0" }, - { CPUID_KABYLAKE_H0, "Kabylake H0" }, -}; - -static struct { - u16 mchid; - const char *name; -} mch_table[] = { - { MCH_SKYLAKE_ID_U, "Skylake-U" }, - { MCH_SKYLAKE_ID_Y, "Skylake-Y" }, - { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" }, - { MCH_KABYLAKE_ID_U, "Kabylake-U" }, - { MCH_KABYLAKE_ID_Y, "Kabylake-Y" }, -}; - -static struct { - u16 lpcid; - const char *name; -} pch_table[] = { - { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, - { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, - { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, - { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, - { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, - { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, -}; - -static struct { - u16 igdid; - const char *name; -} igd_table[] = { - { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, - { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, - { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, -}; - -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - msr_t microcode_ver; - const char *mode[] = {"NOT ", ""}; - const char *cpu_type = "Unknown"; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32 *) cpu_string; - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(0x8B, microcode_ver); - cpuidr = cpuid(1); - microcode_ver = rdmsr(0x8b); - - /* Look for string to match the name */ - for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { - cpu_type = cpu_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); - printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpuidr.eax, cpu_type, microcode_ver.hi); - - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - -static void report_mch_info(void) -{ - int i; - u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); - const char *mch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(mch_table); i++) { - if (mch_table[i].mchid == mchid) { - mch_type = mch_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", - mchid, mch_revision, mch_type); -} - -static void report_pch_info(void) -{ - int i; - u16 lpcid = pch_type(); - const char *pch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { - pch_type = pch_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, pch_revision(), pch_type); -} - -static void report_igd_info(void) -{ - int i; - u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); - const char *igd_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(igd_table); i++) { - if (igd_table[i].igdid == igdid) { - igd_type = igd_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", - igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); -} - -void report_platform_info(void) -{ - report_cpu_info(); - report_mch_info(); - report_pch_info(); - report_igd_info(); -} - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/soc/intel/skylake/romstage/smbus.c b/src/soc/intel/skylake/romstage/smbus.c deleted file mode 100644 index ca9c6ad..0000000 --- a/src/soc/intel/skylake/romstage/smbus.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> -#include <soc/romstage.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void enable_smbus(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address); -}

1 0

Patch set updated for coreboot: soc/intel/skylake: Move bootblock specific code from skylake/romstage
by Rizwan Qureshi 18 Aug '16

18 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16225 -gerrit commit 08f6b19edaddeeafb20cfe44d070fdcb091f6fb9 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Aug 11 14:56:28 2016 +0530 soc/intel/skylake: Move bootblock specific code from skylake/romstage There is a lot of code that is being referred to in bootblock but resides under skylake/romstage folder. Hence move this code into skylake/bootblock, and update the relevant header files and Makefiles. TEST=Build and Boot kunimitsu. Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 5 +- src/soc/intel/skylake/bootblock/bootblock.c | 1 - src/soc/intel/skylake/bootblock/cpu.c | 26 +++ src/soc/intel/skylake/bootblock/i2c.c | 109 +++++++++++ src/soc/intel/skylake/bootblock/pch.c | 205 +++++++++++++++++++- src/soc/intel/skylake/bootblock/report_platform.c | 222 ++++++++++++++++++++++ src/soc/intel/skylake/bootblock/smbus.c | 47 +++++ src/soc/intel/skylake/include/soc/bootblock.h | 9 +- src/soc/intel/skylake/include/soc/romstage.h | 5 - src/soc/intel/skylake/romstage/Makefile.inc | 10 - src/soc/intel/skylake/romstage/cpu.c | 52 ----- src/soc/intel/skylake/romstage/i2c.c | 109 ----------- src/soc/intel/skylake/romstage/pch.c | 221 --------------------- src/soc/intel/skylake/romstage/report_platform.c | 222 ---------------------- src/soc/intel/skylake/romstage/smbus.c | 51 ----- 15 files changed, 618 insertions(+), 676 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 7b27c57..98f2718 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -12,16 +12,19 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += bootblock/smbus.c bootblock-y += bootblock/systemagent.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c bootblock-y += monotonic_timer.c bootblock-y += pch.c bootblock-y += pcr.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index f644d1f..b00fcf7 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -15,7 +15,6 @@ #include <bootblock_common.h> #include <soc/bootblock.h> -#include <soc/romstage.h> void asmlinkage bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 8c1e58a..3cea8bd 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -17,9 +17,11 @@ #include <stdint.h> #include <delay.h> #include <arch/io.h> +#include <console/console.h> #include <cpu/intel/microcode/microcode.c> #include <reset.h> #include <soc/bootblock.h> +#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -105,3 +107,27 @@ void bootblock_cpu_init(void) set_flex_ratio_to_tdp_nominal(); intel_update_microcode_from_cbfs(); } + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c new file mode 100644 index 0000000..64b1fb5 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/i2c.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/bootblock.h> +#include <soc/serialio.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + int devfn; + pci_devfn_t dev; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return 0; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + pci_devfn_t dev; + int devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return; + + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) + return; + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config) + return; + if (!config->i2c[bus].early_init) + return; + + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + SIO_REG_PPR_RESETS); + value = read32(reg); + value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(reg, value); + + /* Initialize the controller */ + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { + sptr = &config->i2c[bus].speed_config[value]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } +} + +void i2c_early_init(void) +{ + int bus; + + /* Initialize I2C controllers that are enabled in devicetree */ + for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) + i2c_early_init_bus(bus); +} diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index e7f414b..22ab109 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -15,13 +15,22 @@ * GNU General Public License for more details. */ #include <arch/io.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/p2sb.h> +#include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr.h> -#include <soc/spi.h> +#include <soc/pm.h> +#include <soc/pmc.h> +#include <soc/smbus.h> + +/* Max PXRC registers in ITSS*/ +#define MAX_PXRC_CONFIG 0x08 /* * Enable Prefetching and Caching. @@ -65,7 +74,6 @@ static void enable_p2sbbar(void) /* Enable P2SB MSE */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* * Enable decoding for HPET memory address range. * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode @@ -81,3 +89,196 @@ void bootblock_pch_early_init(void) enable_spi_prefetch(); enable_p2sbbar(); } + +static void pch_enable_lpc(void) +{ + /* Lookup device tree in romstage */ + const struct device *dev; + const config_t *config; + u16 lpc_en; + + /* IO Decode Range */ + lpc_en = COMA_RANGE | (COMB_RANGE << 4); + pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); + + /* IO Decode Enable */ + lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + /* Set in PCI generic decode range registers */ + pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); + + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); +} + +static void pch_interrupt_init(void) +{ + const struct device *dev; + const config_t *config; + u8 index = 0; + u8 pch_interrupt_routing[MAX_PXRC_CONFIG]; + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pch_interrupt_routing[0] = config->pirqa_routing; + pch_interrupt_routing[1] = config->pirqb_routing; + pch_interrupt_routing[2] = config->pirqc_routing; + pch_interrupt_routing[3] = config->pirqd_routing; + pch_interrupt_routing[4] = config->pirqe_routing; + pch_interrupt_routing[5] = config->pirqf_routing; + pch_interrupt_routing[6] = config->pirqg_routing; + pch_interrupt_routing[7] = config->pirqh_routing; + + for (index = 0; index < MAX_PXRC_CONFIG; index++) { + if (pch_interrupt_routing[index] < 16 && + pch_interrupt_routing[index] > 2 && + pch_interrupt_routing[index] != 8 && + pch_interrupt_routing[index] != 13) { + pcr_write8(PID_ITSS, + (R_PCH_PCR_ITSS_PIRQA_ROUT + index), + pch_interrupt_routing[index]); + } + } +} + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); +} + +static void soc_config_pwrmbase(void) +{ + uint32_t reg32; + + /* Disable PWRMBASE in PMC Device first before changing Base address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable PWRM in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); + + /* + * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] + * to the same value programmed in PMC PCI Offset 48h bit[31:16], + * this has an implication of making sure the PWRMBASE to be + * 64KB aligned. + * + * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] + * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an + * implication of making sure the memory allocated to PWRMBASE to be 64KB + * in size. + */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, + ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | + (PCH_PWRM_BASE_ADDRESS >> 16))); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); +} + +static void soc_config_tco(void) +{ + uint32_t reg32 = 0; + uint16_t tcobase; + uint16_t tcocnt; + + /* Disable TCO in SMBUS Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); + reg32 &= ~SMBUS_TCO_EN; + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); + + /* Program TCO Base */ + pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); + + /* Enable TCO in SMBUS */ + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); + + /* + * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] + * to [SMBUS PCI offset 50h[15:5], 1]. + */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, + (TCO_BASE_ADDDRESS | (1 << 1))); + + /* Program TCO timer halt */ + tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); + tcobase &= ~0x1f; + tcocnt = inw(tcobase + TCO1_CNT); + tcocnt |= TCO_TMR_HLT; + outw(tcocnt, tcobase + TCO1_CNT); +} + +static void soc_config_rtc(void) +{ + /* Enable upper 128 bytes of CMOS */ + pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, + B_PCH_PCR_RTC_CONF_UCMOS_EN); +} + +void pch_early_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + soc_config_tco(); + + /* + * Interrupt Configuration Register Programming + * PIRQx to IRQ Programming + */ + pch_interrupt_init(); + + /* Program generic IO Decode Range */ + pch_enable_lpc(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + enable_smbus(); + + soc_config_rtc(); +} diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c new file mode 100644 index 0000000..2610940 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci.h> +#include <soc/bootblock.h> +#include <soc/cpu.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> +#include <string.h> + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_SKYLAKE_C0, "Skylake C0" }, + { CPUID_SKYLAKE_D0, "Skylake D0" }, + { CPUID_KABYLAKE_G0, "Kabylake G0" }, + { CPUID_KABYLAKE_H0, "Kabylake H0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { MCH_SKYLAKE_ID_U, "Skylake-U" }, + { MCH_SKYLAKE_ID_Y, "Skylake-Y" }, + { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" }, + { MCH_KABYLAKE_ID_U, "Kabylake-U" }, + { MCH_KABYLAKE_ID_Y, "Kabylake-Y" }, +}; + +static struct { + u16 lpcid; + const char *name; +} pch_table[] = { + { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, + { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, + { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, + { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, + { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, + { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, + { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, + { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, +}; + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index; + char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + const char *mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + } else { + u32 *p = (u32 *) cpu_string; + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + *p++ = cpuidr.eax; + *p++ = cpuidr.ebx; + *p++ = cpuidr.ecx; + *p++ = cpuidr.edx; + } + } + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ') + cpu_name++; + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(0x8B, microcode_ver); + cpuidr = cpuid(1); + microcode_ver = rdmsr(0x8b); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpuidr.eax) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpuidr.eax, cpu_type, microcode_ver.hi); + + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); + u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + u16 lpcid = pch_type(); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].lpcid == lpcid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + lpcid, pch_revision(), pch_type); +} + +static void report_igd_info(void) +{ + int i; + u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c new file mode 100644 index 0000000..bb305d5 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/smbus.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <soc/bootblock.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/smbus.h> + +static const struct reg_script smbus_init_script[] = { + /* Set SMBUS I/O base address */ + REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), + /* Set SMBUS enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +void enable_smbus(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} + diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index e57c369..bacbef8 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -26,9 +26,14 @@ inline void bootblock_fsp_temp_ram_init(void) {} void bootblock_cpu_init(void); void bootblock_pch_early_init(void); void bootblock_systemagent_early_init(void); - void pch_uart_init(void); + /* Bootblock post console init programing */ -void pch_enable_lpc(void); +void enable_smbus(void); +void i2c_early_init(void); +void pch_early_init(void); +void report_platform_info(void); +void report_memory_config(void); +void set_max_freq(void); #endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 71887aa..6c40bd6 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,13 +19,8 @@ #include <fsp/romstage.h> -void i2c_early_init(void); void systemagent_early_init(void); -void pch_early_init(void); void intel_early_me_status(void); -void report_platform_info(void); -void set_max_freq(void); - void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7a13084..31a452f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,17 +1,7 @@ -bootblock-y += cpu.c -bootblock-y += i2c.c -bootblock-y += pch.c -bootblock-y += report_platform.c -bootblock-y += smbus.c verstage-y += power_state.c -romstage-y += cpu.c -romstage-y += i2c.c -romstage-y += pch.c romstage-y += power_state.c -romstage-y += report_platform.c romstage-y += romstage.c -romstage-y += smbus.c romstage-y += spi.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/cpu.c b/src/soc/intel/skylake/romstage/cpu.c deleted file mode 100644 index 1b5db73..0000000 --- a/src/soc/intel/skylake/romstage/cpu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <stdlib.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/romstage.h> - -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -void set_max_freq(void) -{ - msr_t msr, perf_ctl, platform_info; - - /* Check for configurable TDP option */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - - if ((platform_info.hi >> 1) & 3) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - - perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); -} diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c deleted file mode 100644 index f6d1384..0000000 --- a/src/soc/intel/skylake/romstage/i2c.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <commonlib/helpers.h> -#include <device/device.h> -#include <device/i2c.h> -#include <device/pci_def.h> -#include <soc/intel/common/lpss_i2c.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/serialio.h> -#include "chip.h" - -uintptr_t lpss_i2c_base_address(unsigned bus) -{ - int devfn; - pci_devfn_t dev; - - /* Find device+function for this controller */ - devfn = i2c_bus_to_devfn(bus); - if (devfn < 0) - return 0; - - /* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - /* Read the first base address for this device */ - return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); -} - -static void i2c_early_init_bus(unsigned bus) -{ - ROMSTAGE_CONST struct soc_intel_skylake_config *config; - ROMSTAGE_CONST struct device *tree_dev; - const struct lpss_i2c_speed_config *sptr; - enum i2c_speed speed; - pci_devfn_t dev; - int devfn; - uintptr_t base; - uint32_t value; - void *reg; - - /* Find the PCI device for this bus controller */ - devfn = i2c_bus_to_devfn(bus); - if (devfn < 0) - return; - - /* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = dev_find_slot(0, devfn); - if (!tree_dev || !tree_dev->enabled) - return; - - /* Skip if not enabled for early init */ - config = tree_dev->chip_info; - if (!config) - return; - if (!config->i2c[bus].early_init) - return; - - /* Prepare early base address for access before memory */ - base = EARLY_I2C_BASE(bus); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Take device out of reset */ - reg = (void *)(base + SIO_REG_PPR_RESETS); - value = read32(reg); - value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | - SIO_REG_PPR_RESETS_IDMA; - write32(reg, value); - - /* Initialize the controller */ - speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; - lpss_i2c_init(bus, speed); - - /* Apply custom speed config if it has been set by the board */ - for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { - sptr = &config->i2c[bus].speed_config[value]; - if (sptr->speed == speed) { - lpss_i2c_set_speed_config(bus, sptr); - break; - } - } -} - -void i2c_early_init(void) -{ - int bus; - - /* Initialize I2C controllers that are enabled in devicetree */ - for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) - i2c_early_init_bus(bus); -} diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c deleted file mode 100644 index dd52b40..0000000 --- a/src/soc/intel/skylake/romstage/pch.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <chip.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/pmc.h> -#include <soc/romstage.h> -#include <soc/smbus.h> - -/* Max PXRC registers in ITSS*/ -#define MAX_PXRC_CONFIG 0x08 - -static const u8 pch_interrupt_routing[] = { - 11, /* PARC: PIRQA -> IRQ11 */ - 10, /* PBRC: PIRQB -> IRQ10 */ - 11, /* PCRC: PIRQC -> IRQ11 */ - 11, /* PDRC: PIRQD -> IRQ11 */ - 11, /* PERC: PIRQE -> IRQ11 */ - 11, /* PFRC: PIRQF -> IRQ11 */ - 11, /* PGRC: PIRQG -> IRQ11 */ - 11 /* PHRC: PIRQH -> IRQ11 */ -}; - -static void pch_enable_lpc(void) -{ - /* Lookup device tree in romstage */ - const struct device *dev; - const config_t *config; - u16 lpc_en; - - /* IO Decode Range */ - lpc_en = COMA_RANGE | (COMB_RANGE << 4); - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); - - /* IO Decode Enable */ - lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); - - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; - - /* Set in PCI generic decode range registers */ - pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); - - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); -} - -static void pch_interrupt_init(void) -{ - u8 index = 0; - - for (index = 0; index < MAX_PXRC_CONFIG; index++) { - if (pch_interrupt_routing[index] < 16 && - pch_interrupt_routing[index] > 2 && - pch_interrupt_routing[index] != 8 && - pch_interrupt_routing[index] != 13) { - pcr_write8(PID_ITSS, - (R_PCH_PCR_ITSS_PIRQA_ROUT + index), - pch_interrupt_routing[index]); - } - } -} - -static void soc_config_acpibase(void) -{ - uint32_t reg32; - - /* Disable ABASE in PMC Device first before changing Base Address*/ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); - - /* Program ACPI Base */ - pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); - - /* Enable ACPI in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); - - /* - * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] - * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] - */ - reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); -} - -static void soc_config_pwrmbase(void) -{ - uint32_t reg32; - - /* Disable PWRMBASE in PMC Device first before changing Base address */ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); - - /* Program PWRM Base */ - pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); - - /* Enable PWRM in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); - - /* - * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] - * to the same value programmed in PMC PCI Offset 48h bit[31:16], - * this has an implication of making sure the PWRMBASE to be - * 64KB aligned. - * - * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] - * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an - * implication of making sure the memory allocated to PWRMBASE to be 64KB - * in size. - */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, - ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | - (PCH_PWRM_BASE_ADDRESS >> 16))); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); -} - -static void soc_config_tco(void) -{ - uint32_t reg32 = 0; - uint16_t tcobase; - uint16_t tcocnt; - - /* Disable TCO in SMBUS Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~SMBUS_TCO_EN; - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); - - /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); - - /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); - - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - * to [SMBUS PCI offset 50h[15:5], 1]. - */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, - (TCO_BASE_ADDDRESS | (1 << 1))); - - /* Program TCO timer halt */ - tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - tcobase &= ~0x1f; - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - outw(tcocnt, tcobase + TCO1_CNT); -} - -static void soc_config_rtc(void) -{ - /* Enable upper 128 bytes of CMOS */ - pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, - B_PCH_PCR_RTC_CONF_UCMOS_EN); -} - -void pch_early_init(void) -{ - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ - soc_config_acpibase(); - - /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ - soc_config_pwrmbase(); - - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - soc_config_tco(); - - /* - * Interrupt Configuration Register Programming - * PIRQx to IRQ Programming - */ - pch_interrupt_init(); - - /* Program generic IO Decode Range */ - pch_enable_lpc(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - enable_smbus(); - - soc_config_rtc(); -} diff --git a/src/soc/intel/skylake/romstage/report_platform.c b/src/soc/intel/skylake/romstage/report_platform.c deleted file mode 100644 index e841359..0000000 --- a/src/soc/intel/skylake/romstage/report_platform.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <device/pci.h> -#include <soc/cpu.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> -#include <string.h> - -static struct { - u32 cpuid; - const char *name; -} cpu_table[] = { - { CPUID_SKYLAKE_C0, "Skylake C0" }, - { CPUID_SKYLAKE_D0, "Skylake D0" }, - { CPUID_KABYLAKE_G0, "Kabylake G0" }, - { CPUID_KABYLAKE_H0, "Kabylake H0" }, -}; - -static struct { - u16 mchid; - const char *name; -} mch_table[] = { - { MCH_SKYLAKE_ID_U, "Skylake-U" }, - { MCH_SKYLAKE_ID_Y, "Skylake-Y" }, - { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" }, - { MCH_KABYLAKE_ID_U, "Kabylake-U" }, - { MCH_KABYLAKE_ID_Y, "Kabylake-Y" }, -}; - -static struct { - u16 lpcid; - const char *name; -} pch_table[] = { - { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, - { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, - { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, - { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, - { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, - { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, -}; - -static struct { - u16 igdid; - const char *name; -} igd_table[] = { - { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, - { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, - { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, -}; - -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - msr_t microcode_ver; - const char *mode[] = {"NOT ", ""}; - const char *cpu_type = "Unknown"; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32 *) cpu_string; - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(0x8B, microcode_ver); - cpuidr = cpuid(1); - microcode_ver = rdmsr(0x8b); - - /* Look for string to match the name */ - for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { - cpu_type = cpu_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); - printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpuidr.eax, cpu_type, microcode_ver.hi); - - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - -static void report_mch_info(void) -{ - int i; - u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); - const char *mch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(mch_table); i++) { - if (mch_table[i].mchid == mchid) { - mch_type = mch_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", - mchid, mch_revision, mch_type); -} - -static void report_pch_info(void) -{ - int i; - u16 lpcid = pch_type(); - const char *pch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { - pch_type = pch_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, pch_revision(), pch_type); -} - -static void report_igd_info(void) -{ - int i; - u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); - const char *igd_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(igd_table); i++) { - if (igd_table[i].igdid == igdid) { - igd_type = igd_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", - igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); -} - -void report_platform_info(void) -{ - report_cpu_info(); - report_mch_info(); - report_pch_info(); - report_igd_info(); -} - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/soc/intel/skylake/romstage/smbus.c b/src/soc/intel/skylake/romstage/smbus.c deleted file mode 100644 index ca9c6ad..0000000 --- a/src/soc/intel/skylake/romstage/smbus.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> -#include <soc/romstage.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void enable_smbus(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address); -}

1 0

Patch set updated for coreboot: soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
by Ravishankar Sarawadi 18 Aug '16

18 Aug '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16246 -gerrit commit fdace469be47657fdf3fe0ae0023848328a3debc Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Aug 17 23:44:56 2016 -0700 soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB Read FSP produced memory HOB and use it to populate DIMM info. DIMM 'part_num' info is stored statically based on memory/SKU id. CQ-DEPEND=CL:16245 BUG = chrome-os-partner:55505 Test = 'dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/mainboard/google/reef/romstage.c | 29 +++++++- src/soc/intel/apollolake/include/soc/meminit.h | 2 + src/soc/intel/apollolake/include/soc/romstage.h | 1 + src/soc/intel/apollolake/meminit.c | 91 ++++++++++++++++++++++++- src/soc/intel/apollolake/romstage.c | 8 +++ 5 files changed, 127 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index f9743b5..6ca6b5a 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,9 +13,16 @@ * GNU General Public License for more details. */ +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> #include <gpio.h> +#include <memory_info.h> +#include <smbios.h> +#include <soc/fsp/FspmUpd.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include <string.h> #include "gpio.h" static const struct lpddr4_swizzle_cfg board_swizzle = { @@ -82,12 +89,14 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", }, /* K4F8E304HB-MGCJ - both logical channels */ [1] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", }, /* * MT53B512M32D2NP-062WT:C - both logical channels. While the parts @@ -100,18 +109,21 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCH", }, }; @@ -121,9 +133,8 @@ static const struct lpddr4_cfg lp4cfg = { .swizzle_config = &board_swizzle, }; -void mainboard_memory_init_params(struct FSPM_UPD *memupd) +static int get_mem_sku(void) { - int mem_sku; gpio_t pads[] = { [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, @@ -133,7 +144,19 @@ void mainboard_memory_init_params(struct FSPM_UPD *memupd) * Read memory SKU id with internal pullups enabled to handle * proto boards with no SKU id pins. */ - mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +} + +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + int mem_sku = get_mem_sku(); meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); } + +void mainboard_save_dimm_info(void) +{ + int mem_sku = get_mem_sku(); + + save_dimm_info(&lp4cfg, mem_sku); +} diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index a7da1ac..e42acb3 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -101,6 +101,7 @@ struct lpddr4_sku { int ch1_rank_density; int ch0_dual_rank; int ch1_dual_rank; + const char *part_num; }; struct lpddr4_cfg { @@ -115,5 +116,6 @@ struct lpddr4_cfg { */ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, const struct lpddr4_cfg *lpcfg, size_t sku_id); +void save_dimm_info(const struct lpddr4_cfg *lpcfg, int mem_sku); #endif /* _SOC_APOLLOLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index e7ee335..5b76f65 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -22,5 +22,6 @@ #include <fsp/api.h> void mainboard_memory_init_params(struct FSPM_UPD *mupd); +void mainboard_save_dimm_info(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 92b84c8..84f30f1 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -12,8 +12,11 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <cbmem.h> #include <console/console.h> +#include <fsp/util.h> +#include <memory_info.h> +#include <smbios.h> #include <soc/meminit.h> #include <stddef.h> /* required for FspmUpd.h */ #include <soc/fsp/FspmUpd.h> @@ -252,3 +255,89 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, lpcfg->swizzle_config); } } + +void save_dimm_info(const struct lpddr4_cfg *lp4cfg, int mem_sku) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + struct DIMM_INFO *dimm_info; + struct memory_info *mem_info; + struct CHANNEL_INFO *channel_info; + struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + if (mem_sku >= lp4cfg->num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + mem_sku, lp4cfg->num_skus); + return; + } + + memory_info_hob = (struct FSP_SMBIOS_MEMORY_INFO *) + fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &memory_info_hob->ChannelInfo[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + dimm_info = &channel_info->DimmInfo[dimm]; + + if (!dimm_info->SizeInMb) + continue; + + /* Populate the DIMM information */ + mem_info->dimm[index].dimm_size = dimm_info->SizeInMb; + mem_info->dimm[index].ddr_type = memory_info_hob->MemoryType; + mem_info->dimm[index].ddr_frequency = + memory_info_hob->MemoryFrequencyInMHz; + mem_info->dimm[index].channel_num = channel_info->ChannelId; + mem_info->dimm[index].dimm_num = dimm_info->DimmId; + memcpy(mem_info->dimm[index].module_part_number, + lp4cfg->skus[mem_sku].part_num, + sizeof(mem_info->dimm[index].module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_8; + break; + + case 16: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_16; + break; + + case 32: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_32; + break; + + case 64: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_64; + break; + + case 128: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_128; + break; + + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8f17fdd..d631192 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -118,6 +118,8 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + mainboard_save_dimm_info(); + /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache @@ -169,6 +171,12 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } +__attribute__ ((weak)) +void mainboard_save_dimm_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + int get_sw_write_protect_state(void) { uint8_t status;

1 0

New patch to review for coreboot: soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
by Ravishankar Sarawadi 18 Aug '16

18 Aug '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16246 -gerrit commit 3afd1dfe50fd242915c8fe1e3a0c41daef7644e6 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Aug 17 23:44:56 2016 -0700 soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB Read FSP produced memory HOB and use it to populate DIMM info. DIMM 'part_num' info is stored statically based on memory/SKU id. CQ-DEPEND=CL:16245 BUG = chrome-os-partner:55505 Test = 'dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/mainboard/google/reef/romstage.c | 29 +++++++- src/soc/intel/apollolake/include/soc/meminit.h | 2 + src/soc/intel/apollolake/include/soc/romstage.h | 1 + src/soc/intel/apollolake/meminit.c | 91 ++++++++++++++++++++++++- src/soc/intel/apollolake/romstage.c | 8 +++ 5 files changed, 127 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index f9743b5..6ca6b5a 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -13,9 +13,16 @@ * GNU General Public License for more details. */ +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> #include <gpio.h> +#include <memory_info.h> +#include <smbios.h> +#include <soc/fsp/FspmUpd.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include <string.h> #include "gpio.h" static const struct lpddr4_swizzle_cfg board_swizzle = { @@ -82,12 +89,14 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", }, /* K4F8E304HB-MGCJ - both logical channels */ [1] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", }, /* * MT53B512M32D2NP-062WT:C - both logical channels. While the parts @@ -100,18 +109,21 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCH", }, }; @@ -121,9 +133,8 @@ static const struct lpddr4_cfg lp4cfg = { .swizzle_config = &board_swizzle, }; -void mainboard_memory_init_params(struct FSPM_UPD *memupd) +static int get_mem_sku(void) { - int mem_sku; gpio_t pads[] = { [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, @@ -133,7 +144,19 @@ void mainboard_memory_init_params(struct FSPM_UPD *memupd) * Read memory SKU id with internal pullups enabled to handle * proto boards with no SKU id pins. */ - mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +} + +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + int mem_sku = get_mem_sku(); meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku); } + +void mainboard_save_dimm_info(void) +{ + int mem_sku = get_mem_sku(); + + save_dimm_info(&lp4cfg, mem_sku); +} diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index a7da1ac..e42acb3 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -101,6 +101,7 @@ struct lpddr4_sku { int ch1_rank_density; int ch0_dual_rank; int ch1_dual_rank; + const char *part_num; }; struct lpddr4_cfg { @@ -115,5 +116,6 @@ struct lpddr4_cfg { */ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, const struct lpddr4_cfg *lpcfg, size_t sku_id); +void save_dimm_info(const struct lpddr4_cfg *lpcfg, int mem_sku); #endif /* _SOC_APOLLOLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index e7ee335..5b76f65 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -22,5 +22,6 @@ #include <fsp/api.h> void mainboard_memory_init_params(struct FSPM_UPD *mupd); +void mainboard_save_dimm_info(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 92b84c8..b6b610c 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -12,8 +12,11 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <cbmem.h> #include <console/console.h> +#include <fsp/util.h> +#include <memory_info.h> +#include <smbios.h> #include <soc/meminit.h> #include <stddef.h> /* required for FspmUpd.h */ #include <soc/fsp/FspmUpd.h> @@ -252,3 +255,89 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, lpcfg->swizzle_config); } } + +void save_dimm_info(const struct lpddr4_cfg *lp4cfg, int mem_sku) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + struct DIMM_INFO *dimm_info; + struct memory_info *mem_info; + struct CHANNEL_INFO *channel_info; + struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + if (mem_sku >= lp4cfg->num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + mem_sku, lp4cfg->num_skus); + return; + } + + memory_info_hob = (struct FSP_SMBIOS_MEMORY_INFO *) + fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &memory_info_hob->ChannelInfo[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + dimm_info = &channel_info->DimmInfo[dimm]; + + if (dimm_info->SizeInMb) + continue; + + /* Populate the DIMM information */ + mem_info->dimm[index].dimm_size = dimm_info->SizeInMb; + mem_info->dimm[index].ddr_type = memory_info_hob->MemoryType; + mem_info->dimm[index].ddr_frequency = + memory_info_hob->MemoryFrequencyInMHz; + mem_info->dimm[index].channel_num = channel_info->ChannelId; + mem_info->dimm[index].dimm_num = dimm_info->DimmId; + memcpy(mem_info->dimm[index].module_part_number, + lp4cfg->skus[mem_sku].part_num, + sizeof(mem_info->dimm[index].module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_8; + break; + + case 16: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_16; + break; + + case 32: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_32; + break; + + case 64: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_64; + break; + + case 128: + mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_128; + break; + + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8f17fdd..d631192 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -118,6 +118,8 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + mainboard_save_dimm_info(); + /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache @@ -169,6 +171,12 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } +__attribute__ ((weak)) +void mainboard_save_dimm_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + int get_sw_write_protect_state(void) { uint8_t status;

1 0

New patch to review for coreboot: drivers/intel/fsp2_0: Add SMBIOS memory HOB support
by Ravishankar Sarawadi 18 Aug '16

18 Aug '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16245 -gerrit commit 7daab00af8e04560bfec81e2a749d883c8f65016 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Aug 17 23:39:37 2016 -0700 drivers/intel/fsp2_0: Add SMBIOS memory HOB support Add SMBIOS memory GUID and functions to retrieve HOB. BUG = chrome-os-partner:55505 Test = 'dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ie7e2239bb691c748d9fd852c3dc8cdc05243b164 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 14 ++++++++++++-- src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 0dd4a52..17adf46 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -45,8 +45,13 @@ const uint8_t fsp_reserved_memory_guid[16] = { }; const uint8_t fsp_nv_storage_guid[16] = { - 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c, - 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 + 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c, + 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 +}; + +const uint8_t smbios_memory_info_guid[16] = { + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 }; /* @@ -218,3 +223,8 @@ const void *fsp_find_nv_storage_data(size_t *size) { return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); } + +const void *fsp_find_smbios_memory_info(size_t *size) +{ + return fsp_find_extension_hob_by_guid(smbios_memory_info_guid, size); +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ba465ea..269bb02 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -61,6 +61,7 @@ const void *fsp_get_hob_list(void); void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); +const void *fsp_find_smbios_memory_info(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); int fsp_find_reserved_memory(struct range_entry *re);

1 0

Patch set updated for coreboot: soc/intel/skylake: Correct Cache as ram size
by Martin Roth 17 Aug '16

17 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16236 -gerrit commit 0db6b6ca08d5198f027e631d159fd9688b04c9e9 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sun Aug 14 15:48:33 2016 +0530 soc/intel/skylake: Correct Cache as ram size DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000 is used to calculate the _car_region_end in car.ld. If the FSP CAR requirement is greater than or even close to DCACHE_RAM_SIZE then, the CAR region for FSP will be determined to be below the overall CAR region boundary i.e, out of CAR memory range. This is working with FSP 1.1 because we provide the FspCarSize and FspCarBase explicitly in a UPD. Hence, FSP is still able to use the upper region of CAR memory for its purpose. However, it will be a problem in case of FSP2.0 where FSP usable CAR is calculated using _car_region_end. So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB) Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 6 +----- src/soc/intel/skylake/bootblock/cache_as_ram.S | 4 ++-- src/soc/intel/skylake/romstage/romstage.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8c8b1b7..3df4bd7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,7 +84,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x10000 + default 0x40000 help The size of the cache-as-ram region required during bootblock and/or romstage. @@ -199,10 +199,6 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. -config DCACHE_RAM_SIZE_TOTAL - hex - default 0x40000 - config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 89a3cf0..3f8f0f0 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -116,7 +116,7 @@ clear_var_mtrr: /* Configure the MTRR mask for the size region */ mov $MTRR_PHYS_MASK(0), %ecx - mov $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax /* size mask */ + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ dec %eax not %eax or $MTRR_PHYS_MASK_VALID, %eax @@ -216,7 +216,7 @@ find_llc_subleaf: wrmsr movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx + movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx movl $CACHE_INIT_VALUE, %eax cld diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fda6087..0ec2f99 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -93,7 +93,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->DdrFreqLimit = config->DdrFreqLimit; if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } }

1 0

Patch set updated for coreboot: soc/intel/skylake: Move bootblock specific code from skylake/romstage
by Martin Roth 17 Aug '16

17 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16225 -gerrit commit 243ad6e0c41f0b8686ffd5ad8fa848cac33e42a9 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Aug 11 14:56:28 2016 +0530 soc/intel/skylake: Move bootblock specific code from skylake/romstage There is a lot of code that is being referred to in bootblock but resides under skylake/romstage folder. Hence move this code into skylake/bootblock, and update the relevant header files and Makefiles. TEST=Build and Boot kunimitsu. Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 5 +- src/soc/intel/skylake/bootblock/bootblock.c | 1 - src/soc/intel/skylake/bootblock/cpu.c | 26 +++ src/soc/intel/skylake/bootblock/i2c.c | 109 +++++++++++ src/soc/intel/skylake/bootblock/pch.c | 205 +++++++++++++++++++- src/soc/intel/skylake/bootblock/report_platform.c | 222 ++++++++++++++++++++++ src/soc/intel/skylake/bootblock/smbus.c | 47 +++++ src/soc/intel/skylake/include/soc/bootblock.h | 9 +- src/soc/intel/skylake/include/soc/romstage.h | 5 - src/soc/intel/skylake/romstage/Makefile.inc | 10 - src/soc/intel/skylake/romstage/cpu.c | 52 ----- src/soc/intel/skylake/romstage/i2c.c | 109 ----------- src/soc/intel/skylake/romstage/pch.c | 221 --------------------- src/soc/intel/skylake/romstage/report_platform.c | 222 ---------------------- src/soc/intel/skylake/romstage/smbus.c | 51 ----- 15 files changed, 618 insertions(+), 676 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 7b27c57..98f2718 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -12,16 +12,19 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += bootblock/smbus.c bootblock-y += bootblock/systemagent.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c bootblock-y += monotonic_timer.c bootblock-y += pch.c bootblock-y += pcr.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index f644d1f..b00fcf7 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -15,7 +15,6 @@ #include <bootblock_common.h> #include <soc/bootblock.h> -#include <soc/romstage.h> void asmlinkage bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 8c1e58a..3cea8bd 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -17,9 +17,11 @@ #include <stdint.h> #include <delay.h> #include <arch/io.h> +#include <console/console.h> #include <cpu/intel/microcode/microcode.c> #include <reset.h> #include <soc/bootblock.h> +#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -105,3 +107,27 @@ void bootblock_cpu_init(void) set_flex_ratio_to_tdp_nominal(); intel_update_microcode_from_cbfs(); } + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c new file mode 100644 index 0000000..64b1fb5 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/i2c.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/bootblock.h> +#include <soc/serialio.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + int devfn; + pci_devfn_t dev; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return 0; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + pci_devfn_t dev; + int devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return; + + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) + return; + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config) + return; + if (!config->i2c[bus].early_init) + return; + + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + SIO_REG_PPR_RESETS); + value = read32(reg); + value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(reg, value); + + /* Initialize the controller */ + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { + sptr = &config->i2c[bus].speed_config[value]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } +} + +void i2c_early_init(void) +{ + int bus; + + /* Initialize I2C controllers that are enabled in devicetree */ + for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) + i2c_early_init_bus(bus); +} diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index e7f414b..a923031 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -15,13 +15,22 @@ * GNU General Public License for more details. */ #include <arch/io.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/p2sb.h> +#include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr.h> -#include <soc/spi.h> +#include <soc/pm.h> +#include <soc/pmc.h> +#include <soc/smbus.h> + +/* Max PXRC registers in ITSS*/ +#define MAX_PXRC_CONFIG 0x08 /* * Enable Prefetching and Caching. @@ -65,7 +74,6 @@ static void enable_p2sbbar(void) /* Enable P2SB MSE */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* * Enable decoding for HPET memory address range. * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode @@ -81,3 +89,196 @@ void bootblock_pch_early_init(void) enable_spi_prefetch(); enable_p2sbbar(); } + +static void pch_enable_lpc(void) +{ + /* Lookup device tree in romstage */ + const struct device *dev; + const config_t *config; + u16 lpc_en; + + /* IO Decode Range */ + lpc_en = COMA_RANGE | (COMB_RANGE << 4); + pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); + + /* IO Decode Enable */ + lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + /* Set in PCI generic decode range registers */ + pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); + + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); +} + +static void pch_interrupt_init(void) +{ + const struct device *dev; + const config_t *config; + u8 index = 0; + u8 pch_interrupt_routing[MAX_PXRC_CONFIG]; + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pch_interrupt_routing[0] = config->pirqa_routing; + pch_interrupt_routing[1] = config->pirqb_routing; + pch_interrupt_routing[2] = config->pirqc_routing; + pch_interrupt_routing[3] = config->pirqd_routing; + pch_interrupt_routing[4] = config->pirqe_routing; + pch_interrupt_routing[5] = config->pirqf_routing; + pch_interrupt_routing[6] = config->pirqg_routing; + pch_interrupt_routing[7] = config->pirqh_routing; + + for (index = 0; index < MAX_PXRC_CONFIG; index++) { + if (pch_interrupt_routing[index] < 16 && + pch_interrupt_routing[index] > 2 && + pch_interrupt_routing[index] != 8 && + pch_interrupt_routing[index] != 13) { + pcr_write8(PID_ITSS, + (R_PCH_PCR_ITSS_PIRQA_ROUT + index), + pch_interrupt_routing[index]); + } + } +} + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address*/ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); +} + +static void soc_config_pwrmbase(void) +{ + uint32_t reg32; + + /* Disable PWRMBASE in PMC Device first before changing Base address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable PWRM in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); + + /* + * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] + * to the same value programmed in PMC PCI Offset 48h bit[31:16], + * this has an implication of making sure the PWRMBASE to be + * 64KB aligned. + * + * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] + * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an + * implication of making sure the memory allocated to PWRMBASE to be 64KB + * in size. + */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, + ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | + (PCH_PWRM_BASE_ADDRESS >> 16))); + pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); +} + +static void soc_config_tco(void) +{ + uint32_t reg32 = 0; + uint16_t tcobase; + uint16_t tcocnt; + + /* Disable TCO in SMBUS Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); + reg32 &= ~SMBUS_TCO_EN; + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); + + /* Program TCO Base */ + pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); + + /* Enable TCO in SMBUS */ + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); + + /* + * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] + * to [SMBUS PCI offset 50h[15:5], 1]. + */ + pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, + (TCO_BASE_ADDDRESS | (1 << 1))); + + /* Program TCO timer halt */ + tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); + tcobase &= ~0x1f; + tcocnt = inw(tcobase + TCO1_CNT); + tcocnt |= TCO_TMR_HLT; + outw(tcocnt, tcobase + TCO1_CNT); +} + +static void soc_config_rtc(void) +{ + /* Enable upper 128 bytes of CMOS */ + pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, + B_PCH_PCR_RTC_CONF_UCMOS_EN); +} + +void pch_early_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + soc_config_tco(); + + /* + * Interrupt Configuration Register Programming + * PIRQx to IRQ Programming + */ + pch_interrupt_init(); + + /* Program generic IO Decode Range */ + pch_enable_lpc(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + enable_smbus(); + + soc_config_rtc(); +} diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c new file mode 100644 index 0000000..2610940 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci.h> +#include <soc/bootblock.h> +#include <soc/cpu.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> +#include <string.h> + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_SKYLAKE_C0, "Skylake C0" }, + { CPUID_SKYLAKE_D0, "Skylake D0" }, + { CPUID_KABYLAKE_G0, "Kabylake G0" }, + { CPUID_KABYLAKE_H0, "Kabylake H0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { MCH_SKYLAKE_ID_U, "Skylake-U" }, + { MCH_SKYLAKE_ID_Y, "Skylake-Y" }, + { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" }, + { MCH_KABYLAKE_ID_U, "Kabylake-U" }, + { MCH_KABYLAKE_ID_Y, "Kabylake-Y" }, +}; + +static struct { + u16 lpcid; + const char *name; +} pch_table[] = { + { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, + { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, + { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, + { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, + { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, + { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, + { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, + { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, +}; + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index; + char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + const char *mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + } else { + u32 *p = (u32 *) cpu_string; + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + *p++ = cpuidr.eax; + *p++ = cpuidr.ebx; + *p++ = cpuidr.ecx; + *p++ = cpuidr.edx; + } + } + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ') + cpu_name++; + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(0x8B, microcode_ver); + cpuidr = cpuid(1); + microcode_ver = rdmsr(0x8b); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpuidr.eax) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpuidr.eax, cpu_type, microcode_ver.hi); + + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); + u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + u16 lpcid = pch_type(); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].lpcid == lpcid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + lpcid, pch_revision(), pch_type); +} + +static void report_igd_info(void) +{ + int i; + u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c new file mode 100644 index 0000000..bb305d5 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/smbus.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <soc/bootblock.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/smbus.h> + +static const struct reg_script smbus_init_script[] = { + /* Set SMBUS I/O base address */ + REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), + /* Set SMBUS enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +void enable_smbus(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} + diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index e57c369..bacbef8 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -26,9 +26,14 @@ inline void bootblock_fsp_temp_ram_init(void) {} void bootblock_cpu_init(void); void bootblock_pch_early_init(void); void bootblock_systemagent_early_init(void); - void pch_uart_init(void); + /* Bootblock post console init programing */ -void pch_enable_lpc(void); +void enable_smbus(void); +void i2c_early_init(void); +void pch_early_init(void); +void report_platform_info(void); +void report_memory_config(void); +void set_max_freq(void); #endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 71887aa..6c40bd6 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,13 +19,8 @@ #include <fsp/romstage.h> -void i2c_early_init(void); void systemagent_early_init(void); -void pch_early_init(void); void intel_early_me_status(void); -void report_platform_info(void); -void set_max_freq(void); - void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7a13084..31a452f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,17 +1,7 @@ -bootblock-y += cpu.c -bootblock-y += i2c.c -bootblock-y += pch.c -bootblock-y += report_platform.c -bootblock-y += smbus.c verstage-y += power_state.c -romstage-y += cpu.c -romstage-y += i2c.c -romstage-y += pch.c romstage-y += power_state.c -romstage-y += report_platform.c romstage-y += romstage.c -romstage-y += smbus.c romstage-y += spi.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/cpu.c b/src/soc/intel/skylake/romstage/cpu.c deleted file mode 100644 index 1b5db73..0000000 --- a/src/soc/intel/skylake/romstage/cpu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <stdlib.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/romstage.h> - -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -void set_max_freq(void) -{ - msr_t msr, perf_ctl, platform_info; - - /* Check for configurable TDP option */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - - if ((platform_info.hi >> 1) & 3) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - - perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); -} diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c deleted file mode 100644 index f6d1384..0000000 --- a/src/soc/intel/skylake/romstage/i2c.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <commonlib/helpers.h> -#include <device/device.h> -#include <device/i2c.h> -#include <device/pci_def.h> -#include <soc/intel/common/lpss_i2c.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/serialio.h> -#include "chip.h" - -uintptr_t lpss_i2c_base_address(unsigned bus) -{ - int devfn; - pci_devfn_t dev; - - /* Find device+function for this controller */ - devfn = i2c_bus_to_devfn(bus); - if (devfn < 0) - return 0; - - /* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - /* Read the first base address for this device */ - return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); -} - -static void i2c_early_init_bus(unsigned bus) -{ - ROMSTAGE_CONST struct soc_intel_skylake_config *config; - ROMSTAGE_CONST struct device *tree_dev; - const struct lpss_i2c_speed_config *sptr; - enum i2c_speed speed; - pci_devfn_t dev; - int devfn; - uintptr_t base; - uint32_t value; - void *reg; - - /* Find the PCI device for this bus controller */ - devfn = i2c_bus_to_devfn(bus); - if (devfn < 0) - return; - - /* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = dev_find_slot(0, devfn); - if (!tree_dev || !tree_dev->enabled) - return; - - /* Skip if not enabled for early init */ - config = tree_dev->chip_info; - if (!config) - return; - if (!config->i2c[bus].early_init) - return; - - /* Prepare early base address for access before memory */ - base = EARLY_I2C_BASE(bus); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Take device out of reset */ - reg = (void *)(base + SIO_REG_PPR_RESETS); - value = read32(reg); - value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | - SIO_REG_PPR_RESETS_IDMA; - write32(reg, value); - - /* Initialize the controller */ - speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; - lpss_i2c_init(bus, speed); - - /* Apply custom speed config if it has been set by the board */ - for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { - sptr = &config->i2c[bus].speed_config[value]; - if (sptr->speed == speed) { - lpss_i2c_set_speed_config(bus, sptr); - break; - } - } -} - -void i2c_early_init(void) -{ - int bus; - - /* Initialize I2C controllers that are enabled in devicetree */ - for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) - i2c_early_init_bus(bus); -} diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c deleted file mode 100644 index dd52b40..0000000 --- a/src/soc/intel/skylake/romstage/pch.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <chip.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pch.h> -#include <soc/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/pmc.h> -#include <soc/romstage.h> -#include <soc/smbus.h> - -/* Max PXRC registers in ITSS*/ -#define MAX_PXRC_CONFIG 0x08 - -static const u8 pch_interrupt_routing[] = { - 11, /* PARC: PIRQA -> IRQ11 */ - 10, /* PBRC: PIRQB -> IRQ10 */ - 11, /* PCRC: PIRQC -> IRQ11 */ - 11, /* PDRC: PIRQD -> IRQ11 */ - 11, /* PERC: PIRQE -> IRQ11 */ - 11, /* PFRC: PIRQF -> IRQ11 */ - 11, /* PGRC: PIRQG -> IRQ11 */ - 11 /* PHRC: PIRQH -> IRQ11 */ -}; - -static void pch_enable_lpc(void) -{ - /* Lookup device tree in romstage */ - const struct device *dev; - const config_t *config; - u16 lpc_en; - - /* IO Decode Range */ - lpc_en = COMA_RANGE | (COMB_RANGE << 4); - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); - - /* IO Decode Enable */ - lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); - - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; - - /* Set in PCI generic decode range registers */ - pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); - - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec); -} - -static void pch_interrupt_init(void) -{ - u8 index = 0; - - for (index = 0; index < MAX_PXRC_CONFIG; index++) { - if (pch_interrupt_routing[index] < 16 && - pch_interrupt_routing[index] > 2 && - pch_interrupt_routing[index] != 8 && - pch_interrupt_routing[index] != 13) { - pcr_write8(PID_ITSS, - (R_PCH_PCR_ITSS_PIRQA_ROUT + index), - pch_interrupt_routing[index]); - } - } -} - -static void soc_config_acpibase(void) -{ - uint32_t reg32; - - /* Disable ABASE in PMC Device first before changing Base Address*/ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); - - /* Program ACPI Base */ - pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); - - /* Enable ACPI in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); - - /* - * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] - * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] - */ - reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0); -} - -static void soc_config_pwrmbase(void) -{ - uint32_t reg32; - - /* Disable PWRMBASE in PMC Device first before changing Base address */ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); - - /* Program PWRM Base */ - pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); - - /* Enable PWRM in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); - - /* - * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] - * to the same value programmed in PMC PCI Offset 48h bit[31:16], - * this has an implication of making sure the PWRMBASE to be - * 64KB aligned. - * - * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] - * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an - * implication of making sure the memory allocated to PWRMBASE to be 64KB - * in size. - */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA, - ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | - (PCH_PWRM_BASE_ADDRESS >> 16))); - pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0); -} - -static void soc_config_tco(void) -{ - uint32_t reg32 = 0; - uint16_t tcobase; - uint16_t tcocnt; - - /* Disable TCO in SMBUS Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~SMBUS_TCO_EN; - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); - - /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); - - /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); - - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - * to [SMBUS PCI offset 50h[15:5], 1]. - */ - pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE, - (TCO_BASE_ADDDRESS | (1 << 1))); - - /* Program TCO timer halt */ - tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); - tcobase &= ~0x1f; - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - outw(tcocnt, tcobase + TCO1_CNT); -} - -static void soc_config_rtc(void) -{ - /* Enable upper 128 bytes of CMOS */ - pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0, - B_PCH_PCR_RTC_CONF_UCMOS_EN); -} - -void pch_early_init(void) -{ - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ - soc_config_acpibase(); - - /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ - soc_config_pwrmbase(); - - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - soc_config_tco(); - - /* - * Interrupt Configuration Register Programming - * PIRQx to IRQ Programming - */ - pch_interrupt_init(); - - /* Program generic IO Decode Range */ - pch_enable_lpc(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - enable_smbus(); - - soc_config_rtc(); -} diff --git a/src/soc/intel/skylake/romstage/report_platform.c b/src/soc/intel/skylake/romstage/report_platform.c deleted file mode 100644 index e841359..0000000 --- a/src/soc/intel/skylake/romstage/report_platform.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <device/pci.h> -#include <soc/cpu.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> -#include <string.h> - -static struct { - u32 cpuid; - const char *name; -} cpu_table[] = { - { CPUID_SKYLAKE_C0, "Skylake C0" }, - { CPUID_SKYLAKE_D0, "Skylake D0" }, - { CPUID_KABYLAKE_G0, "Kabylake G0" }, - { CPUID_KABYLAKE_H0, "Kabylake H0" }, -}; - -static struct { - u16 mchid; - const char *name; -} mch_table[] = { - { MCH_SKYLAKE_ID_U, "Skylake-U" }, - { MCH_SKYLAKE_ID_Y, "Skylake-Y" }, - { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" }, - { MCH_KABYLAKE_ID_U, "Kabylake-U" }, - { MCH_KABYLAKE_ID_Y, "Kabylake-Y" }, -}; - -static struct { - u16 lpcid; - const char *name; -} pch_table[] = { - { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, - { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, - { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, - { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, - { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, - { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, -}; - -static struct { - u16 igdid; - const char *name; -} igd_table[] = { - { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"}, - { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" }, - { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" }, -}; - -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - msr_t microcode_ver; - const char *mode[] = {"NOT ", ""}; - const char *cpu_type = "Unknown"; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32 *) cpu_string; - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(0x8B, microcode_ver); - cpuidr = cpuid(1); - microcode_ver = rdmsr(0x8b); - - /* Look for string to match the name */ - for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { - cpu_type = cpu_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); - printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpuidr.eax, cpu_type, microcode_ver.hi); - - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - -static void report_mch_info(void) -{ - int i; - u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); - const char *mch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(mch_table); i++) { - if (mch_table[i].mchid == mchid) { - mch_type = mch_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", - mchid, mch_revision, mch_type); -} - -static void report_pch_info(void) -{ - int i; - u16 lpcid = pch_type(); - const char *pch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { - pch_type = pch_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, pch_revision(), pch_type); -} - -static void report_igd_info(void) -{ - int i; - u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); - const char *igd_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(igd_table); i++) { - if (igd_table[i].igdid == igdid) { - igd_type = igd_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", - igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); -} - -void report_platform_info(void) -{ - report_cpu_info(); - report_mch_info(); - report_pch_info(); - report_igd_info(); -} - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/soc/intel/skylake/romstage/smbus.c b/src/soc/intel/skylake/romstage/smbus.c deleted file mode 100644 index ca9c6ad..0000000 --- a/src/soc/intel/skylake/romstage/smbus.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> -#include <soc/romstage.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void enable_smbus(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address); -}

1 0

Patch merged into coreboot/master: skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
by gerrit＠coreboot.org 17 Aug '16

17 Aug '16

the following patch was just integrated into master: commit cf73c1317dd1ab62a96eb17ed6d9c8590fb4c514 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Aug 4 20:01:12 2016 +0530 skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init Prepare Skylake for FSP2.0 support. We do not use FSP-T in FSP2.0 driver, hence guard the FspTempRamInit call under a switch. In addition to the current early PCH configuration program few more register, so all in all we do the following, * Program and enable ACPI Base. * Program and enable PWRM Base. * Program TCO Base. * Program Interrupt configuration registers. * Program LPC IO decode range. * Program SMBUS Base address and enable it. * Enable upper 128 bytes of CMOS. And split the above programming into into smaller functions. Also, as part of bootblock_pch_early_init we enable decoding for HPET range. This is needed for FspMemoryInit to store and retrieve a global data pointer. And also move P2SB related definitions to a new header file. TEST=Build and boot Kunimitsu Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Reviewed-on: https://review.coreboot.org/16113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16113 for details. -gerrit

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2016