coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: intel/apollolake: Fix check for return value of pmc_gpe_route_to_gpio
by gerrit＠coreboot.org 17 Aug '16

17 Aug '16

the following patch was just integrated into master: commit e7de6fb162bb9a7c0551027514596d6d7f45421b Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Aug 14 21:50:50 2016 -0700 intel/apollolake: Fix check for return value of pmc_gpe_route_to_gpio pmc_gpe_route_to_gpio returns -1 on error. However, the value was being stored in unsigned int and compared against -1. Fix this by using local variable ret. Change-Id: I5ec824949d4ee0fbdbb2ffdc9fc9d4762455b27b Reported-by: Coverity ID 1357443, 1357442, 1357441 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/16218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16218 for details. -gerrit

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New patch to review for coreboot: rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevin
by Martin Roth 17 Aug '16

17 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16241 -gerrit commit 92ffb08024739c93fe2bb13fcc48da6a285a6596 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Jul 25 10:06:09 2016 +0800 rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevin We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 8 +- .../gru/sdram_inf/sdram-lpddr3-hynix-4GB-933.inc | 1563 ++++++++++++++++++++ src/soc/rockchip/rk3399/clock.c | 4 +- src/soc/rockchip/rk3399/sdram.c | 2 +- 4 files changed, 1573 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 6403e98..f34ebf1 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -35,6 +35,9 @@ static struct rk3399_sdram_params sdram_configs[] = { /* 800MHz, disable odt */ #include "sdram_inf/sdram-lpddr3-hynix-4GB-800-no-odt.inc" + +/* 933MHz, enable odt 120o */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB-933.inc" }; enum dram_speeds { @@ -43,6 +46,7 @@ enum dram_speeds { dram_800MHz = 2, dram_666MHz_NO_ODT = 3, dram_800MHz_NO_ODT = 4, + dram_933MHz = 5, }; static enum dram_speeds get_sdram_index(void) @@ -59,8 +63,10 @@ static enum dram_speeds get_sdram_index(void) return dram_200MHz; case 3: return dram_666MHz_NO_ODT; - default: + case 4: return dram_800MHz; + default: + return dram_933MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_inf/sdram-lpddr3-hynix-4GB-933.inc b/src/mainboard/google/gru/sdram_inf/sdram-lpddr3-hynix-4GB-933.inc new file mode 100644 index 0000000..fe1949e --- /dev/null +++ b/src/mainboard/google/gru/sdram_inf/sdram-lpddr3-hynix-4GB-933.inc @@ -0,0 +1,1563 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .ddrconfig = 1, + { + {0x1d191519}, + {0x14040808}, + {0x00000002}, + {0x00006226}, + {0x00000054}, + 0x00000000 + } + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .ddrconfig = 1, + { + {0x1d191519}, + {0x14040808}, + {0x00000002}, + {0x00006226}, + {0x00000054}, + 0x00000000 + } + } + }, + .ddr_freq = 933*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 1, + { + { + 0x00000700, /* DENALI_CTL_00_DATA */ + 0x00000000, /* DENALI_CTL_01_DATA */ + 0x00000000, /* DENALI_CTL_02_DATA */ + 0x00000000, /* DENALI_CTL_03_DATA */ + 0x00000000, /* DENALI_CTL_04_DATA */ + 0x0000005e, /* DENALI_CTL_05_DATA */ + 0x0002d976, /* DENALI_CTL_06_DATA */ + 0x000003a6, /* DENALI_CTL_07_DATA */ + 0x0000247a, /* DENALI_CTL_08_DATA */ + 0x0000005e, /* DENALI_CTL_09_DATA */ + 0x0002d976, /* DENALI_CTL_10_DATA */ + 0x000003a6, /* DENALI_CTL_11_DATA */ + 0x0000247a, /* DENALI_CTL_12_DATA */ + 0x0000005e, /* DENALI_CTL_13_DATA */ + 0x0002d976, /* DENALI_CTL_14_DATA */ + 0x000003a6, /* DENALI_CTL_15_DATA */ + 0x0100247a, /* DENALI_CTL_16_DATA */ + 0x00000000, /* DENALI_CTL_17_DATA */ + 0x00000101, /* DENALI_CTL_18_DATA */ + 0x00020100, /* DENALI_CTL_19_DATA */ + 0x000000bb, /* DENALI_CTL_20_DATA */ + 0x000001d3, /* DENALI_CTL_21_DATA */ + 0x00000000, /* DENALI_CTL_22_DATA */ + 0x081c0000, /* DENALI_CTL_23_DATA */ + 0x00081c00, /* DENALI_CTL_24_DATA */ + 0x0400081c, /* DENALI_CTL_25_DATA */ + 0x3b0a0004, /* DENALI_CTL_26_DATA */ + 0x2f110828, /* DENALI_CTL_27_DATA */ + 0x283b0a00, /* DENALI_CTL_28_DATA */ + 0x002f1108, /* DENALI_CTL_29_DATA */ + 0x08283b0a, /* DENALI_CTL_30_DATA */ + 0x08002f11, /* DENALI_CTL_31_DATA */ + 0x00000a0a, /* DENALI_CTL_32_DATA */ + 0x0800ff4f, /* DENALI_CTL_33_DATA */ + 0x0a0a080f, /* DENALI_CTL_34_DATA */ + 0x0800ff4f, /* DENALI_CTL_35_DATA */ + 0x0a0a080f, /* DENALI_CTL_36_DATA */ + 0x0800ff4f, /* DENALI_CTL_37_DATA */ + 0x0203000f, /* DENALI_CTL_38_DATA */ + 0x110f1100, /* DENALI_CTL_39_DATA */ + 0x040f110f, /* DENALI_CTL_40_DATA */ + 0x14000a0a, /* DENALI_CTL_41_DATA */ + 0x03030a0a, /* DENALI_CTL_42_DATA */ + 0x00010003, /* DENALI_CTL_43_DATA */ + 0x03212121, /* DENALI_CTL_44_DATA */ + 0x00141414, /* DENALI_CTL_45_DATA */ + 0x00000000, /* DENALI_CTL_46_DATA */ + 0x03010000, /* DENALI_CTL_47_DATA */ + 0x0e3100c5, /* DENALI_CTL_48_DATA */ + 0x0e3100c5, /* DENALI_CTL_49_DATA */ + 0x0e3100c5, /* DENALI_CTL_50_DATA */ + 0x00000000, /* DENALI_CTL_51_DATA */ + 0x00080008, /* DENALI_CTL_52_DATA */ + 0x00170008, /* DENALI_CTL_53_DATA */ + 0x00170017, /* DENALI_CTL_54_DATA */ + 0x00111111, /* DENALI_CTL_55_DATA */ + 0x00000000, /* DENALI_CTL_56_DATA */ + 0x00000000, /* DENALI_CTL_57_DATA */ + 0x00000000, /* DENALI_CTL_58_DATA */ + 0x00ce0000, /* DENALI_CTL_59_DATA */ + 0x00ce00ce, /* DENALI_CTL_60_DATA */ + 0x00ce00ce, /* DENALI_CTL_61_DATA */ + 0x000000ce, /* DENALI_CTL_62_DATA */ + 0x00000000, /* DENALI_CTL_63_DATA */ + 0x00000000, /* DENALI_CTL_64_DATA */ + 0x00000000, /* DENALI_CTL_65_DATA */ + 0x00000000, /* DENALI_CTL_66_DATA */ + 0x00000000, /* DENALI_CTL_67_DATA */ + 0x00000000, /* DENALI_CTL_68_DATA */ + 0x00000301, /* DENALI_CTL_69_DATA */ + 0x00000001, /* DENALI_CTL_70_DATA */ + 0x00000000, /* DENALI_CTL_71_DATA */ + 0x00000000, /* DENALI_CTL_72_DATA */ + 0x01000000, /* DENALI_CTL_73_DATA */ + 0x80104002, /* DENALI_CTL_74_DATA */ + 0x00040003, /* DENALI_CTL_75_DATA */ + 0x00040005, /* DENALI_CTL_76_DATA */ + 0x00030000, /* DENALI_CTL_77_DATA */ + 0x00050004, /* DENALI_CTL_78_DATA */ + 0x00000004, /* DENALI_CTL_79_DATA */ + 0x00040003, /* DENALI_CTL_80_DATA */ + 0x00040005, /* DENALI_CTL_81_DATA */ + 0x38c40000, /* DENALI_CTL_82_DATA */ + 0x00001c62, /* DENALI_CTL_83_DATA */ + 0x1c6238c4, /* DENALI_CTL_84_DATA */ + 0x38c40000, /* DENALI_CTL_85_DATA */ + 0x00001c62, /* DENALI_CTL_86_DATA */ + 0x00000000, /* DENALI_CTL_87_DATA */ + 0x00000000, /* DENALI_CTL_88_DATA */ + 0x00000000, /* DENALI_CTL_89_DATA */ + 0x00000000, /* DENALI_CTL_90_DATA */ + 0x00000000, /* DENALI_CTL_91_DATA */ + 0x02020200, /* DENALI_CTL_92_DATA */ + 0x00020202, /* DENALI_CTL_93_DATA */ + 0x00030200, /* DENALI_CTL_94_DATA */ + 0x00040700, /* DENALI_CTL_95_DATA */ + 0x00000302, /* DENALI_CTL_96_DATA */ + 0x02000407, /* DENALI_CTL_97_DATA */ + 0x00000003, /* DENALI_CTL_98_DATA */ + 0x00030f04, /* DENALI_CTL_99_DATA */ + 0x00070004, /* DENALI_CTL_100_DATA */ + 0x00000000, /* DENALI_CTL_101_DATA */ + 0x00000000, /* DENALI_CTL_102_DATA */ + 0x00000000, /* DENALI_CTL_103_DATA */ + 0x00000000, /* DENALI_CTL_104_DATA */ + 0x00000000, /* DENALI_CTL_105_DATA */ + 0x00000000, /* DENALI_CTL_106_DATA */ + 0x00000000, /* DENALI_CTL_107_DATA */ + 0x00010000, /* DENALI_CTL_108_DATA */ + 0x20040020, /* DENALI_CTL_109_DATA */ + 0x00200400, /* DENALI_CTL_110_DATA */ + 0x01000400, /* DENALI_CTL_111_DATA */ + 0x00000b80, /* DENALI_CTL_112_DATA */ + 0x00000000, /* DENALI_CTL_113_DATA */ + 0x00000001, /* DENALI_CTL_114_DATA */ + 0x00000002, /* DENALI_CTL_115_DATA */ + 0x0000000e, /* DENALI_CTL_116_DATA */ + 0x00000000, /* DENALI_CTL_117_DATA */ + 0x00000000, /* DENALI_CTL_118_DATA */ + 0x00000000, /* DENALI_CTL_119_DATA */ + 0x00000000, /* DENALI_CTL_120_DATA */ + 0x00000000, /* DENALI_CTL_121_DATA */ + 0x00bb0000, /* DENALI_CTL_122_DATA */ + 0x00ea005e, /* DENALI_CTL_123_DATA */ + 0x00ea0000, /* DENALI_CTL_124_DATA */ + 0x005e00bb, /* DENALI_CTL_125_DATA */ + 0x000000ea, /* DENALI_CTL_126_DATA */ + 0x00bb00ea, /* DENALI_CTL_127_DATA */ + 0x00ea005e, /* DENALI_CTL_128_DATA */ + 0x00ea0000, /* DENALI_CTL_129_DATA */ + 0x00000000, /* DENALI_CTL_130_DATA */ + 0x00000000, /* DENALI_CTL_131_DATA */ + 0x00000000, /* DENALI_CTL_132_DATA */ + 0x00c30000, /* DENALI_CTL_133_DATA */ + 0x0000001c, /* DENALI_CTL_134_DATA */ + 0x001c00c3, /* DENALI_CTL_135_DATA */ + 0x00c30000, /* DENALI_CTL_136_DATA */ + 0x0000001c, /* DENALI_CTL_137_DATA */ + 0x00010001, /* DENALI_CTL_138_DATA */ + 0x06000001, /* DENALI_CTL_139_DATA */ + 0x00000707, /* DENALI_CTL_140_DATA */ + 0x00000000, /* DENALI_CTL_141_DATA */ + 0x00000000, /* DENALI_CTL_142_DATA */ + 0x00000000, /* DENALI_CTL_143_DATA */ + 0x00000000, /* DENALI_CTL_144_DATA */ + 0x00000000, /* DENALI_CTL_145_DATA */ + 0x00000000, /* DENALI_CTL_146_DATA */ + 0x00c30000, /* DENALI_CTL_147_DATA */ + 0x0000001c, /* DENALI_CTL_148_DATA */ + 0x001c00c3, /* DENALI_CTL_149_DATA */ + 0x00c30000, /* DENALI_CTL_150_DATA */ + 0x0000001c, /* DENALI_CTL_151_DATA */ + 0x00010001, /* DENALI_CTL_152_DATA */ + 0x06000001, /* DENALI_CTL_153_DATA */ + 0x00000707, /* DENALI_CTL_154_DATA */ + 0x00000000, /* DENALI_CTL_155_DATA */ + 0x00000000, /* DENALI_CTL_156_DATA */ + 0x00000000, /* DENALI_CTL_157_DATA */ + 0x00000000, /* DENALI_CTL_158_DATA */ + 0x00000000, /* DENALI_CTL_159_DATA */ + 0x00000000, /* DENALI_CTL_160_DATA */ + 0x01000000, /* DENALI_CTL_161_DATA */ + 0x00000000, /* DENALI_CTL_162_DATA */ + 0x00000000, /* DENALI_CTL_163_DATA */ + 0x18151100, /* DENALI_CTL_164_DATA */ + 0x0000000c, /* DENALI_CTL_165_DATA */ + 0x00000000, /* DENALI_CTL_166_DATA */ + 0x00000000, /* DENALI_CTL_167_DATA */ + 0x00000000, /* DENALI_CTL_168_DATA */ + 0x00000000, /* DENALI_CTL_169_DATA */ + 0x00000000, /* DENALI_CTL_170_DATA */ + 0x00000000, /* DENALI_CTL_171_DATA */ + 0x00000000, /* DENALI_CTL_172_DATA */ + 0x00000000, /* DENALI_CTL_173_DATA */ + 0x00000000, /* DENALI_CTL_174_DATA */ + 0x00000000, /* DENALI_CTL_175_DATA */ + 0x00000000, /* DENALI_CTL_176_DATA */ + 0x00000000, /* DENALI_CTL_177_DATA */ + 0x00000000, /* DENALI_CTL_178_DATA */ + 0x0003a603, /* DENALI_CTL_179_DATA */ + 0x00550151, /* DENALI_CTL_180_DATA */ + 0x00000000, /* DENALI_CTL_181_DATA */ + 0x015103a6, /* DENALI_CTL_182_DATA */ + 0x00000055, /* DENALI_CTL_183_DATA */ + 0x0003a600, /* DENALI_CTL_184_DATA */ + 0x00550151, /* DENALI_CTL_185_DATA */ + 0x00000000, /* DENALI_CTL_186_DATA */ + 0x002f0000, /* DENALI_CTL_187_DATA */ + 0x002f002f, /* DENALI_CTL_188_DATA */ + 0x01010100, /* DENALI_CTL_189_DATA */ + 0x01000202, /* DENALI_CTL_190_DATA */ + 0x0a000002, /* DENALI_CTL_191_DATA */ + 0x01000f0f, /* DENALI_CTL_192_DATA */ + 0x00000000, /* DENALI_CTL_193_DATA */ + 0x00000000, /* DENALI_CTL_194_DATA */ + 0x00010003, /* DENALI_CTL_195_DATA */ + 0x00000c03, /* DENALI_CTL_196_DATA */ + 0x00000100, /* DENALI_CTL_197_DATA */ + 0x00010000, /* DENALI_CTL_198_DATA */ + 0x01000000, /* DENALI_CTL_199_DATA */ + 0x00010000, /* DENALI_CTL_200_DATA */ + 0x00000001, /* DENALI_CTL_201_DATA */ + 0x00000000, /* DENALI_CTL_202_DATA */ + 0x00000000, /* DENALI_CTL_203_DATA */ + 0x00000000, /* DENALI_CTL_204_DATA */ + 0x00000000, /* DENALI_CTL_205_DATA */ + 0x00000000, /* DENALI_CTL_206_DATA */ + 0x00000000, /* DENALI_CTL_207_DATA */ + 0x00000000, /* DENALI_CTL_208_DATA */ + 0x00000000, /* DENALI_CTL_209_DATA */ + 0x00000000, /* DENALI_CTL_210_DATA */ + 0x00010000, /* DENALI_CTL_211_DATA */ + 0x04040401, /* DENALI_CTL_212_DATA */ + 0x01010808, /* DENALI_CTL_213_DATA */ + 0x04040001, /* DENALI_CTL_214_DATA */ + 0x0c0c0c04, /* DENALI_CTL_215_DATA */ + 0x08080808, /* DENALI_CTL_216_DATA */ + 0x02010103, /* DENALI_CTL_217_DATA */ + 0x02010103, /* DENALI_CTL_218_DATA */ + 0x00010103, /* DENALI_CTL_219_DATA */ + 0x00020202, /* DENALI_CTL_220_DATA */ + 0x06030600, /* DENALI_CTL_221_DATA */ + 0x00030603, /* DENALI_CTL_222_DATA */ + 0x00000000, /* DENALI_CTL_223_DATA */ + 0x00000000, /* DENALI_CTL_224_DATA */ + 0x0d000001, /* DENALI_CTL_225_DATA */ + 0x00010028, /* DENALI_CTL_226_DATA */ + 0x00010000, /* DENALI_CTL_227_DATA */ + 0x00000003, /* DENALI_CTL_228_DATA */ + 0x00000000, /* DENALI_CTL_229_DATA */ + 0x00000000, /* DENALI_CTL_230_DATA */ + 0x00000000, /* DENALI_CTL_231_DATA */ + 0x00000000, /* DENALI_CTL_232_DATA */ + 0x00000000, /* DENALI_CTL_233_DATA */ + 0x00000000, /* DENALI_CTL_234_DATA */ + 0x00000000, /* DENALI_CTL_235_DATA */ + 0x00000000, /* DENALI_CTL_236_DATA */ + 0x00010100, /* DENALI_CTL_237_DATA */ + 0x01000000, /* DENALI_CTL_238_DATA */ + 0x00000001, /* DENALI_CTL_239_DATA */ + 0x00000303, /* DENALI_CTL_240_DATA */ + 0x00000000, /* DENALI_CTL_241_DATA */ + 0x00000000, /* DENALI_CTL_242_DATA */ + 0x00000000, /* DENALI_CTL_243_DATA */ + 0x00000000, /* DENALI_CTL_244_DATA */ + 0x00000000, /* DENALI_CTL_245_DATA */ + 0x00000000, /* DENALI_CTL_246_DATA */ + 0x00000000, /* DENALI_CTL_247_DATA */ + 0x00000000, /* DENALI_CTL_248_DATA */ + 0x00000000, /* DENALI_CTL_249_DATA */ + 0x00000000, /* DENALI_CTL_250_DATA */ + 0x00000000, /* DENALI_CTL_251_DATA */ + 0x00000000, /* DENALI_CTL_252_DATA */ + 0x00000000, /* DENALI_CTL_253_DATA */ + 0x00000000, /* DENALI_CTL_254_DATA */ + 0x00000000, /* DENALI_CTL_255_DATA */ + 0x000556aa, /* DENALI_CTL_256_DATA */ + 0x000aaaaa, /* DENALI_CTL_257_DATA */ + 0x000aa955, /* DENALI_CTL_258_DATA */ + 0x00055555, /* DENALI_CTL_259_DATA */ + 0x000b3133, /* DENALI_CTL_260_DATA */ + 0x0004cd33, /* DENALI_CTL_261_DATA */ + 0x0004cecc, /* DENALI_CTL_262_DATA */ + 0x000b32cc, /* DENALI_CTL_263_DATA */ + 0x00010300, /* DENALI_CTL_264_DATA */ + 0x03000100, /* DENALI_CTL_265_DATA */ + 0x00000000, /* DENALI_CTL_266_DATA */ + 0x00000000, /* DENALI_CTL_267_DATA */ + 0x00000000, /* DENALI_CTL_268_DATA */ + 0x00000000, /* DENALI_CTL_269_DATA */ + 0x00000000, /* DENALI_CTL_270_DATA */ + 0x00000000, /* DENALI_CTL_271_DATA */ + 0x00000000, /* DENALI_CTL_272_DATA */ + 0x00000000, /* DENALI_CTL_273_DATA */ + 0x00ffff00, /* DENALI_CTL_274_DATA */ + 0x20200000, /* DENALI_CTL_275_DATA */ + 0x08000020, /* DENALI_CTL_276_DATA */ + 0x00001c62, /* DENALI_CTL_277_DATA */ + 0x00000200, /* DENALI_CTL_278_DATA */ + 0x00000200, /* DENALI_CTL_279_DATA */ + 0x00000200, /* DENALI_CTL_280_DATA */ + 0x00000200, /* DENALI_CTL_281_DATA */ + 0x00001c62, /* DENALI_CTL_282_DATA */ + 0x00011bd4, /* DENALI_CTL_283_DATA */ + 0x1c62070c, /* DENALI_CTL_284_DATA */ + 0x00000200, /* DENALI_CTL_285_DATA */ + 0x00000200, /* DENALI_CTL_286_DATA */ + 0x00000200, /* DENALI_CTL_287_DATA */ + 0x00000200, /* DENALI_CTL_288_DATA */ + 0x00001c62, /* DENALI_CTL_289_DATA */ + 0x00011bd4, /* DENALI_CTL_290_DATA */ + 0x1c62070c, /* DENALI_CTL_291_DATA */ + 0x00000200, /* DENALI_CTL_292_DATA */ + 0x00000200, /* DENALI_CTL_293_DATA */ + 0x00000200, /* DENALI_CTL_294_DATA */ + 0x00000200, /* DENALI_CTL_295_DATA */ + 0x00001c62, /* DENALI_CTL_296_DATA */ + 0x00011bd4, /* DENALI_CTL_297_DATA */ + 0x0202070c, /* DENALI_CTL_298_DATA */ + 0x03030202, /* DENALI_CTL_299_DATA */ + 0x00000018, /* DENALI_CTL_300_DATA */ + 0x00000000, /* DENALI_CTL_301_DATA */ + 0x00000000, /* DENALI_CTL_302_DATA */ + 0x00001403, /* DENALI_CTL_303_DATA */ + 0x00000000, /* DENALI_CTL_304_DATA */ + 0x00000000, /* DENALI_CTL_305_DATA */ + 0x00000000, /* DENALI_CTL_306_DATA */ + 0x00030000, /* DENALI_CTL_307_DATA */ + 0x000f0021, /* DENALI_CTL_308_DATA */ + 0x000f0021, /* DENALI_CTL_309_DATA */ + 0x000f0021, /* DENALI_CTL_310_DATA */ + 0x00000000, /* DENALI_CTL_311_DATA */ + 0x00000000, /* DENALI_CTL_312_DATA */ + 0x01000000, /* DENALI_CTL_313_DATA */ + 0x02090209, /* DENALI_CTL_314_DATA */ + 0x00050209, /* DENALI_CTL_315_DATA */ + 0x00000000, /* DENALI_CTL_316_DATA */ + 0x00000000, /* DENALI_CTL_317_DATA */ + 0x00000000, /* DENALI_CTL_318_DATA */ + 0x00000000, /* DENALI_CTL_319_DATA */ + 0x00000000, /* DENALI_CTL_320_DATA */ + 0x00000000, /* DENALI_CTL_321_DATA */ + 0x00000000, /* DENALI_CTL_322_DATA */ + 0x00000000, /* DENALI_CTL_323_DATA */ + 0x01000101, /* DENALI_CTL_324_DATA */ + 0x01010101, /* DENALI_CTL_325_DATA */ + 0x01000101, /* DENALI_CTL_326_DATA */ + 0x01000100, /* DENALI_CTL_327_DATA */ + 0x00010001, /* DENALI_CTL_328_DATA */ + 0x00010002, /* DENALI_CTL_329_DATA */ + 0x00020100, /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + } + }, + { + { + 0x00000700, /* DENALI_PI_00_DATA */ + 0x00000000, /* DENALI_PI_01_DATA */ + 0x000038c4, /* DENALI_PI_02_DATA */ + 0x00001c62, /* DENALI_PI_03_DATA */ + 0x000038c4, /* DENALI_PI_04_DATA */ + 0x00001c62, /* DENALI_PI_05_DATA */ + 0x000038c4, /* DENALI_PI_06_DATA */ + 0x1c621c62, /* DENALI_PI_07_DATA */ + 0x00000200, /* DENALI_PI_08_DATA */ + 0x00000200, /* DENALI_PI_09_DATA */ + 0x00000200, /* DENALI_PI_10_DATA */ + 0x00000200, /* DENALI_PI_11_DATA */ + 0x00001c62, /* DENALI_PI_12_DATA */ + 0x00000200, /* DENALI_PI_13_DATA */ + 0x00000200, /* DENALI_PI_14_DATA */ + 0x00000200, /* DENALI_PI_15_DATA */ + 0x00000200, /* DENALI_PI_16_DATA */ + 0x00001c62, /* DENALI_PI_17_DATA */ + 0x00000200, /* DENALI_PI_18_DATA */ + 0x00000200, /* DENALI_PI_19_DATA */ + 0x00000200, /* DENALI_PI_20_DATA */ + 0x00000200, /* DENALI_PI_21_DATA */ + 0x00010000, /* DENALI_PI_22_DATA */ + 0x00000007, /* DENALI_PI_23_DATA */ + 0x81000001, /* DENALI_PI_24_DATA */ + 0x0f0003f0, /* DENALI_PI_25_DATA */ + 0x3fffffff, /* DENALI_PI_26_DATA */ + 0x0f0000a0, /* DENALI_PI_27_DATA */ + 0x377ff000, /* DENALI_PI_28_DATA */ + 0x0f000020, /* DENALI_PI_29_DATA */ + 0x377ff000, /* DENALI_PI_30_DATA */ + 0x0f000030, /* DENALI_PI_31_DATA */ + 0x377ff000, /* DENALI_PI_32_DATA */ + 0x0f0000b0, /* DENALI_PI_33_DATA */ + 0x377ff000, /* DENALI_PI_34_DATA */ + 0x0f000100, /* DENALI_PI_35_DATA */ + 0x377ff000, /* DENALI_PI_36_DATA */ + 0x0f000110, /* DENALI_PI_37_DATA */ + 0x377ff000, /* DENALI_PI_38_DATA */ + 0x0f000010, /* DENALI_PI_39_DATA */ + 0x377ff000, /* DENALI_PI_40_DATA */ + 0x03000101, /* DENALI_PI_41_DATA */ + 0x04323232, /* DENALI_PI_42_DATA */ + 0x081c0008, /* DENALI_PI_43_DATA */ + 0x00081c00, /* DENALI_PI_44_DATA */ + 0x0000001c, /* DENALI_PI_45_DATA */ + 0x0e3100c5, /* DENALI_PI_46_DATA */ + 0x0e3100c5, /* DENALI_PI_47_DATA */ + 0x0e3100c5, /* DENALI_PI_48_DATA */ + 0x00000500, /* DENALI_PI_49_DATA */ + 0x00000000, /* DENALI_PI_50_DATA */ + 0x00000000, /* DENALI_PI_51_DATA */ + 0x00000000, /* DENALI_PI_52_DATA */ + 0x00000000, /* DENALI_PI_53_DATA */ + 0x00000000, /* DENALI_PI_54_DATA */ + 0x00000000, /* DENALI_PI_55_DATA */ + 0x00000000, /* DENALI_PI_56_DATA */ + 0x00000000, /* DENALI_PI_57_DATA */ + 0x04040000, /* DENALI_PI_58_DATA */ + 0x0d000004, /* DENALI_PI_59_DATA */ + 0x00000128, /* DENALI_PI_60_DATA */ + 0x00000000, /* DENALI_PI_61_DATA */ + 0x00030003, /* DENALI_PI_62_DATA */ + 0x00000018, /* DENALI_PI_63_DATA */ + 0x00000000, /* DENALI_PI_64_DATA */ + 0x00000000, /* DENALI_PI_65_DATA */ + 0x04060002, /* DENALI_PI_66_DATA */ + 0x04010401, /* DENALI_PI_67_DATA */ + 0x01080801, /* DENALI_PI_68_DATA */ + 0x04020201, /* DENALI_PI_69_DATA */ + 0x01080804, /* DENALI_PI_70_DATA */ + 0x00000000, /* DENALI_PI_71_DATA */ + 0x04040000, /* DENALI_PI_72_DATA */ + 0x0c0c0c04, /* DENALI_PI_73_DATA */ + 0x00000000, /* DENALI_PI_74_DATA */ + 0x00000000, /* DENALI_PI_75_DATA */ + 0x00000000, /* DENALI_PI_76_DATA */ + 0x00030300, /* DENALI_PI_77_DATA */ + 0x00000014, /* DENALI_PI_78_DATA */ + 0x00000000, /* DENALI_PI_79_DATA */ + 0x01010300, /* DENALI_PI_80_DATA */ + 0x00000000, /* DENALI_PI_81_DATA */ + 0x00000000, /* DENALI_PI_82_DATA */ + 0x01000000, /* DENALI_PI_83_DATA */ + 0x00000101, /* DENALI_PI_84_DATA */ + 0x55555a5a, /* DENALI_PI_85_DATA */ + 0x55555a5a, /* DENALI_PI_86_DATA */ + 0x55555a5a, /* DENALI_PI_87_DATA */ + 0x55555a5a, /* DENALI_PI_88_DATA */ + 0x0c0c0001, /* DENALI_PI_89_DATA */ + 0x0707000c, /* DENALI_PI_90_DATA */ + 0x02020007, /* DENALI_PI_91_DATA */ + 0x00000102, /* DENALI_PI_92_DATA */ + 0x00030000, /* DENALI_PI_93_DATA */ + 0x17030000, /* DENALI_PI_94_DATA */ + 0x000f0021, /* DENALI_PI_95_DATA */ + 0x000f0021, /* DENALI_PI_96_DATA */ + 0x000f0021, /* DENALI_PI_97_DATA */ + 0x00000000, /* DENALI_PI_98_DATA */ + 0x00000000, /* DENALI_PI_99_DATA */ + 0x00000100, /* DENALI_PI_100_DATA */ + 0x140a0000, /* DENALI_PI_101_DATA */ + 0x000a030a, /* DENALI_PI_102_DATA */ + 0x03000a03, /* DENALI_PI_103_DATA */ + 0x010a000a, /* DENALI_PI_104_DATA */ + 0x00000100, /* DENALI_PI_105_DATA */ + 0x01000000, /* DENALI_PI_106_DATA */ + 0x00000000, /* DENALI_PI_107_DATA */ + 0x00000100, /* DENALI_PI_108_DATA */ + 0x1e1a0000, /* DENALI_PI_109_DATA */ + 0x10010204, /* DENALI_PI_110_DATA */ + 0x07070705, /* DENALI_PI_111_DATA */ + 0x20000202, /* DENALI_PI_112_DATA */ + 0x00201000, /* DENALI_PI_113_DATA */ + 0x00201000, /* DENALI_PI_114_DATA */ + 0x04041000, /* DENALI_PI_115_DATA */ + 0x12120100, /* DENALI_PI_116_DATA */ + 0x00010112, /* DENALI_PI_117_DATA */ + 0x004b004a, /* DENALI_PI_118_DATA */ + 0x1a030000, /* DENALI_PI_119_DATA */ + 0x0102041e, /* DENALI_PI_120_DATA */ + 0x34000000, /* DENALI_PI_121_DATA */ + 0x00000000, /* DENALI_PI_122_DATA */ + 0x00000000, /* DENALI_PI_123_DATA */ + 0x00000000, /* DENALI_PI_124_DATA */ + 0x0000c300, /* DENALI_PI_125_DATA */ + 0x0001001c, /* DENALI_PI_126_DATA */ + 0x004d4d07, /* DENALI_PI_127_DATA */ + 0x001c00c3, /* DENALI_PI_128_DATA */ + 0x4d070001, /* DENALI_PI_129_DATA */ + 0x0000c34d, /* DENALI_PI_130_DATA */ + 0x0001001c, /* DENALI_PI_131_DATA */ + 0x004d4d07, /* DENALI_PI_132_DATA */ + 0x001c00c3, /* DENALI_PI_133_DATA */ + 0x4d070001, /* DENALI_PI_134_DATA */ + 0x0000c34d, /* DENALI_PI_135_DATA */ + 0x0001001c, /* DENALI_PI_136_DATA */ + 0x004d4d07, /* DENALI_PI_137_DATA */ + 0x001c00c3, /* DENALI_PI_138_DATA */ + 0x4d070001, /* DENALI_PI_139_DATA */ + 0x00c3004d, /* DENALI_PI_140_DATA */ + 0x0001001c, /* DENALI_PI_141_DATA */ + 0x004d4d07, /* DENALI_PI_142_DATA */ + 0x001c00c3, /* DENALI_PI_143_DATA */ + 0x4d070001, /* DENALI_PI_144_DATA */ + 0x0000c34d, /* DENALI_PI_145_DATA */ + 0x0001001c, /* DENALI_PI_146_DATA */ + 0x004d4d07, /* DENALI_PI_147_DATA */ + 0x001c00c3, /* DENALI_PI_148_DATA */ + 0x4d070001, /* DENALI_PI_149_DATA */ + 0x0000c34d, /* DENALI_PI_150_DATA */ + 0x0001001c, /* DENALI_PI_151_DATA */ + 0x004d4d07, /* DENALI_PI_152_DATA */ + 0x001c00c3, /* DENALI_PI_153_DATA */ + 0x4d070001, /* DENALI_PI_154_DATA */ + 0x0100004d, /* DENALI_PI_155_DATA */ + 0x00ea00ea, /* DENALI_PI_156_DATA */ + 0x080400ea, /* DENALI_PI_157_DATA */ + 0x0f081114, /* DENALI_PI_158_DATA */ + 0x2800fcc1, /* DENALI_PI_159_DATA */ + 0x0a0e2006, /* DENALI_PI_160_DATA */ + 0x1114080a, /* DENALI_PI_161_DATA */ + 0x00000f08, /* DENALI_PI_162_DATA */ + 0x2800fcc1, /* DENALI_PI_163_DATA */ + 0x0a0e2006, /* DENALI_PI_164_DATA */ + 0x1114080a, /* DENALI_PI_165_DATA */ + 0x00000f08, /* DENALI_PI_166_DATA */ + 0x2800fcc1, /* DENALI_PI_167_DATA */ + 0x0a0e2006, /* DENALI_PI_168_DATA */ + 0x0200020a, /* DENALI_PI_169_DATA */ + 0x02000200, /* DENALI_PI_170_DATA */ + 0x02000200, /* DENALI_PI_171_DATA */ + 0x02000200, /* DENALI_PI_172_DATA */ + 0x02000200, /* DENALI_PI_173_DATA */ + 0x00000000, /* DENALI_PI_174_DATA */ + 0x00000000, /* DENALI_PI_175_DATA */ + 0x00000000, /* DENALI_PI_176_DATA */ + 0x00000000, /* DENALI_PI_177_DATA */ + 0x00000000, /* DENALI_PI_178_DATA */ + 0x00000000, /* DENALI_PI_179_DATA */ + 0x00000000, /* DENALI_PI_180_DATA */ + 0x00000000, /* DENALI_PI_181_DATA */ + 0x00000000, /* DENALI_PI_182_DATA */ + 0x00000000, /* DENALI_PI_183_DATA */ + 0x00000000, /* DENALI_PI_184_DATA */ + 0x00000000, /* DENALI_PI_185_DATA */ + 0x01000300, /* DENALI_PI_186_DATA */ + 0x001c6200, /* DENALI_PI_187_DATA */ + 0x00011bd4, /* DENALI_PI_188_DATA */ + 0x00001c62, /* DENALI_PI_189_DATA */ + 0x00011bd4, /* DENALI_PI_190_DATA */ + 0x00001c62, /* DENALI_PI_191_DATA */ + 0x00011bd4, /* DENALI_PI_192_DATA */ + 0x08000000, /* DENALI_PI_193_DATA */ + 0x00000100, /* DENALI_PI_194_DATA */ + 0x00000000, /* DENALI_PI_195_DATA */ + 0x00000000, /* DENALI_PI_196_DATA */ + 0x00000000, /* DENALI_PI_197_DATA */ + 0x00000000, /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + } + }, + { + { + 0x76543210, /* DENALI_PHY_00_DATA */ + 0x0004c008, /* DENALI_PHY_01_DATA */ + 0x000001a2, /* DENALI_PHY_02_DATA */ + 0x00000000, /* DENALI_PHY_03_DATA */ + 0x00000000, /* DENALI_PHY_04_DATA */ + 0x00010000, /* DENALI_PHY_05_DATA */ + 0x01665555, /* DENALI_PHY_06_DATA */ + 0x00665555, /* DENALI_PHY_07_DATA */ + 0x00010f00, /* DENALI_PHY_08_DATA */ + 0x06010200, /* DENALI_PHY_09_DATA */ + 0x00000003, /* DENALI_PHY_10_DATA */ + 0x001700c0, /* DENALI_PHY_11_DATA */ + 0x00cc0101, /* DENALI_PHY_12_DATA */ + 0x00030066, /* DENALI_PHY_13_DATA */ + 0x00000000, /* DENALI_PHY_14_DATA */ + 0x00000000, /* DENALI_PHY_15_DATA */ + 0x00000000, /* DENALI_PHY_16_DATA */ + 0x00000000, /* DENALI_PHY_17_DATA */ + 0x00000000, /* DENALI_PHY_18_DATA */ + 0x00000000, /* DENALI_PHY_19_DATA */ + 0x00000000, /* DENALI_PHY_20_DATA */ + 0x00000000, /* DENALI_PHY_21_DATA */ + 0x04080000, /* DENALI_PHY_22_DATA */ + 0x04080400, /* DENALI_PHY_23_DATA */ + 0x08000000, /* DENALI_PHY_24_DATA */ + 0x0c00c007, /* DENALI_PHY_25_DATA */ + 0x00000100, /* DENALI_PHY_26_DATA */ + 0x00000100, /* DENALI_PHY_27_DATA */ + 0x55555555, /* DENALI_PHY_28_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_29_DATA */ + 0x55555555, /* DENALI_PHY_30_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_31_DATA */ + 0x00005555, /* DENALI_PHY_32_DATA */ + 0x00000000, /* DENALI_PHY_33_DATA */ + 0x00000000, /* DENALI_PHY_34_DATA */ + 0x00000000, /* DENALI_PHY_35_DATA */ + 0x00000000, /* DENALI_PHY_36_DATA */ + 0x00000000, /* DENALI_PHY_37_DATA */ + 0x00000000, /* DENALI_PHY_38_DATA */ + 0x00000000, /* DENALI_PHY_39_DATA */ + 0x00000000, /* DENALI_PHY_40_DATA */ + 0x00000000, /* DENALI_PHY_41_DATA */ + 0x00000000, /* DENALI_PHY_42_DATA */ + 0x00000000, /* DENALI_PHY_43_DATA */ + 0x00000000, /* DENALI_PHY_44_DATA */ + 0x00000000, /* DENALI_PHY_45_DATA */ + 0x00000000, /* DENALI_PHY_46_DATA */ + 0x00000000, /* DENALI_PHY_47_DATA */ + 0x00000000, /* DENALI_PHY_48_DATA */ + 0x00000000, /* DENALI_PHY_49_DATA */ + 0x00000000, /* DENALI_PHY_50_DATA */ + 0x00000000, /* DENALI_PHY_51_DATA */ + 0x00200000, /* DENALI_PHY_52_DATA */ + 0x00000000, /* DENALI_PHY_53_DATA */ + 0x00000000, /* DENALI_PHY_54_DATA */ + 0x00000000, /* DENALI_PHY_55_DATA */ + 0x00000000, /* DENALI_PHY_56_DATA */ + 0x00000000, /* DENALI_PHY_57_DATA */ + 0x00000000, /* DENALI_PHY_58_DATA */ + 0x02600260, /* DENALI_PHY_59_DATA */ + 0x02600260, /* DENALI_PHY_60_DATA */ + 0x02600260, /* DENALI_PHY_61_DATA */ + 0x02600260, /* DENALI_PHY_62_DATA */ + 0x00000260, /* DENALI_PHY_63_DATA */ + 0x00000000, /* DENALI_PHY_64_DATA */ + 0x00000000, /* DENALI_PHY_65_DATA */ + 0x00000000, /* DENALI_PHY_66_DATA */ + 0x00000000, /* DENALI_PHY_67_DATA */ + 0x00800000, /* DENALI_PHY_68_DATA */ + 0x00800080, /* DENALI_PHY_69_DATA */ + 0x00800080, /* DENALI_PHY_70_DATA */ + 0x00800080, /* DENALI_PHY_71_DATA */ + 0x00800080, /* DENALI_PHY_72_DATA */ + 0x00800080, /* DENALI_PHY_73_DATA */ + 0x00800080, /* DENALI_PHY_74_DATA */ + 0x00800080, /* DENALI_PHY_75_DATA */ + 0x00800080, /* DENALI_PHY_76_DATA */ + 0x01a20080, /* DENALI_PHY_77_DATA */ + 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000000, /* DENALI_PHY_79_DATA */ + 0x00030000, /* DENALI_PHY_80_DATA */ + 0x00000200, /* DENALI_PHY_81_DATA */ + 0x00000000, /* DENALI_PHY_82_DATA */ + 0x51315152, /* DENALI_PHY_83_DATA */ + 0xc0013150, /* DENALI_PHY_84_DATA */ + 0x020000c0, /* DENALI_PHY_85_DATA */ + 0x00100001, /* DENALI_PHY_86_DATA */ + 0x0c064208, /* DENALI_PHY_87_DATA */ + 0x000f0c18, /* DENALI_PHY_88_DATA */ + 0x01000140, /* DENALI_PHY_89_DATA */ + 0x00000c20, /* DENALI_PHY_90_DATA */ + 0x00000000, /* DENALI_PHY_91_DATA */ + 0x00000000, /* DENALI_PHY_92_DATA */ + 0x00000000, /* DENALI_PHY_93_DATA */ + 0x00000000, /* DENALI_PHY_94_DATA */ + 0x00000000, /* DENALI_PHY_95_DATA */ + 0x00000000, /* DENALI_PHY_96_DATA */ + 0x00000000, /* DENALI_PHY_97_DATA */ + 0x00000000, /* DENALI_PHY_98_DATA */ + 0x00000000, /* DENALI_PHY_99_DATA */ + 0x00000000, /* DENALI_PHY_100_DATA */ + 0x00000000, /* DENALI_PHY_101_DATA */ + 0x00000000, /* DENALI_PHY_102_DATA */ + 0x00000000, /* DENALI_PHY_103_DATA */ + 0x00000000, /* DENALI_PHY_104_DATA */ + 0x00000000, /* DENALI_PHY_105_DATA */ + 0x00000000, /* DENALI_PHY_106_DATA */ + 0x00000000, /* DENALI_PHY_107_DATA */ + 0x00000000, /* DENALI_PHY_108_DATA */ + 0x00000000, /* DENALI_PHY_109_DATA */ + 0x00000000, /* DENALI_PHY_110_DATA */ + 0x00000000, /* DENALI_PHY_111_DATA */ + 0x00000000, /* DENALI_PHY_112_DATA */ + 0x00000000, /* DENALI_PHY_113_DATA */ + 0x00000000, /* DENALI_PHY_114_DATA */ + 0x00000000, /* DENALI_PHY_115_DATA */ + 0x00000000, /* DENALI_PHY_116_DATA */ + 0x00000000, /* DENALI_PHY_117_DATA */ + 0x00000000, /* DENALI_PHY_118_DATA */ + 0x00000000, /* DENALI_PHY_119_DATA */ + 0x00000000, /* DENALI_PHY_120_DATA */ + 0x00000000, /* DENALI_PHY_121_DATA */ + 0x00000000, /* DENALI_PHY_122_DATA */ + 0x00000000, /* DENALI_PHY_123_DATA */ + 0x00000000, /* DENALI_PHY_124_DATA */ + 0x00000000, /* DENALI_PHY_125_DATA */ + 0x00000000, /* DENALI_PHY_126_DATA */ + 0x00000000, /* DENALI_PHY_127_DATA */ + 0x76543210, /* DENALI_PHY_128_DATA */ + 0x0004c008, /* DENALI_PHY_129_DATA */ + 0x000001a2, /* DENALI_PHY_130_DATA */ + 0x00000000, /* DENALI_PHY_131_DATA */ + 0x00000000, /* DENALI_PHY_132_DATA */ + 0x00010000, /* DENALI_PHY_133_DATA */ + 0x01665555, /* DENALI_PHY_134_DATA */ + 0x00665555, /* DENALI_PHY_135_DATA */ + 0x00010f00, /* DENALI_PHY_136_DATA */ + 0x06010200, /* DENALI_PHY_137_DATA */ + 0x00000003, /* DENALI_PHY_138_DATA */ + 0x001700c0, /* DENALI_PHY_139_DATA */ + 0x00cc0101, /* DENALI_PHY_140_DATA */ + 0x00030066, /* DENALI_PHY_141_DATA */ + 0x00000000, /* DENALI_PHY_142_DATA */ + 0x00000000, /* DENALI_PHY_143_DATA */ + 0x00000000, /* DENALI_PHY_144_DATA */ + 0x00000000, /* DENALI_PHY_145_DATA */ + 0x00000000, /* DENALI_PHY_146_DATA */ + 0x00000000, /* DENALI_PHY_147_DATA */ + 0x00000000, /* DENALI_PHY_148_DATA */ + 0x00000000, /* DENALI_PHY_149_DATA */ + 0x04080000, /* DENALI_PHY_150_DATA */ + 0x04080400, /* DENALI_PHY_151_DATA */ + 0x08000000, /* DENALI_PHY_152_DATA */ + 0x0c00c007, /* DENALI_PHY_153_DATA */ + 0x00000100, /* DENALI_PHY_154_DATA */ + 0x00000100, /* DENALI_PHY_155_DATA */ + 0x55555555, /* DENALI_PHY_156_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_157_DATA */ + 0x55555555, /* DENALI_PHY_158_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_159_DATA */ + 0x00005555, /* DENALI_PHY_160_DATA */ + 0x00000000, /* DENALI_PHY_161_DATA */ + 0x00000000, /* DENALI_PHY_162_DATA */ + 0x00000000, /* DENALI_PHY_163_DATA */ + 0x00000000, /* DENALI_PHY_164_DATA */ + 0x00000000, /* DENALI_PHY_165_DATA */ + 0x00000000, /* DENALI_PHY_166_DATA */ + 0x00000000, /* DENALI_PHY_167_DATA */ + 0x00000000, /* DENALI_PHY_168_DATA */ + 0x00000000, /* DENALI_PHY_169_DATA */ + 0x00000000, /* DENALI_PHY_170_DATA */ + 0x00000000, /* DENALI_PHY_171_DATA */ + 0x00000000, /* DENALI_PHY_172_DATA */ + 0x00000000, /* DENALI_PHY_173_DATA */ + 0x00000000, /* DENALI_PHY_174_DATA */ + 0x00000000, /* DENALI_PHY_175_DATA */ + 0x00000000, /* DENALI_PHY_176_DATA */ + 0x00000000, /* DENALI_PHY_177_DATA */ + 0x00000000, /* DENALI_PHY_178_DATA */ + 0x00000000, /* DENALI_PHY_179_DATA */ + 0x00200000, /* DENALI_PHY_180_DATA */ + 0x00000000, /* DENALI_PHY_181_DATA */ + 0x00000000, /* DENALI_PHY_182_DATA */ + 0x00000000, /* DENALI_PHY_183_DATA */ + 0x00000000, /* DENALI_PHY_184_DATA */ + 0x00000000, /* DENALI_PHY_185_DATA */ + 0x00000000, /* DENALI_PHY_186_DATA */ + 0x02600260, /* DENALI_PHY_187_DATA */ + 0x02600260, /* DENALI_PHY_188_DATA */ + 0x02600260, /* DENALI_PHY_189_DATA */ + 0x02600260, /* DENALI_PHY_190_DATA */ + 0x00000260, /* DENALI_PHY_191_DATA */ + 0x00000000, /* DENALI_PHY_192_DATA */ + 0x00000000, /* DENALI_PHY_193_DATA */ + 0x00000000, /* DENALI_PHY_194_DATA */ + 0x00000000, /* DENALI_PHY_195_DATA */ + 0x00800000, /* DENALI_PHY_196_DATA */ + 0x00800080, /* DENALI_PHY_197_DATA */ + 0x00800080, /* DENALI_PHY_198_DATA */ + 0x00800080, /* DENALI_PHY_199_DATA */ + 0x00800080, /* DENALI_PHY_200_DATA */ + 0x00800080, /* DENALI_PHY_201_DATA */ + 0x00800080, /* DENALI_PHY_202_DATA */ + 0x00800080, /* DENALI_PHY_203_DATA */ + 0x00800080, /* DENALI_PHY_204_DATA */ + 0x01a20080, /* DENALI_PHY_205_DATA */ + 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000000, /* DENALI_PHY_207_DATA */ + 0x00030000, /* DENALI_PHY_208_DATA */ + 0x00000200, /* DENALI_PHY_209_DATA */ + 0x00000000, /* DENALI_PHY_210_DATA */ + 0x51315152, /* DENALI_PHY_211_DATA */ + 0xc0013150, /* DENALI_PHY_212_DATA */ + 0x020000c0, /* DENALI_PHY_213_DATA */ + 0x00100001, /* DENALI_PHY_214_DATA */ + 0x0c064208, /* DENALI_PHY_215_DATA */ + 0x000f0c18, /* DENALI_PHY_216_DATA */ + 0x01000140, /* DENALI_PHY_217_DATA */ + 0x00000c20, /* DENALI_PHY_218_DATA */ + 0x00000000, /* DENALI_PHY_219_DATA */ + 0x00000000, /* DENALI_PHY_220_DATA */ + 0x00000000, /* DENALI_PHY_221_DATA */ + 0x00000000, /* DENALI_PHY_222_DATA */ + 0x00000000, /* DENALI_PHY_223_DATA */ + 0x00000000, /* DENALI_PHY_224_DATA */ + 0x00000000, /* DENALI_PHY_225_DATA */ + 0x00000000, /* DENALI_PHY_226_DATA */ + 0x00000000, /* DENALI_PHY_227_DATA */ + 0x00000000, /* DENALI_PHY_228_DATA */ + 0x00000000, /* DENALI_PHY_229_DATA */ + 0x00000000, /* DENALI_PHY_230_DATA */ + 0x00000000, /* DENALI_PHY_231_DATA */ + 0x00000000, /* DENALI_PHY_232_DATA */ + 0x00000000, /* DENALI_PHY_233_DATA */ + 0x00000000, /* DENALI_PHY_234_DATA */ + 0x00000000, /* DENALI_PHY_235_DATA */ + 0x00000000, /* DENALI_PHY_236_DATA */ + 0x00000000, /* DENALI_PHY_237_DATA */ + 0x00000000, /* DENALI_PHY_238_DATA */ + 0x00000000, /* DENALI_PHY_239_DATA */ + 0x00000000, /* DENALI_PHY_240_DATA */ + 0x00000000, /* DENALI_PHY_241_DATA */ + 0x00000000, /* DENALI_PHY_242_DATA */ + 0x00000000, /* DENALI_PHY_243_DATA */ + 0x00000000, /* DENALI_PHY_244_DATA */ + 0x00000000, /* DENALI_PHY_245_DATA */ + 0x00000000, /* DENALI_PHY_246_DATA */ + 0x00000000, /* DENALI_PHY_247_DATA */ + 0x00000000, /* DENALI_PHY_248_DATA */ + 0x00000000, /* DENALI_PHY_249_DATA */ + 0x00000000, /* DENALI_PHY_250_DATA */ + 0x00000000, /* DENALI_PHY_251_DATA */ + 0x00000000, /* DENALI_PHY_252_DATA */ + 0x00000000, /* DENALI_PHY_253_DATA */ + 0x00000000, /* DENALI_PHY_254_DATA */ + 0x00000000, /* DENALI_PHY_255_DATA */ + 0x76543210, /* DENALI_PHY_256_DATA */ + 0x0004c008, /* DENALI_PHY_257_DATA */ + 0x000001a2, /* DENALI_PHY_258_DATA */ + 0x00000000, /* DENALI_PHY_259_DATA */ + 0x00000000, /* DENALI_PHY_260_DATA */ + 0x00010000, /* DENALI_PHY_261_DATA */ + 0x01665555, /* DENALI_PHY_262_DATA */ + 0x00665555, /* DENALI_PHY_263_DATA */ + 0x00010f00, /* DENALI_PHY_264_DATA */ + 0x06010200, /* DENALI_PHY_265_DATA */ + 0x00000003, /* DENALI_PHY_266_DATA */ + 0x001700c0, /* DENALI_PHY_267_DATA */ + 0x00cc0101, /* DENALI_PHY_268_DATA */ + 0x00030066, /* DENALI_PHY_269_DATA */ + 0x00000000, /* DENALI_PHY_270_DATA */ + 0x00000000, /* DENALI_PHY_271_DATA */ + 0x00000000, /* DENALI_PHY_272_DATA */ + 0x00000000, /* DENALI_PHY_273_DATA */ + 0x00000000, /* DENALI_PHY_274_DATA */ + 0x00000000, /* DENALI_PHY_275_DATA */ + 0x00000000, /* DENALI_PHY_276_DATA */ + 0x00000000, /* DENALI_PHY_277_DATA */ + 0x04080000, /* DENALI_PHY_278_DATA */ + 0x04080400, /* DENALI_PHY_279_DATA */ + 0x08000000, /* DENALI_PHY_280_DATA */ + 0x0c00c007, /* DENALI_PHY_281_DATA */ + 0x00000100, /* DENALI_PHY_282_DATA */ + 0x00000100, /* DENALI_PHY_283_DATA */ + 0x55555555, /* DENALI_PHY_284_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_285_DATA */ + 0x55555555, /* DENALI_PHY_286_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_287_DATA */ + 0x00005555, /* DENALI_PHY_288_DATA */ + 0x00000000, /* DENALI_PHY_289_DATA */ + 0x00000000, /* DENALI_PHY_290_DATA */ + 0x00000000, /* DENALI_PHY_291_DATA */ + 0x00000000, /* DENALI_PHY_292_DATA */ + 0x00000000, /* DENALI_PHY_293_DATA */ + 0x00000000, /* DENALI_PHY_294_DATA */ + 0x00000000, /* DENALI_PHY_295_DATA */ + 0x00000000, /* DENALI_PHY_296_DATA */ + 0x00000000, /* DENALI_PHY_297_DATA */ + 0x00000000, /* DENALI_PHY_298_DATA */ + 0x00000000, /* DENALI_PHY_299_DATA */ + 0x00000000, /* DENALI_PHY_300_DATA */ + 0x00000000, /* DENALI_PHY_301_DATA */ + 0x00000000, /* DENALI_PHY_302_DATA */ + 0x00000000, /* DENALI_PHY_303_DATA */ + 0x00000000, /* DENALI_PHY_304_DATA */ + 0x00000000, /* DENALI_PHY_305_DATA */ + 0x00000000, /* DENALI_PHY_306_DATA */ + 0x00000000, /* DENALI_PHY_307_DATA */ + 0x00200000, /* DENALI_PHY_308_DATA */ + 0x00000000, /* DENALI_PHY_309_DATA */ + 0x00000000, /* DENALI_PHY_310_DATA */ + 0x00000000, /* DENALI_PHY_311_DATA */ + 0x00000000, /* DENALI_PHY_312_DATA */ + 0x00000000, /* DENALI_PHY_313_DATA */ + 0x00000000, /* DENALI_PHY_314_DATA */ + 0x02600260, /* DENALI_PHY_315_DATA */ + 0x02600260, /* DENALI_PHY_316_DATA */ + 0x02600260, /* DENALI_PHY_317_DATA */ + 0x02600260, /* DENALI_PHY_318_DATA */ + 0x00000260, /* DENALI_PHY_319_DATA */ + 0x00000000, /* DENALI_PHY_320_DATA */ + 0x00000000, /* DENALI_PHY_321_DATA */ + 0x00000000, /* DENALI_PHY_322_DATA */ + 0x00000000, /* DENALI_PHY_323_DATA */ + 0x00800000, /* DENALI_PHY_324_DATA */ + 0x00800080, /* DENALI_PHY_325_DATA */ + 0x00800080, /* DENALI_PHY_326_DATA */ + 0x00800080, /* DENALI_PHY_327_DATA */ + 0x00800080, /* DENALI_PHY_328_DATA */ + 0x00800080, /* DENALI_PHY_329_DATA */ + 0x00800080, /* DENALI_PHY_330_DATA */ + 0x00800080, /* DENALI_PHY_331_DATA */ + 0x00800080, /* DENALI_PHY_332_DATA */ + 0x01a20080, /* DENALI_PHY_333_DATA */ + 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000000, /* DENALI_PHY_335_DATA */ + 0x00030000, /* DENALI_PHY_336_DATA */ + 0x00000200, /* DENALI_PHY_337_DATA */ + 0x00000000, /* DENALI_PHY_338_DATA */ + 0x51315152, /* DENALI_PHY_339_DATA */ + 0xc0013150, /* DENALI_PHY_340_DATA */ + 0x020000c0, /* DENALI_PHY_341_DATA */ + 0x00100001, /* DENALI_PHY_342_DATA */ + 0x0c064208, /* DENALI_PHY_343_DATA */ + 0x000f0c18, /* DENALI_PHY_344_DATA */ + 0x01000140, /* DENALI_PHY_345_DATA */ + 0x00000c20, /* DENALI_PHY_346_DATA */ + 0x00000000, /* DENALI_PHY_347_DATA */ + 0x00000000, /* DENALI_PHY_348_DATA */ + 0x00000000, /* DENALI_PHY_349_DATA */ + 0x00000000, /* DENALI_PHY_350_DATA */ + 0x00000000, /* DENALI_PHY_351_DATA */ + 0x00000000, /* DENALI_PHY_352_DATA */ + 0x00000000, /* DENALI_PHY_353_DATA */ + 0x00000000, /* DENALI_PHY_354_DATA */ + 0x00000000, /* DENALI_PHY_355_DATA */ + 0x00000000, /* DENALI_PHY_356_DATA */ + 0x00000000, /* DENALI_PHY_357_DATA */ + 0x00000000, /* DENALI_PHY_358_DATA */ + 0x00000000, /* DENALI_PHY_359_DATA */ + 0x00000000, /* DENALI_PHY_360_DATA */ + 0x00000000, /* DENALI_PHY_361_DATA */ + 0x00000000, /* DENALI_PHY_362_DATA */ + 0x00000000, /* DENALI_PHY_363_DATA */ + 0x00000000, /* DENALI_PHY_364_DATA */ + 0x00000000, /* DENALI_PHY_365_DATA */ + 0x00000000, /* DENALI_PHY_366_DATA */ + 0x00000000, /* DENALI_PHY_367_DATA */ + 0x00000000, /* DENALI_PHY_368_DATA */ + 0x00000000, /* DENALI_PHY_369_DATA */ + 0x00000000, /* DENALI_PHY_370_DATA */ + 0x00000000, /* DENALI_PHY_371_DATA */ + 0x00000000, /* DENALI_PHY_372_DATA */ + 0x00000000, /* DENALI_PHY_373_DATA */ + 0x00000000, /* DENALI_PHY_374_DATA */ + 0x00000000, /* DENALI_PHY_375_DATA */ + 0x00000000, /* DENALI_PHY_376_DATA */ + 0x00000000, /* DENALI_PHY_377_DATA */ + 0x00000000, /* DENALI_PHY_378_DATA */ + 0x00000000, /* DENALI_PHY_379_DATA */ + 0x00000000, /* DENALI_PHY_380_DATA */ + 0x00000000, /* DENALI_PHY_381_DATA */ + 0x00000000, /* DENALI_PHY_382_DATA */ + 0x00000000, /* DENALI_PHY_383_DATA */ + 0x76543210, /* DENALI_PHY_384_DATA */ + 0x0004c008, /* DENALI_PHY_385_DATA */ + 0x000001a2, /* DENALI_PHY_386_DATA */ + 0x00000000, /* DENALI_PHY_387_DATA */ + 0x00000000, /* DENALI_PHY_388_DATA */ + 0x00010000, /* DENALI_PHY_389_DATA */ + 0x01665555, /* DENALI_PHY_390_DATA */ + 0x00665555, /* DENALI_PHY_391_DATA */ + 0x00010f00, /* DENALI_PHY_392_DATA */ + 0x06010200, /* DENALI_PHY_393_DATA */ + 0x00000003, /* DENALI_PHY_394_DATA */ + 0x001700c0, /* DENALI_PHY_395_DATA */ + 0x00cc0101, /* DENALI_PHY_396_DATA */ + 0x00030066, /* DENALI_PHY_397_DATA */ + 0x00000000, /* DENALI_PHY_398_DATA */ + 0x00000000, /* DENALI_PHY_399_DATA */ + 0x00000000, /* DENALI_PHY_400_DATA */ + 0x00000000, /* DENALI_PHY_401_DATA */ + 0x00000000, /* DENALI_PHY_402_DATA */ + 0x00000000, /* DENALI_PHY_403_DATA */ + 0x00000000, /* DENALI_PHY_404_DATA */ + 0x00000000, /* DENALI_PHY_405_DATA */ + 0x04080000, /* DENALI_PHY_406_DATA */ + 0x04080400, /* DENALI_PHY_407_DATA */ + 0x08000000, /* DENALI_PHY_408_DATA */ + 0x0c00c007, /* DENALI_PHY_409_DATA */ + 0x00000100, /* DENALI_PHY_410_DATA */ + 0x00000100, /* DENALI_PHY_411_DATA */ + 0x55555555, /* DENALI_PHY_412_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_413_DATA */ + 0x55555555, /* DENALI_PHY_414_DATA */ + 0xaaaaaaaa, /* DENALI_PHY_415_DATA */ + 0x00005555, /* DENALI_PHY_416_DATA */ + 0x00000000, /* DENALI_PHY_417_DATA */ + 0x00000000, /* DENALI_PHY_418_DATA */ + 0x00000000, /* DENALI_PHY_419_DATA */ + 0x00000000, /* DENALI_PHY_420_DATA */ + 0x00000000, /* DENALI_PHY_421_DATA */ + 0x00000000, /* DENALI_PHY_422_DATA */ + 0x00000000, /* DENALI_PHY_423_DATA */ + 0x00000000, /* DENALI_PHY_424_DATA */ + 0x00000000, /* DENALI_PHY_425_DATA */ + 0x00000000, /* DENALI_PHY_426_DATA */ + 0x00000000, /* DENALI_PHY_427_DATA */ + 0x00000000, /* DENALI_PHY_428_DATA */ + 0x00000000, /* DENALI_PHY_429_DATA */ + 0x00000000, /* DENALI_PHY_430_DATA */ + 0x00000000, /* DENALI_PHY_431_DATA */ + 0x00000000, /* DENALI_PHY_432_DATA */ + 0x00000000, /* DENALI_PHY_433_DATA */ + 0x00000000, /* DENALI_PHY_434_DATA */ + 0x00000000, /* DENALI_PHY_435_DATA */ + 0x00200000, /* DENALI_PHY_436_DATA */ + 0x00000000, /* DENALI_PHY_437_DATA */ + 0x00000000, /* DENALI_PHY_438_DATA */ + 0x00000000, /* DENALI_PHY_439_DATA */ + 0x00000000, /* DENALI_PHY_440_DATA */ + 0x00000000, /* DENALI_PHY_441_DATA */ + 0x00000000, /* DENALI_PHY_442_DATA */ + 0x02600260, /* DENALI_PHY_443_DATA */ + 0x02600260, /* DENALI_PHY_444_DATA */ + 0x02600260, /* DENALI_PHY_445_DATA */ + 0x02600260, /* DENALI_PHY_446_DATA */ + 0x00000260, /* DENALI_PHY_447_DATA */ + 0x00000000, /* DENALI_PHY_448_DATA */ + 0x00000000, /* DENALI_PHY_449_DATA */ + 0x00000000, /* DENALI_PHY_450_DATA */ + 0x00000000, /* DENALI_PHY_451_DATA */ + 0x00800000, /* DENALI_PHY_452_DATA */ + 0x00800080, /* DENALI_PHY_453_DATA */ + 0x00800080, /* DENALI_PHY_454_DATA */ + 0x00800080, /* DENALI_PHY_455_DATA */ + 0x00800080, /* DENALI_PHY_456_DATA */ + 0x00800080, /* DENALI_PHY_457_DATA */ + 0x00800080, /* DENALI_PHY_458_DATA */ + 0x00800080, /* DENALI_PHY_459_DATA */ + 0x00800080, /* DENALI_PHY_460_DATA */ + 0x01a20080, /* DENALI_PHY_461_DATA */ + 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000000, /* DENALI_PHY_463_DATA */ + 0x00030000, /* DENALI_PHY_464_DATA */ + 0x00000200, /* DENALI_PHY_465_DATA */ + 0x00000000, /* DENALI_PHY_466_DATA */ + 0x51315152, /* DENALI_PHY_467_DATA */ + 0xc0013150, /* DENALI_PHY_468_DATA */ + 0x020000c0, /* DENALI_PHY_469_DATA */ + 0x00100001, /* DENALI_PHY_470_DATA */ + 0x0c064208, /* DENALI_PHY_471_DATA */ + 0x000f0c18, /* DENALI_PHY_472_DATA */ + 0x01000140, /* DENALI_PHY_473_DATA */ + 0x00000c20, /* DENALI_PHY_474_DATA */ + 0x00000000, /* DENALI_PHY_475_DATA */ + 0x00000000, /* DENALI_PHY_476_DATA */ + 0x00000000, /* DENALI_PHY_477_DATA */ + 0x00000000, /* DENALI_PHY_478_DATA */ + 0x00000000, /* DENALI_PHY_479_DATA */ + 0x00000000, /* DENALI_PHY_480_DATA */ + 0x00000000, /* DENALI_PHY_481_DATA */ + 0x00000000, /* DENALI_PHY_482_DATA */ + 0x00000000, /* DENALI_PHY_483_DATA */ + 0x00000000, /* DENALI_PHY_484_DATA */ + 0x00000000, /* DENALI_PHY_485_DATA */ + 0x00000000, /* DENALI_PHY_486_DATA */ + 0x00000000, /* DENALI_PHY_487_DATA */ + 0x00000000, /* DENALI_PHY_488_DATA */ + 0x00000000, /* DENALI_PHY_489_DATA */ + 0x00000000, /* DENALI_PHY_490_DATA */ + 0x00000000, /* DENALI_PHY_491_DATA */ + 0x00000000, /* DENALI_PHY_492_DATA */ + 0x00000000, /* DENALI_PHY_493_DATA */ + 0x00000000, /* DENALI_PHY_494_DATA */ + 0x00000000, /* DENALI_PHY_495_DATA */ + 0x00000000, /* DENALI_PHY_496_DATA */ + 0x00000000, /* DENALI_PHY_497_DATA */ + 0x00000000, /* DENALI_PHY_498_DATA */ + 0x00000000, /* DENALI_PHY_499_DATA */ + 0x00000000, /* DENALI_PHY_500_DATA */ + 0x00000000, /* DENALI_PHY_501_DATA */ + 0x00000000, /* DENALI_PHY_502_DATA */ + 0x00000000, /* DENALI_PHY_503_DATA */ + 0x00000000, /* DENALI_PHY_504_DATA */ + 0x00000000, /* DENALI_PHY_505_DATA */ + 0x00000000, /* DENALI_PHY_506_DATA */ + 0x00000000, /* DENALI_PHY_507_DATA */ + 0x00000000, /* DENALI_PHY_508_DATA */ + 0x00000000, /* DENALI_PHY_509_DATA */ + 0x00000000, /* DENALI_PHY_510_DATA */ + 0x00000000, /* DENALI_PHY_511_DATA */ + 0x00000000, /* DENALI_PHY_512_DATA */ + 0x00800000, /* DENALI_PHY_513_DATA */ + 0x00000000, /* DENALI_PHY_514_DATA */ + 0x00000000, /* DENALI_PHY_515_DATA */ + 0x00000000, /* DENALI_PHY_516_DATA */ + 0x00000000, /* DENALI_PHY_517_DATA */ + 0x00000000, /* DENALI_PHY_518_DATA */ + 0x00000001, /* DENALI_PHY_519_DATA */ + 0x00000000, /* DENALI_PHY_520_DATA */ + 0x00000000, /* DENALI_PHY_521_DATA */ + 0x00000000, /* DENALI_PHY_522_DATA */ + 0x00400320, /* DENALI_PHY_523_DATA */ + 0x00000040, /* DENALI_PHY_524_DATA */ + 0x00806420, /* DENALI_PHY_525_DATA */ + 0x00917531, /* DENALI_PHY_526_DATA */ + 0x00806420, /* DENALI_PHY_527_DATA */ + 0x01917531, /* DENALI_PHY_528_DATA */ + 0x00020003, /* DENALI_PHY_529_DATA */ + 0x00000000, /* DENALI_PHY_530_DATA */ + 0x00000000, /* DENALI_PHY_531_DATA */ + 0x00000000, /* DENALI_PHY_532_DATA */ + 0x000556aa, /* DENALI_PHY_533_DATA */ + 0x000aaaaa, /* DENALI_PHY_534_DATA */ + 0x000aa955, /* DENALI_PHY_535_DATA */ + 0x00055555, /* DENALI_PHY_536_DATA */ + 0x000b3133, /* DENALI_PHY_537_DATA */ + 0x0004cd33, /* DENALI_PHY_538_DATA */ + 0x0004cecc, /* DENALI_PHY_539_DATA */ + 0x000b32cc, /* DENALI_PHY_540_DATA */ + 0x0a418820, /* DENALI_PHY_541_DATA */ + 0x103f0000, /* DENALI_PHY_542_DATA */ + 0x0000003f, /* DENALI_PHY_543_DATA */ + 0x00038055, /* DENALI_PHY_544_DATA */ + 0x03800380, /* DENALI_PHY_545_DATA */ + 0x03800380, /* DENALI_PHY_546_DATA */ + 0x00000380, /* DENALI_PHY_547_DATA */ + 0x42080010, /* DENALI_PHY_548_DATA */ + 0x00000003, /* DENALI_PHY_549_DATA */ + 0x00000000, /* DENALI_PHY_550_DATA */ + 0x00000000, /* DENALI_PHY_551_DATA */ + 0x00000000, /* DENALI_PHY_552_DATA */ + 0x00000000, /* DENALI_PHY_553_DATA */ + 0x00000000, /* DENALI_PHY_554_DATA */ + 0x00000000, /* DENALI_PHY_555_DATA */ + 0x00000000, /* DENALI_PHY_556_DATA */ + 0x00000000, /* DENALI_PHY_557_DATA */ + 0x00000000, /* DENALI_PHY_558_DATA */ + 0x00000000, /* DENALI_PHY_559_DATA */ + 0x00000000, /* DENALI_PHY_560_DATA */ + 0x00000000, /* DENALI_PHY_561_DATA */ + 0x00000000, /* DENALI_PHY_562_DATA */ + 0x00000000, /* DENALI_PHY_563_DATA */ + 0x00000000, /* DENALI_PHY_564_DATA */ + 0x00000000, /* DENALI_PHY_565_DATA */ + 0x00000000, /* DENALI_PHY_566_DATA */ + 0x00000000, /* DENALI_PHY_567_DATA */ + 0x00000000, /* DENALI_PHY_568_DATA */ + 0x00000000, /* DENALI_PHY_569_DATA */ + 0x00000000, /* DENALI_PHY_570_DATA */ + 0x00000000, /* DENALI_PHY_571_DATA */ + 0x00000000, /* DENALI_PHY_572_DATA */ + 0x00000000, /* DENALI_PHY_573_DATA */ + 0x00000000, /* DENALI_PHY_574_DATA */ + 0x00000000, /* DENALI_PHY_575_DATA */ + 0x00000000, /* DENALI_PHY_576_DATA */ + 0x00000000, /* DENALI_PHY_577_DATA */ + 0x00000000, /* DENALI_PHY_578_DATA */ + 0x00000000, /* DENALI_PHY_579_DATA */ + 0x00000000, /* DENALI_PHY_580_DATA */ + 0x00000000, /* DENALI_PHY_581_DATA */ + 0x00000000, /* DENALI_PHY_582_DATA */ + 0x00000000, /* DENALI_PHY_583_DATA */ + 0x00000000, /* DENALI_PHY_584_DATA */ + 0x00000000, /* DENALI_PHY_585_DATA */ + 0x00000000, /* DENALI_PHY_586_DATA */ + 0x00000000, /* DENALI_PHY_587_DATA */ + 0x00000000, /* DENALI_PHY_588_DATA */ + 0x00000000, /* DENALI_PHY_589_DATA */ + 0x00000000, /* DENALI_PHY_590_DATA */ + 0x00000000, /* DENALI_PHY_591_DATA */ + 0x00000000, /* DENALI_PHY_592_DATA */ + 0x00000000, /* DENALI_PHY_593_DATA */ + 0x00000000, /* DENALI_PHY_594_DATA */ + 0x00000000, /* DENALI_PHY_595_DATA */ + 0x00000000, /* DENALI_PHY_596_DATA */ + 0x00000000, /* DENALI_PHY_597_DATA */ + 0x00000000, /* DENALI_PHY_598_DATA */ + 0x00000000, /* DENALI_PHY_599_DATA */ + 0x00000000, /* DENALI_PHY_600_DATA */ + 0x00000000, /* DENALI_PHY_601_DATA */ + 0x00000000, /* DENALI_PHY_602_DATA */ + 0x00000000, /* DENALI_PHY_603_DATA */ + 0x00000000, /* DENALI_PHY_604_DATA */ + 0x00000000, /* DENALI_PHY_605_DATA */ + 0x00000000, /* DENALI_PHY_606_DATA */ + 0x00000000, /* DENALI_PHY_607_DATA */ + 0x00000000, /* DENALI_PHY_608_DATA */ + 0x00000000, /* DENALI_PHY_609_DATA */ + 0x00000000, /* DENALI_PHY_610_DATA */ + 0x00000000, /* DENALI_PHY_611_DATA */ + 0x00000000, /* DENALI_PHY_612_DATA */ + 0x00000000, /* DENALI_PHY_613_DATA */ + 0x00000000, /* DENALI_PHY_614_DATA */ + 0x00000000, /* DENALI_PHY_615_DATA */ + 0x00000000, /* DENALI_PHY_616_DATA */ + 0x00000000, /* DENALI_PHY_617_DATA */ + 0x00000000, /* DENALI_PHY_618_DATA */ + 0x00000000, /* DENALI_PHY_619_DATA */ + 0x00000000, /* DENALI_PHY_620_DATA */ + 0x00000000, /* DENALI_PHY_621_DATA */ + 0x00000000, /* DENALI_PHY_622_DATA */ + 0x00000000, /* DENALI_PHY_623_DATA */ + 0x00000000, /* DENALI_PHY_624_DATA */ + 0x00000000, /* DENALI_PHY_625_DATA */ + 0x00000000, /* DENALI_PHY_626_DATA */ + 0x00000000, /* DENALI_PHY_627_DATA */ + 0x00000000, /* DENALI_PHY_628_DATA */ + 0x00000000, /* DENALI_PHY_629_DATA */ + 0x00000000, /* DENALI_PHY_630_DATA */ + 0x00000000, /* DENALI_PHY_631_DATA */ + 0x00000000, /* DENALI_PHY_632_DATA */ + 0x00000000, /* DENALI_PHY_633_DATA */ + 0x00000000, /* DENALI_PHY_634_DATA */ + 0x00000000, /* DENALI_PHY_635_DATA */ + 0x00000000, /* DENALI_PHY_636_DATA */ + 0x00000000, /* DENALI_PHY_637_DATA */ + 0x00000000, /* DENALI_PHY_638_DATA */ + 0x00000000, /* DENALI_PHY_639_DATA */ + 0x00000000, /* DENALI_PHY_640_DATA */ + 0x00800000, /* DENALI_PHY_641_DATA */ + 0x00000000, /* DENALI_PHY_642_DATA */ + 0x00000000, /* DENALI_PHY_643_DATA */ + 0x00000000, /* DENALI_PHY_644_DATA */ + 0x00000000, /* DENALI_PHY_645_DATA */ + 0x00000000, /* DENALI_PHY_646_DATA */ + 0x00000001, /* DENALI_PHY_647_DATA */ + 0x00000000, /* DENALI_PHY_648_DATA */ + 0x00000000, /* DENALI_PHY_649_DATA */ + 0x00000000, /* DENALI_PHY_650_DATA */ + 0x00400320, /* DENALI_PHY_651_DATA */ + 0x00000040, /* DENALI_PHY_652_DATA */ + 0x00008eca, /* DENALI_PHY_653_DATA */ + 0x00009fdb, /* DENALI_PHY_654_DATA */ + 0x00008eca, /* DENALI_PHY_655_DATA */ + 0x01009fdb, /* DENALI_PHY_656_DATA */ + 0x00020003, /* DENALI_PHY_657_DATA */ + 0x00000000, /* DENALI_PHY_658_DATA */ + 0x00000000, /* DENALI_PHY_659_DATA */ + 0x00000000, /* DENALI_PHY_660_DATA */ + 0x000556aa, /* DENALI_PHY_661_DATA */ + 0x000aaaaa, /* DENALI_PHY_662_DATA */ + 0x000aa955, /* DENALI_PHY_663_DATA */ + 0x00055555, /* DENALI_PHY_664_DATA */ + 0x000b3133, /* DENALI_PHY_665_DATA */ + 0x0004cd33, /* DENALI_PHY_666_DATA */ + 0x0004cecc, /* DENALI_PHY_667_DATA */ + 0x000b32cc, /* DENALI_PHY_668_DATA */ + 0x0004a0e6, /* DENALI_PHY_669_DATA */ + 0x080f0000, /* DENALI_PHY_670_DATA */ + 0x0000000f, /* DENALI_PHY_671_DATA */ + 0x00038055, /* DENALI_PHY_672_DATA */ + 0x03800380, /* DENALI_PHY_673_DATA */ + 0x03800380, /* DENALI_PHY_674_DATA */ + 0x00000380, /* DENALI_PHY_675_DATA */ + 0x42080010, /* DENALI_PHY_676_DATA */ + 0x00000003, /* DENALI_PHY_677_DATA */ + 0x00000000, /* DENALI_PHY_678_DATA */ + 0x00000000, /* DENALI_PHY_679_DATA */ + 0x00000000, /* DENALI_PHY_680_DATA */ + 0x00000000, /* DENALI_PHY_681_DATA */ + 0x00000000, /* DENALI_PHY_682_DATA */ + 0x00000000, /* DENALI_PHY_683_DATA */ + 0x00000000, /* DENALI_PHY_684_DATA */ + 0x00000000, /* DENALI_PHY_685_DATA */ + 0x00000000, /* DENALI_PHY_686_DATA */ + 0x00000000, /* DENALI_PHY_687_DATA */ + 0x00000000, /* DENALI_PHY_688_DATA */ + 0x00000000, /* DENALI_PHY_689_DATA */ + 0x00000000, /* DENALI_PHY_690_DATA */ + 0x00000000, /* DENALI_PHY_691_DATA */ + 0x00000000, /* DENALI_PHY_692_DATA */ + 0x00000000, /* DENALI_PHY_693_DATA */ + 0x00000000, /* DENALI_PHY_694_DATA */ + 0x00000000, /* DENALI_PHY_695_DATA */ + 0x00000000, /* DENALI_PHY_696_DATA */ + 0x00000000, /* DENALI_PHY_697_DATA */ + 0x00000000, /* DENALI_PHY_698_DATA */ + 0x00000000, /* DENALI_PHY_699_DATA */ + 0x00000000, /* DENALI_PHY_700_DATA */ + 0x00000000, /* DENALI_PHY_701_DATA */ + 0x00000000, /* DENALI_PHY_702_DATA */ + 0x00000000, /* DENALI_PHY_703_DATA */ + 0x00000000, /* DENALI_PHY_704_DATA */ + 0x00000000, /* DENALI_PHY_705_DATA */ + 0x00000000, /* DENALI_PHY_706_DATA */ + 0x00000000, /* DENALI_PHY_707_DATA */ + 0x00000000, /* DENALI_PHY_708_DATA */ + 0x00000000, /* DENALI_PHY_709_DATA */ + 0x00000000, /* DENALI_PHY_710_DATA */ + 0x00000000, /* DENALI_PHY_711_DATA */ + 0x00000000, /* DENALI_PHY_712_DATA */ + 0x00000000, /* DENALI_PHY_713_DATA */ + 0x00000000, /* DENALI_PHY_714_DATA */ + 0x00000000, /* DENALI_PHY_715_DATA */ + 0x00000000, /* DENALI_PHY_716_DATA */ + 0x00000000, /* DENALI_PHY_717_DATA */ + 0x00000000, /* DENALI_PHY_718_DATA */ + 0x00000000, /* DENALI_PHY_719_DATA */ + 0x00000000, /* DENALI_PHY_720_DATA */ + 0x00000000, /* DENALI_PHY_721_DATA */ + 0x00000000, /* DENALI_PHY_722_DATA */ + 0x00000000, /* DENALI_PHY_723_DATA */ + 0x00000000, /* DENALI_PHY_724_DATA */ + 0x00000000, /* DENALI_PHY_725_DATA */ + 0x00000000, /* DENALI_PHY_726_DATA */ + 0x00000000, /* DENALI_PHY_727_DATA */ + 0x00000000, /* DENALI_PHY_728_DATA */ + 0x00000000, /* DENALI_PHY_729_DATA */ + 0x00000000, /* DENALI_PHY_730_DATA */ + 0x00000000, /* DENALI_PHY_731_DATA */ + 0x00000000, /* DENALI_PHY_732_DATA */ + 0x00000000, /* DENALI_PHY_733_DATA */ + 0x00000000, /* DENALI_PHY_734_DATA */ + 0x00000000, /* DENALI_PHY_735_DATA */ + 0x00000000, /* DENALI_PHY_736_DATA */ + 0x00000000, /* DENALI_PHY_737_DATA */ + 0x00000000, /* DENALI_PHY_738_DATA */ + 0x00000000, /* DENALI_PHY_739_DATA */ + 0x00000000, /* DENALI_PHY_740_DATA */ + 0x00000000, /* DENALI_PHY_741_DATA */ + 0x00000000, /* DENALI_PHY_742_DATA */ + 0x00000000, /* DENALI_PHY_743_DATA */ + 0x00000000, /* DENALI_PHY_744_DATA */ + 0x00000000, /* DENALI_PHY_745_DATA */ + 0x00000000, /* DENALI_PHY_746_DATA */ + 0x00000000, /* DENALI_PHY_747_DATA */ + 0x00000000, /* DENALI_PHY_748_DATA */ + 0x00000000, /* DENALI_PHY_749_DATA */ + 0x00000000, /* DENALI_PHY_750_DATA */ + 0x00000000, /* DENALI_PHY_751_DATA */ + 0x00000000, /* DENALI_PHY_752_DATA */ + 0x00000000, /* DENALI_PHY_753_DATA */ + 0x00000000, /* DENALI_PHY_754_DATA */ + 0x00000000, /* DENALI_PHY_755_DATA */ + 0x00000000, /* DENALI_PHY_756_DATA */ + 0x00000000, /* DENALI_PHY_757_DATA */ + 0x00000000, /* DENALI_PHY_758_DATA */ + 0x00000000, /* DENALI_PHY_759_DATA */ + 0x00000000, /* DENALI_PHY_760_DATA */ + 0x00000000, /* DENALI_PHY_761_DATA */ + 0x00000000, /* DENALI_PHY_762_DATA */ + 0x00000000, /* DENALI_PHY_763_DATA */ + 0x00000000, /* DENALI_PHY_764_DATA */ + 0x00000000, /* DENALI_PHY_765_DATA */ + 0x00000000, /* DENALI_PHY_766_DATA */ + 0x00000000, /* DENALI_PHY_767_DATA */ + 0x00000000, /* DENALI_PHY_768_DATA */ + 0x00800000, /* DENALI_PHY_769_DATA */ + 0x00000000, /* DENALI_PHY_770_DATA */ + 0x00000000, /* DENALI_PHY_771_DATA */ + 0x00000000, /* DENALI_PHY_772_DATA */ + 0x00000000, /* DENALI_PHY_773_DATA */ + 0x00000000, /* DENALI_PHY_774_DATA */ + 0x00000001, /* DENALI_PHY_775_DATA */ + 0x00000000, /* DENALI_PHY_776_DATA */ + 0x00000000, /* DENALI_PHY_777_DATA */ + 0x00000000, /* DENALI_PHY_778_DATA */ + 0x00400320, /* DENALI_PHY_779_DATA */ + 0x00000040, /* DENALI_PHY_780_DATA */ + 0x00008eca, /* DENALI_PHY_781_DATA */ + 0x00009fdb, /* DENALI_PHY_782_DATA */ + 0x00008eca, /* DENALI_PHY_783_DATA */ + 0x01009fdb, /* DENALI_PHY_784_DATA */ + 0x00020003, /* DENALI_PHY_785_DATA */ + 0x00000000, /* DENALI_PHY_786_DATA */ + 0x00000000, /* DENALI_PHY_787_DATA */ + 0x00000000, /* DENALI_PHY_788_DATA */ + 0x000556aa, /* DENALI_PHY_789_DATA */ + 0x000aaaaa, /* DENALI_PHY_790_DATA */ + 0x000aa955, /* DENALI_PHY_791_DATA */ + 0x00055555, /* DENALI_PHY_792_DATA */ + 0x000b3133, /* DENALI_PHY_793_DATA */ + 0x0004cd33, /* DENALI_PHY_794_DATA */ + 0x0004cecc, /* DENALI_PHY_795_DATA */ + 0x000b32cc, /* DENALI_PHY_796_DATA */ + 0x1ee6b16a, /* DENALI_PHY_797_DATA */ + 0x10000000, /* DENALI_PHY_798_DATA */ + 0x00000000, /* DENALI_PHY_799_DATA */ + 0x00038055, /* DENALI_PHY_800_DATA */ + 0x03800380, /* DENALI_PHY_801_DATA */ + 0x03800380, /* DENALI_PHY_802_DATA */ + 0x00000380, /* DENALI_PHY_803_DATA */ + 0x42080010, /* DENALI_PHY_804_DATA */ + 0x00000003, /* DENALI_PHY_805_DATA */ + 0x00000000, /* DENALI_PHY_806_DATA */ + 0x00000000, /* DENALI_PHY_807_DATA */ + 0x00000000, /* DENALI_PHY_808_DATA */ + 0x00000000, /* DENALI_PHY_809_DATA */ + 0x00000000, /* DENALI_PHY_810_DATA */ + 0x00000000, /* DENALI_PHY_811_DATA */ + 0x00000000, /* DENALI_PHY_812_DATA */ + 0x00000000, /* DENALI_PHY_813_DATA */ + 0x00000000, /* DENALI_PHY_814_DATA */ + 0x00000000, /* DENALI_PHY_815_DATA */ + 0x00000000, /* DENALI_PHY_816_DATA */ + 0x00000000, /* DENALI_PHY_817_DATA */ + 0x00000000, /* DENALI_PHY_818_DATA */ + 0x00000000, /* DENALI_PHY_819_DATA */ + 0x00000000, /* DENALI_PHY_820_DATA */ + 0x00000000, /* DENALI_PHY_821_DATA */ + 0x00000000, /* DENALI_PHY_822_DATA */ + 0x00000000, /* DENALI_PHY_823_DATA */ + 0x00000000, /* DENALI_PHY_824_DATA */ + 0x00000000, /* DENALI_PHY_825_DATA */ + 0x00000000, /* DENALI_PHY_826_DATA */ + 0x00000000, /* DENALI_PHY_827_DATA */ + 0x00000000, /* DENALI_PHY_828_DATA */ + 0x00000000, /* DENALI_PHY_829_DATA */ + 0x00000000, /* DENALI_PHY_830_DATA */ + 0x00000000, /* DENALI_PHY_831_DATA */ + 0x00000000, /* DENALI_PHY_832_DATA */ + 0x00000000, /* DENALI_PHY_833_DATA */ + 0x00000000, /* DENALI_PHY_834_DATA */ + 0x00000000, /* DENALI_PHY_835_DATA */ + 0x00000000, /* DENALI_PHY_836_DATA */ + 0x00000000, /* DENALI_PHY_837_DATA */ + 0x00000000, /* DENALI_PHY_838_DATA */ + 0x00000000, /* DENALI_PHY_839_DATA */ + 0x00000000, /* DENALI_PHY_840_DATA */ + 0x00000000, /* DENALI_PHY_841_DATA */ + 0x00000000, /* DENALI_PHY_842_DATA */ + 0x00000000, /* DENALI_PHY_843_DATA */ + 0x00000000, /* DENALI_PHY_844_DATA */ + 0x00000000, /* DENALI_PHY_845_DATA */ + 0x00000000, /* DENALI_PHY_846_DATA */ + 0x00000000, /* DENALI_PHY_847_DATA */ + 0x00000000, /* DENALI_PHY_848_DATA */ + 0x00000000, /* DENALI_PHY_849_DATA */ + 0x00000000, /* DENALI_PHY_850_DATA */ + 0x00000000, /* DENALI_PHY_851_DATA */ + 0x00000000, /* DENALI_PHY_852_DATA */ + 0x00000000, /* DENALI_PHY_853_DATA */ + 0x00000000, /* DENALI_PHY_854_DATA */ + 0x00000000, /* DENALI_PHY_855_DATA */ + 0x00000000, /* DENALI_PHY_856_DATA */ + 0x00000000, /* DENALI_PHY_857_DATA */ + 0x00000000, /* DENALI_PHY_858_DATA */ + 0x00000000, /* DENALI_PHY_859_DATA */ + 0x00000000, /* DENALI_PHY_860_DATA */ + 0x00000000, /* DENALI_PHY_861_DATA */ + 0x00000000, /* DENALI_PHY_862_DATA */ + 0x00000000, /* DENALI_PHY_863_DATA */ + 0x00000000, /* DENALI_PHY_864_DATA */ + 0x00000000, /* DENALI_PHY_865_DATA */ + 0x00000000, /* DENALI_PHY_866_DATA */ + 0x00000000, /* DENALI_PHY_867_DATA */ + 0x00000000, /* DENALI_PHY_868_DATA */ + 0x00000000, /* DENALI_PHY_869_DATA */ + 0x00000000, /* DENALI_PHY_870_DATA */ + 0x00000000, /* DENALI_PHY_871_DATA */ + 0x00000000, /* DENALI_PHY_872_DATA */ + 0x00000000, /* DENALI_PHY_873_DATA */ + 0x00000000, /* DENALI_PHY_874_DATA */ + 0x00000000, /* DENALI_PHY_875_DATA */ + 0x00000000, /* DENALI_PHY_876_DATA */ + 0x00000000, /* DENALI_PHY_877_DATA */ + 0x00000000, /* DENALI_PHY_878_DATA */ + 0x00000000, /* DENALI_PHY_879_DATA */ + 0x00000000, /* DENALI_PHY_880_DATA */ + 0x00000000, /* DENALI_PHY_881_DATA */ + 0x00000000, /* DENALI_PHY_882_DATA */ + 0x00000000, /* DENALI_PHY_883_DATA */ + 0x00000000, /* DENALI_PHY_884_DATA */ + 0x00000000, /* DENALI_PHY_885_DATA */ + 0x00000000, /* DENALI_PHY_886_DATA */ + 0x00000000, /* DENALI_PHY_887_DATA */ + 0x00000000, /* DENALI_PHY_888_DATA */ + 0x00000000, /* DENALI_PHY_889_DATA */ + 0x00000000, /* DENALI_PHY_890_DATA */ + 0x00000000, /* DENALI_PHY_891_DATA */ + 0x00000000, /* DENALI_PHY_892_DATA */ + 0x00000000, /* DENALI_PHY_893_DATA */ + 0x00000000, /* DENALI_PHY_894_DATA */ + 0x00000000, /* DENALI_PHY_895_DATA */ + 0x00000001, /* DENALI_PHY_896_DATA */ + 0x00000000, /* DENALI_PHY_897_DATA */ + 0x01000005, /* DENALI_PHY_898_DATA */ + 0x04000f00, /* DENALI_PHY_899_DATA */ + 0x00020040, /* DENALI_PHY_900_DATA */ + 0x00020055, /* DENALI_PHY_901_DATA */ + 0x00000000, /* DENALI_PHY_902_DATA */ + 0x00000000, /* DENALI_PHY_903_DATA */ + 0x00000000, /* DENALI_PHY_904_DATA */ + 0x00000050, /* DENALI_PHY_905_DATA */ + 0x00000000, /* DENALI_PHY_906_DATA */ + 0x00010100, /* DENALI_PHY_907_DATA */ + 0x00000601, /* DENALI_PHY_908_DATA */ + 0x00000000, /* DENALI_PHY_909_DATA */ + 0x00006400, /* DENALI_PHY_910_DATA */ + 0x01221102, /* DENALI_PHY_911_DATA */ + 0x00000000, /* DENALI_PHY_912_DATA */ + 0x00051f00, /* DENALI_PHY_913_DATA */ + 0x051f051f, /* DENALI_PHY_914_DATA */ + 0x051f051f, /* DENALI_PHY_915_DATA */ + 0x00030003, /* DENALI_PHY_916_DATA */ + 0x03000300, /* DENALI_PHY_917_DATA */ + 0x00000300, /* DENALI_PHY_918_DATA */ + 0x01221102, /* DENALI_PHY_919_DATA */ + 0x00000000, /* DENALI_PHY_920_DATA */ + 0x00000000, /* DENALI_PHY_921_DATA */ + 0x04020000, /* DENALI_PHY_922_DATA */ + 0x00000001, /* DENALI_PHY_923_DATA */ + 0x00000011, /* DENALI_PHY_924_DATA */ + 0x00000011, /* DENALI_PHY_925_DATA */ + 0x00000400, /* DENALI_PHY_926_DATA */ + 0x00000000, /* DENALI_PHY_927_DATA */ + 0x00000011, /* DENALI_PHY_928_DATA */ + 0x00000011, /* DENALI_PHY_929_DATA */ + 0x00004410, /* DENALI_PHY_930_DATA */ + 0x00004410, /* DENALI_PHY_931_DATA */ + 0x00004410, /* DENALI_PHY_932_DATA */ + 0x00004410, /* DENALI_PHY_933_DATA */ + 0x00004410, /* DENALI_PHY_934_DATA */ + 0x00000011, /* DENALI_PHY_935_DATA */ + 0x00004410, /* DENALI_PHY_936_DATA */ + 0x00000011, /* DENALI_PHY_937_DATA */ + 0x00004410, /* DENALI_PHY_938_DATA */ + 0x00000011, /* DENALI_PHY_939_DATA */ + 0x00004410, /* DENALI_PHY_940_DATA */ + 0x00000000, /* DENALI_PHY_941_DATA */ + 0x00000000, /* DENALI_PHY_942_DATA */ + 0x00000000, /* DENALI_PHY_943_DATA */ + 0x04000000, /* DENALI_PHY_944_DATA */ + 0x00000000, /* DENALI_PHY_945_DATA */ + 0x00000000, /* DENALI_PHY_946_DATA */ + 0x00000508, /* DENALI_PHY_947_DATA */ + 0x00000000, /* DENALI_PHY_948_DATA */ + 0x00000000, /* DENALI_PHY_949_DATA */ + 0x00000000, /* DENALI_PHY_950_DATA */ + 0x00000000, /* DENALI_PHY_951_DATA */ + 0x00000000, /* DENALI_PHY_952_DATA */ + 0x00000000, /* DENALI_PHY_953_DATA */ + 0xe4000000, /* DENALI_PHY_954_DATA */ + 0x00000000, /* DENALI_PHY_955_DATA */ + 0x00000000, /* DENALI_PHY_956_DATA */ + 0x01010000, /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + } + }, +}, diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index cfe363c..ed9afda 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -556,9 +556,9 @@ void rkclk_configure_ddr(unsigned int hz) dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; break; - case 928*MHz: + case 933*MHz: dpll_cfg = (struct pll_div) - {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; + {.refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}; break; default: die("Unsupported SDRAM frequency, add to clock.c!"); diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9587696..9aa2952 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -992,7 +992,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params) printk(BIOS_INFO, "Starting SDRAM initialization...\n"); if ((dramtype == DDR3 && ddr_freq > 800*MHz) || - (dramtype == LPDDR3 && ddr_freq > 928*MHz) || + (dramtype == LPDDR3 && ddr_freq > 933*MHz) || (dramtype == LPDDR4 && ddr_freq > 800*MHz)) die("SDRAM frequency is to high!");

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Patch set updated for coreboot: soc/marvell/mvmap2315: Add NVM driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16161 -gerrit commit 92bd5e2422b552b2931982fd0b326fe32c7a2961 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:25:43 2016 -0700 soc/marvell/mvmap2315: Add NVM driver This driver uses BootROM callback to read and write to the nvm using I2C. Testing: booted successfully. Change-Id: I8639af3e004f6631d7e596507c106159835f979f Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/include/soc/nvm.h | 25 +++++++ src/soc/marvell/mvmap2315/nvm.c | 105 ++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 0d1ef2b..e16286b 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -27,6 +27,7 @@ bootblock-y += gpio.c bootblock-y += flash.c bootblock-y += load_validate.c bootblock-y += media.c +bootblock-y += nvm.c bootblock-y += pinmux.c bootblock-y += pmic.c bootblock-y += reset.c diff --git a/src/soc/marvell/mvmap2315/include/soc/nvm.h b/src/soc/marvell/mvmap2315/include/soc/nvm.h new file mode 100644 index 0000000..ede0d97 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/nvm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_MARVELL_MVMAP2315_NVM_H__ +#define __SOC_MARVELL_MVMAP2315_NVM_H__ + +#define MVMAP2315_NVM_LOCKDOWN_FLAG BIT(0) + +u32 nvm_init(void); +u32 nvm_read(u32 offset, u32 *buffer, u32 size); +u32 nvm_write(u32 offset, u32 *buffer, u32 size); +void nvm_lockdown(void); + +#endif /* __SOC_MARVELL_MVMAP2315_NVM_H__ */ diff --git a/src/soc/marvell/mvmap2315/nvm.c b/src/soc/marvell/mvmap2315/nvm.c new file mode 100644 index 0000000..7e33e98 --- /dev/null +++ b/src/soc/marvell/mvmap2315/nvm.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/bdb.h> +#include <soc/clock.h> +#include <soc/flash.h> +#include <soc/load_validate.h> +#include <soc/nvm.h> + +struct flash_ops nvm_callbacks = { + .init = (void *)MVMAP2315_FLASH_INIT, + .read = (void *)MVMAP2315_FLASH_READ, + .write = (void *)MVMAP2315_FLASH_WRITE, +}; + +static void set_nvm_parameters(struct flash_params *eeprom_info, u32 offset, + u32 *buffer, u32 size) +{ + eeprom_info->offset = offset; + eeprom_info->buff = (u32)buffer; + eeprom_info->size = size; + eeprom_info->id = 0x0; + eeprom_info->partition = 0x0; +} + +u32 nvm_init(void) +{ + int rc; + + clrbits_le32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, + MVMAP2315_SDMMC_CLK_RSTN); + setbits_le32(&mvmap2315_apmu_clk->apaonclk_sdmmc_clkgenconfig, + MVMAP2315_SDMMC_CLK_RSTN); + + rc = nvm_callbacks.init(MVMAP2315_EEPROM, 0, 0); + + if (rc) + printk(BIOS_DEBUG, "nvm_init failed with rc=%x.\n", rc); + + return rc; +} + +u32 nvm_read(u32 offset, u32 *buffer, u32 size) +{ + struct flash_params eeprom_read_info; + u32 rc; + + set_nvm_parameters(&eeprom_read_info, offset, buffer, size); + + rc = nvm_init(); + + if (rc) + return rc; + + rc = nvm_callbacks.read(MVMAP2315_EEPROM, 0, &eeprom_read_info); + + if (rc) + printk(BIOS_INFO, "nvm_read callback failed, rc=%x\n", rc); + + return rc; +} + +u32 nvm_write(u32 offset, u32 *buffer, u32 size) +{ + struct flash_params eeprom_read_info; + u32 rc; + + set_nvm_parameters(&eeprom_read_info, offset, buffer, size); + + rc = nvm_init(); + + if (rc) + return rc; + + rc = nvm_callbacks.write(MVMAP2315_EEPROM, 0, &eeprom_read_info); + + if (rc) + printk(BIOS_INFO, "nvm_write callback failed, rc=%x\n", rc); + + return rc; +} + +void nvm_lockdown(void) +{ + setbits_le32(&mvmap2315_mcu_secconfig->boot_hw_lockdown_nvm, + MVMAP2315_NVM_LOCKDOWN_FLAG); +}

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add APMU driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15518 -gerrit commit 20e1f6bc7aa2408afd3527b96e906fb92b4b7df1 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:24:35 2016 -0700 soc/marvell/mvmap2315: Add APMU driver APMU is the AP power management unit. It is a separate processor that handles enabling individual power rails. This driver handles sending and receiving commands from/to APMU. Testing: booted successfully. Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/apmu.c | 131 ++++++++ src/soc/marvell/mvmap2315/bootblock.c | 3 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/apmu.h | 368 +++++++++++++++++++++ 5 files changed, 505 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 85c526e..69733bf 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOC_MARVELL_MVMAP2315),y) +bootblock-y += apmu.c bootblock-y += bootblock.c bootblock-y += bdb.c bootblock-y += clock.c diff --git a/src/soc/marvell/mvmap2315/apmu.c b/src/soc/marvell/mvmap2315/apmu.c new file mode 100644 index 0000000..d6cbc7f --- /dev/null +++ b/src/soc/marvell/mvmap2315/apmu.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/apmu.h> +#include <soc/clock.h> + +void apmu_start(void) +{ + u32 reg; + + printk(BIOS_DEBUG, "APMU init...\n"); + + /* TODO: remove in real silicon */ + write32(&mvmap2315_apmu_pwrctl->scratch0, 0x900dc0de); + + /* Dedicate LCM area to the APMU */ + reg = MVMAP2315_LCM_START_BANK | + MVMAP2315_LCM_END_BANK | + MVMAP2315_LCM_DIRACCESS_EN; + write32(&mvmap2315_lcm_regs->lcm_access, reg); + + /* Taking APMU out of reset */ + setbits_le32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig, + MVMAP2315_APMU_CLK_EN); + + setbits_le32(&mvmap2315_apmu_clk->apaonclk_apmucpu_clkgenconfig, + MVMAP2315_APMU_CLK_RSTN); +} + +static int apmu_sending_cmd(u32 cmd) +{ + int success; + u32 timeout = 0; + + printk(BIOS_DEBUG, "sending cmd: %x\n", cmd); + + /* Send a sync command */ + write32(&mvmap2315_apmu_pwrctl->pwrcmdfifo, + cmd | MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ); + + while (!(read32(&mvmap2315_apmu_pwrctl->intstatus) & + (MVMAP2315_APMU_ISTCLR_DONE | + MVMAP2315_APMU_ISTCLR_ERROR)) && + (timeout < MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT)) + timeout++; + + if (timeout >= MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT) { + printk(BIOS_DEBUG, "cmd Timed out\n"); + success = -2; + } + + if (read32(&mvmap2315_apmu_pwrctl->intstatus) & + MVMAP2315_APMU_ISTCLR_DONE) { + printk(BIOS_DEBUG, "Completed cmd: %x\n", + read32(&mvmap2315_apmu_pwrctl->doneirq)); + + setbits_le32(&mvmap2315_apmu_pwrctl->intstatusclear, + MVMAP2315_APMU_ISTCLR_DONE); + success = 0; + + } else if (read32(&mvmap2315_apmu_pwrctl->intstatus) & + MVMAP2315_APMU_ISTCLR_ERROR) { + printk(BIOS_DEBUG, "Error cmd: %x\n", + read32(&mvmap2315_apmu_pwrctl->errorirq)); + + setbits_le32(&mvmap2315_apmu_pwrctl->intstatusclear, + MVMAP2315_APMU_ISTCLR_ERROR); + + success = -1; + } + + return success; +} + +int apmu_set_dev(u32 dev, u32 state) +{ + u32 cmd; + + cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + cmd |= MVMAP2315_APMU_OPCODE_PWRST << MVMAP2315_APMU_OPCODE_SHIFT; + cmd |= state << MVMAP2315_APMU_DEV_STATE_SHIFT; + cmd |= dev << MVMAP2315_APMU_DEV_OBJECT_SHIFT; + + return apmu_sending_cmd(cmd); +} + +int apmu_set_pll(u32 dev, u32 state, u32 freq) +{ + u32 cmd; + + cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + cmd |= MVMAP2315_APMU_OPCODE_PWRST << MVMAP2315_APMU_OPCODE_SHIFT; + cmd |= freq << MVMAP2315_APMU_DEV_FREQ_SHIFT; + cmd |= state << MVMAP2315_APMU_DEV_STATE_SHIFT; + cmd |= dev << MVMAP2315_APMU_DEV_OBJECT_SHIFT; + + return apmu_sending_cmd(cmd); +} + + +int apmu_set_clk(u32 clk, u32 state, u32 div, u32 src) +{ + u32 cmd; + + cmd = MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ; + cmd |= MVMAP2315_APMU_OPCODE_CLKST << MVMAP2315_APMU_OPCODE_SHIFT; + cmd |= state << MVMAP2315_APMU_CLK_STATE_SHIFT; + cmd |= div << MVMAP2315_APMU_CLK_DIV_SHIFT; + cmd |= src << MVMAP2315_APMU_CLK_SOURCE_SHIFT; + cmd |= clk << MVMAP2315_APMU_CLK_OBJECT_SHIFT; + + return apmu_sending_cmd(cmd); +} diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index c02d1e5..8ad2eed 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <timestamp.h> #include <console/uart.h> +#include <soc/apmu.h> #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> @@ -46,6 +47,8 @@ void bootblock_soc_init(void) printk(BIOS_DEBUG, "loading and validating APMU firmware.\n"); load_and_validate(&bdb_info, APMU_FIRMWARE); + apmu_start(); + printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); load_and_validate(&bdb_info, MCU_FIRMWARE); diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index fb3b05f..31f895f 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -34,6 +34,8 @@ #define MVMAP2315_GENTIMER_BASE 0xE0137000 #define MVMAP2315_MPMU_CLK_BASE 0xEF000800 #define MVMAP2315_MCU_SECCONFIG_BASE 0xED600000 +#define MVMAP2315_APMU_PWRCTL_BASE 0xE012C000 +#define MVMAP2315_LCM_REGS_BASE 0xE0130000 #define MVMAP2315_RAM_BASE 0x00000000 #define MVMAP2315_DEVICE_BASE 0x80000000 diff --git a/src/soc/marvell/mvmap2315/include/soc/apmu.h b/src/soc/marvell/mvmap2315/include/soc/apmu.h new file mode 100644 index 0000000..b29b061 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/apmu.h @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_APMU_H__ +#define __SOC_MARVELL_MVMAP2315_APMU_H__ + +#include <soc/addressmap.h> +#include <types.h> + +enum pll_t { + CPU_PLL = 93, + MC_PLL = 94, + MCFLC_PLL = 95, + A2_PLL = 96, + MAIN_PLL = 97, + GPU_PLL0 = 98, + GPU_PLL1 = 99, + MIPI_PLL = 100, + DISPLAY_PLL = 101, + APLL0 = 102, +}; + +enum apll_freq_t { + APLL_NOCHANGE = 0, + APLL_589P824 = 1, + APLL_541P9008 = 2, + APLL_451P584 = 3 +}; + +enum dev_statet_t { + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D3WAKEINT = 11 +}; + +enum dev_t { + APCPU_0 = 0, + APCPU_L2 = 4, + A2 = 5, + MC = 6, + DDRPHY_0 = 7, + DDRPHY_1 = 8, + DDRPHY_2 = 9, + DDRPHY_3 = 10, + MCFLC = 11, + SDMMC = 50, + AES256 = 54, + AP_AXI_HS = 55, + AP_UART0 = 56, + AP_UART1 = 57, + AP_M2M = 65, + AP_APB = 66, + AP_GIC = 67, +}; + +enum clk_t { + M4CLK = 124, +}; + +enum clk_src_t { + SRCSEL_NO_CHANGE = 0, + SRCSEL_CPU_PLL = 1, + SRCSEL_MC_PLL = 2, + SRCSEL_MCFLC_PLL = 3, + SRCSEL_A2_PLL = 4, + SRCSEL_MAIN_PLL = 5, + SRCSEL_GPU_PLL0 = 6, + SRCSEL_GPU_PLL1 = 7, + SRCSEL_MIPI_PLL = 8, + SRCSEL_DISPLAY_PLL = 9, + SRCSEL_APLL0 = 10, + SRCSEL_APLL1 = 11, +}; + +enum clk_state_t { + NOCHANGE = 0, + GATED = 1, + RUNNING = 2 +}; + +#define MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT 0x5000 +#define MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ BIT(27) +#define MVMAP2315_APMU_ISTCLR_DONE BIT(30) +#define MVMAP2315_APMU_ISTCLR_ERROR BIT(31) + +#define MVMAP2315_APMU_OPCODE_CLKST 1 +#define MVMAP2315_APMU_OPCODE_PWRST 2 +#define MVMAP2315_APMU_OPCODE_SHIFT 28 + +#define MVMAP2315_APMU_DEV_FREQ_SHIFT 12 +#define MVMAP2315_APMU_DEV_STATE_SHIFT 8 +#define MVMAP2315_APMU_DEV_OBJECT_SHIFT 0 + +#define MVMAP2315_APMU_CLK_STATE_SHIFT 25 +#define MVMAP2315_APMU_CLK_DIV_SHIFT 12 +#define MVMAP2315_APMU_CLK_SOURCE_SHIFT 8 +#define MVMAP2315_APMU_CLK_OBJECT_SHIFT 0 + +struct mvmap2315_apmu_pwrctl_regs { + u32 pwrcmdfifo; + u32 pwrcmdfifostatus; + u8 _reserved0[0x08]; + u32 intstatusset; + u32 intstatusclear; + u32 intstatus; + u8 _reserved1[0x04]; + u32 doneirq; + u32 errorirq; + u32 scratch0; + u32 scratch1; + u8 _reserved2[0x10]; + u32 pmp_spci_rx_int_status; + u32 pmp_spci_rx_int_set; + u32 pmp_spci_rx_int_clear; + u8 _reserved3[0x04]; + u32 pmp_spci_tx_int_status; + u32 pmp_spci_tx_int_set; + u32 pmp_spci_tx_int_clear; + u8 _reserved4[0xa4]; + u32 global_pwrstate; + u8 _reserved5[0x0c]; + u32 a72core0_pwrstate; + u8 _reserved6[0x0c]; + u32 a72core1_pwrstate; + u8 _reserved7[0x0c]; + u32 a72core2_pwrstate; + u8 _reserved8[0x0c]; + u32 a72core3_pwrstate; + u8 _reserved9[0x0c]; + u32 a72l2_pwrstate; + u8 _reserved10[0x0c]; + u32 a2fab_pwrstate; + u8 _reserved11[0x0c]; + u32 mc_pwrstate; + u8 _reserved12[0x0c]; + u32 mc_phy0_pwrstate; + u8 _reserved13[0x0c]; + u32 mc_phy1_pwrstate; + u8 _reserved14[0x0c]; + u32 mc_phy2_pwrstate; + u8 _reserved15[0x0c]; + u32 mc_phy3_pwrstate; + u8 _reserved16[0x0c]; + u32 mcflc_pwrstate; + u8 _reserved17[0x0c]; + u32 mcflc_phy0_pwrstate; + u8 _reserved18[0x0c]; + u32 mcflc_phy1_pwrstate; + u8 _reserved19[0x0c]; + u32 mcflc_phy2_pwrstate; + u8 _reserved20[0x0c]; + u32 mcflc_phy3_pwrstate; + u8 _reserved21[0x0c]; + u32 gpu3dcore0_pwrstate; + u8 _reserved22[0x0c]; + u32 gpu3dcore1_pwrstate; + u8 _reserved23[0x0c]; + u32 gpu3dcore2_pwrstate; + u8 _reserved24[0x0c]; + u32 gpu3dcore3_pwrstate; + u8 _reserved25[0x0c]; + u32 gpu3dl2_pwrstate; + u8 _reserved26[0x0c]; + u32 smmu_pwrstate; + u8 _reserved27[0x0c]; + u32 vpudec_pwrstate; + u8 _reserved28[0x0c]; + u32 jpeg_pwrstate; + u8 _reserved29[0x0c]; + u32 decoder_pwrstate; + u8 _reserved30[0x0c]; + u32 vpuenc_pwrstate; + u8 _reserved31[0x0c]; + u32 vp8_pwrstate; + u8 _reserved32[0x0c]; + u32 vp9_pwrstate; + u8 _reserved33[0x0c]; + u32 zram_pwrstate; + u8 _reserved34[0x0c]; + u32 gpu2d_pwrstate; + u8 _reserved35[0x0c]; + u32 edisplay_pwrstate; + u8 _reserved36[0x0c]; + u32 edp_phy_pwrstate; + u8 _reserved37[0x0c]; + u32 dsi_phy0_pwrstate; + u8 _reserved38[0x0c]; + u32 dsi_phy1_pwrstate; + u8 _reserved39[0x0c]; + u32 display_pwrstate; + u8 _reserved40[0x0c]; + u32 mci_x40_pwrstate; + u8 _reserved41[0x0c]; + u32 mci_x4_phy0_pwrstate; + u8 _reserved42[0x0c]; + u32 mci_x41_pwrstate; + u8 _reserved43[0x0c]; + u32 mci_x4_phy1_pwrstate; + u8 _reserved44[0x0c]; + u32 mci_x42_pwrstate; + u8 _reserved45[0x0c]; + u32 mci_x4_phy2_pwrstate; + u8 _reserved46[0x0c]; + u32 mci_x2_pwrstate; + u8 _reserved47[0x0c]; + u32 mci_x2_phy_pwrstate; + u8 _reserved48[0x0c]; + u32 mci_x10_pwrstate; + u8 _reserved49[0x0c]; + u32 mci_x1_phy0_pwrstate; + u8 _reserved50[0x0c]; + u32 mci_x11_pwrstate; + u8 _reserved51[0x0c]; + u32 mci_x1_phy1_pwrstate; + u8 _reserved52[0x0c]; + u32 mci_x12_pwrstate; + u8 _reserved53[0x0c]; + u32 mci_x1_phy2_pwrstate; + u8 _reserved54[0x0c]; + u32 mci_x13_pwrstate; + u8 _reserved55[0x0c]; + u32 mci_x1_phy3_pwrstate; + u8 _reserved56[0x2c]; + u32 sdmmc_pwrstate; + u8 _reserved57[0x0c]; + u32 emmc_phy_pwrstate; + u8 _reserved58[0x0c]; + u32 sdio_phy0_pwrstate; + u8 _reserved59[0x0c]; + u32 sdio_phy1_pwrstate; + u8 _reserved60[0x0c]; + u32 aes256_pwrstate; + u8 _reserved61[0x0c]; + u32 ap_axi_pwrstate; + u8 _reserved62[0x1c]; + u32 ap_uart0_pwrstate; + u8 _reserved63[0x0c]; + u32 ap_uart1_pwrstate; + u8 _reserved64[0x0c]; + u32 ap_ssp0_pwrstate; + u8 _reserved65[0x0c]; + u32 ap_ssp1_pwrstate; + u8 _reserved66[0x0c]; + u32 ap_i2c0_pwrstate; + u8 _reserved67[0x0c]; + u32 ap_i2c1_pwrstate; + u8 _reserved68[0x0c]; + u32 ap_i2c2_pwrstate; + u8 _reserved69[0x0c]; + u32 ap_i2c3_pwrstate; + u8 _reserved70[0x0c]; + u32 ap_i2c4_pwrstate; + u8 _reserved71[0x0c]; + u32 ap_lcm_pwrstate; + u8 _reserved72[0x0c]; + u32 ap_m2m_pwrstate; + u8 _reserved73[0x0c]; + u32 ap_apb_pwrstate; + u8 _reserved74[0x0c]; + u32 bcm_r4_pwrstate; + u8 _reserved75[0x0c]; + u32 apmu_m4_pwrstate; + u8 _reserved76[0x0c]; + u32 ap_gic_pwrstate; + u8 _reserved77[0x4c]; + u32 cpu_pll_pwrstate; + u8 _reserved78[0x0c]; + u32 mc_pll_pwrstate; + u8 _reserved79[0x0c]; + u32 mcflc_pll_pwrstate; + u8 _reserved80[0x0c]; + u32 a2_pll_pwrstate; + u8 _reserved81[0x0c]; + u32 main_pll_pwrstate; + u8 _reserved82[0x0c]; + u32 gpu_pll0_pwrstate; + u8 _reserved83[0x0c]; + u32 gpu_pll1_pwrstate; + u8 _reserved84[0x0c]; + u32 mipi_pll_pwrstate; + u8 _reserved85[0x0c]; + u32 display_pll_pwrstate; + u8 _reserved86[0x0c]; + u32 avs_vmain_pwrstate; + u8 _reserved87[0x0c]; + u32 avs_vcpu_pwrstate; + u8 _reserved88[0x0c]; + u32 avs_vgpu_pwrstate; + u8 _reserved89[0x0c]; + u32 ap_tsene_pwrstate; + u8 _reserved90[0x0c]; + u32 rng_pwrstate; + u8 _reserved91[0x3c]; + u32 padgroup29_pwrstate; + u8 _reserved92[0x0c]; + u32 padgroup30_pwrstate; + u8 _reserved93[0x0c]; + u32 padgroup31_pwrstate; + u8 _reserved94[0x0c]; + u32 padgroup32_pwrstate; + u8 _reserved95[0x0c]; + u32 padgroup33_pwrstate; +}; + +check_member(mvmap2315_apmu_pwrctl_regs, padgroup33_pwrstate, 0x750); +static struct mvmap2315_apmu_pwrctl_regs * const mvmap2315_apmu_pwrctl + = (void *)MVMAP2315_APMU_PWRCTL_BASE; + +#define MVMAP2315_LCM_DIRACCESS_EN BIT(0) +#define MVMAP2315_LCM_START_BANK BIT(6) +#define MVMAP2315_LCM_END_BANK (BIT(8) | BIT(10)) +struct mvmap2315_lcm_regs { + u32 lcm_scfg; + u32 lcm_access; + u8 _reserved0[0x08]; + u32 lcm_ctrl_bank_mstr_id_wr0; + u32 lcm_ctrl_bank_mstr_id_wr1; + u32 lcm_ctrl_bank_mstr_id_wr2; + u32 lcm_ctrl_bank_mstr_id_wr3; + u32 lcm_ctrl_bank_mstr_id_wr4; + u32 lcm_ctrl_bank_mstr_id_wr5; + u8 _reserved1[0x28]; + u32 lcm_ctrl_bank_mask_id_wr0; + u32 lcm_ctrl_bank_mask_id_wr1; + u32 lcm_ctrl_bank_mask_id_wr2; + u32 lcm_ctrl_bank_mask_id_wr3; + u32 lcm_ctrl_bank_mask_id_wr4; + u32 lcm_ctrl_bank_mask_id_wr5; + u8 _reserved2[0x28]; + u32 lcm_ctrl_bank_mstr_id_rd0; + u32 lcm_ctrl_bank_mstr_id_rd1; + u32 lcm_ctrl_bank_mstr_id_rd2; + u32 lcm_ctrl_bank_mstr_id_rd3; + u32 lcm_ctrl_bank_mstr_id_rd4; + u32 lcm_ctrl_bank_mstr_id_rd5; + u8 _reserved3[0x28]; + u32 lcm_ctrl_bank_mask_id_rd0; + u32 lcm_ctrl_bank_mask_id_rd1; + u32 lcm_ctrl_bank_mask_id_rd2; + u32 lcm_ctrl_bank_mask_id_rd3; + u32 lcm_ctrl_bank_mask_id_rd4; + u32 lcm_ctrl_bank_mask_id_rd5; +}; + +check_member(mvmap2315_lcm_regs, lcm_ctrl_bank_mask_id_rd5, 0xe4); +static struct mvmap2315_lcm_regs * const mvmap2315_lcm_regs + = (void *)MVMAP2315_LCM_REGS_BASE; + +void apmu_start(void); +int apmu_set_pll(u32 dev, u32 state, u32 freq); +int apmu_set_dev(u32 dev, u32 state); +int apmu_set_clk(u32 clk, u32 state, u32 div, u32 src); + +#endif /* __SOC_MARVELL_MVMAP2315_APMU_H__ */

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add WDT driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15519 -gerrit commit ec91c9095ac57727365d7aaa8788b1fe9a4631d6 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:26:01 2016 -0700 soc/marvell/mvmap2315: Add WDT driver Testing: booted successfully. Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 3 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/wdt.h | 53 ++++++++++++++++ src/soc/marvell/mvmap2315/wdt.c | 74 ++++++++++++++++++++++ 4 files changed, 132 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index e16286b..b1f7751 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -34,6 +34,7 @@ bootblock-y += reset.c bootblock-y += timer.c bootblock-y += sdram.c bootblock-y += uart.c +bootblock-y += wdt.c ramstage-y += cbmem.c ramstage-y += gpio.c @@ -43,6 +44,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-y += sdram.c ramstage-y += uart.c +ramstage-y += wdt.c romstage-y += cbmem.c romstage-y += clock.c @@ -55,6 +57,7 @@ romstage-y += romstage.c romstage-y += sdram.c romstage-y += timer.c romstage-y += uart.c +romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 318bfc0..aefb5b8 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -25,6 +25,8 @@ #define MVMAP2315_GPIOF_BASE 0xE0142000 #define MVMAP2315_GPIOG_BASE 0xE0142100 #define MVMAP2315_GPIOH_BASE 0xE0142200 +#define MVMAP2315_WDT0_BASE 0XE1010000 +#define MVMAP2315_WDT1_BASE 0XE1020000 #define MVMAP2315_A2BUS_BANKED_BASE 0xF0000000 #define MVMAP2315_A2BUS_ALIAS6_BASE 0xF0002000 diff --git a/src/soc/marvell/mvmap2315/include/soc/wdt.h b/src/soc/marvell/mvmap2315/include/soc/wdt.h new file mode 100644 index 0000000..4c08b9c --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/wdt.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_WDT_H__ +#define __SOC_MARVELL_MVMAP2315_WDT_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_R4_WDT 0 +#define MVMAP2315_AP_WDT 1 + +#define MVMAP2315_WDT_CR_RPL_SHIFT 2 +#define MVMAP2315_WDT_CR_RMOD BIT(1) +#define MVMAP2315_WDT_CR_EN BIT(0) +#define MVMAP2315_WDT_TORR_TOP_SHIFT 0 +#define MVMAP2315_WDT_CRR_SHIFT 0 +struct mvmap2315_wdt_regs { + u32 wdt_cr; + u32 wdt_torr; + u32 wdt_ccvr; + u32 wdt_crr; + u32 wdt_stat; + u32 wdt_eoi; + u8 _reserved0[0xcc]; + u32 wdt_comp_params_5; + u32 wdt_comp_params_4; + u32 wdt_comp_params_3; + u32 wdt_comp_params_2; + u32 wdt_comp_params_1; + u32 wdt_comp_version; + u32 wdt_comp_type; +}; + +check_member(mvmap2315_wdt_regs, wdt_comp_type, 0xfc); + + +void enable_sp_watchdog(u32 timer, u32 timeout_value); +void reset_sp_watchdog(u32 timer, u32 timeout_value); + +#endif /* __SOC_MARVELL_MVMAP2315_WDT_H__ */ diff --git a/src/soc/marvell/mvmap2315/wdt.c b/src/soc/marvell/mvmap2315/wdt.c new file mode 100644 index 0000000..8c643b7 --- /dev/null +++ b/src/soc/marvell/mvmap2315/wdt.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/wdt.h> + +struct mvmap2315_wdt_regs *mvmap2315_wdts[] = { + (struct mvmap2315_wdt_regs *)MVMAP2315_WDT0_BASE, + (struct mvmap2315_wdt_regs *)MVMAP2315_WDT1_BASE, +}; + +void enable_sp_watchdog(u32 timer, u32 timeout_value) +{ + u32 reg; + + reg = read32(&mvmap2315_wdts[timer]->wdt_cr); + + /* set watchdog Reset pulse length to the highest value + * (256 Pclk cycles) + */ + reg |= 7 << MVMAP2315_WDT_CR_RPL_SHIFT; + + /* set the watchdog timer to generate a system reset */ + reg &= ~MVMAP2315_WDT_CR_RMOD; + + write32(&mvmap2315_wdts[timer]->wdt_cr, reg); + + /* enable the watchdog timer */ + setbits_le32(&mvmap2315_wdts[timer]->wdt_cr, MVMAP2315_WDT_CR_EN); + + /* set watchdog Timeout Range Register */ + reg = timeout_value << MVMAP2315_WDT_TORR_TOP_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_torr, reg); + + /* reset the timer */ + reg = 0x76 << MVMAP2315_WDT_CRR_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_crr, reg); +} + +void reset_sp_watchdog(u32 timer, u32 timeout_value) +{ + u32 reg; + + /* set watchdog Timeout Range Register */ + reg = timeout_value << MVMAP2315_WDT_TORR_TOP_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_torr, reg); + + if (read32(&mvmap2315_wdts[timer]->wdt_cr) & MVMAP2315_WDT_CR_EN) { + /* reset the timer */ + reg = 0x76 << MVMAP2315_WDT_CRR_SHIFT; + write32(&mvmap2315_wdts[timer]->wdt_crr, reg); + } else { + /* enable the watchdog timer */ + setbits_le32(&mvmap2315_wdts[timer]->wdt_cr, + MVMAP2315_WDT_CR_EN); + } +}

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add PMIC driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16149 -gerrit commit 0dafacfacb4583f433a48390f37a0666578fa7a0 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:24:57 2016 -0700 soc/marvell/mvmap2315: Add PMIC driver Testing: booted successfully. Change-Id: I168206585f403d2259efe424e563982be661df0b Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/bootblock.c | 29 ++- src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/pmic.h | 194 +++++++++++++++++++++ src/soc/marvell/mvmap2315/pmic.c | 125 +++++++++++++ 5 files changed, 349 insertions(+), 2 deletions(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 69733bf..1e0cdac 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -27,6 +27,7 @@ bootblock-y += flash.c bootblock-y += load_validate.c bootblock-y += media.c bootblock-y += pinmux.c +bootblock-y += pmic.c bootblock-y += reset.c bootblock-y += timer.c bootblock-y += sdram.c diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 8ad2eed..4b2fd2100 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <stdlib.h> +#include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> #include <timestamp.h> @@ -25,6 +26,7 @@ #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> +#include <soc/pmic.h> #include <soc/uart.h> void bootblock_soc_early_init(void) @@ -41,6 +43,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { struct bdb_pointer bdb_info; + u32 boot_path; set_bdb_pointers((u8 *)MVMAP2315_BDB_LCM_BASE, &bdb_info); @@ -49,8 +52,30 @@ void bootblock_soc_init(void) apmu_start(); - printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); - load_and_validate(&bdb_info, MCU_FIRMWARE); + if (!(read32((void *)MVMAP2315_LOWPWR_REG) & MVMAP2315_LOWPWR_FLAG)) { + printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); + load_and_validate(&bdb_info, MCU_FIRMWARE); + mcu_start(); + boot_path = get_boot_path(); + } else { + printk(BIOS_DEBUG, "Low power restart. Skip MCU code load.\n"); + boot_path = get_boot_path(); + } + + switch (boot_path) { + case NO_BOOT: + no_boot(); + break; + case CHARGING_SCREEN: + charging_screen(); + break; + case FULL_BOOT: + full_boot(); + break; + } + + printk(BIOS_DEBUG, "Powering up the AP core0.\n"); + ap_start((void *)0xE0010000); /* initializing UART1 to free UART0 to be used by romstage */ uart_num = 1; diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 31f895f..e3ee304 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -36,10 +36,12 @@ #define MVMAP2315_MCU_SECCONFIG_BASE 0xED600000 #define MVMAP2315_APMU_PWRCTL_BASE 0xE012C000 #define MVMAP2315_LCM_REGS_BASE 0xE0130000 +#define MVMAP2315_CPU_BASE 0xF0410000 #define MVMAP2315_RAM_BASE 0x00000000 #define MVMAP2315_DEVICE_BASE 0x80000000 #define MVMAP2315_FLASH_BASE 0xFE000000 #define MVMAP2315_LCM_BASE 0xE0000000 +#define MVMAP2315_LOWPWR_REG 0xE0002000 #endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/pmic.h b/src/soc/marvell/mvmap2315/include/soc/pmic.h new file mode 100644 index 0000000..01a6040 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/pmic.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_PMIC_H__ +#define __SOC_MARVELL_MVMAP2315_PMIC_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_LOWPWR_FLAG BIT(4) + +#define MVMAP2315_APGENCFG_SYSBARDISABLE BIT(1) +#define MVMAP2315_APGENCFG_BROADCASTINNER BIT(2) +#define MVMAP2315_APGENCFG_BROADCASTOUTER BIT(3) +#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINT BIT(4) +#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU BIT(5) +#define MVMAP2315_APCORECFG0_AA64NAA32 BIT(4) +struct mvmap2315_cpu_regs { + u32 fuse00; + u32 fuse01; + u32 fuse02; + u32 fuse03; + u32 fuse04; + u32 fuse05; + u32 fuse06; + u32 fuse07; + u32 fuse10; + u32 fuse11; + u32 fuse12; + u32 fuse13; + u32 fuse14; + u32 fuse15; + u32 fuse16; + u32 fuse17; + u8 _reserved0[0x20]; + u32 fuse20; + u32 fuse21; + u32 fuse22; + u32 fuse23; + u32 fuse24; + u32 fuse25; + u32 fuse26; + u32 fuse27; + u32 fuse30; + u32 fuse31; + u32 fuse32; + u32 fuse33; + u32 fuse34; + u32 fuse35; + u32 fuse36; + u32 fuse37; + u32 fuse40; + u32 fuse41; + u32 fuse42; + u32 fuse43; + u32 fuse44; + u32 fuse45; + u32 fuse46; + u32 fuse47; + u32 fuse50; + u32 fuse51; + u32 fuse52; + u32 fuse53; + u32 fuse54; + u32 fuse55; + u32 fuse56; + u32 fuse57; + u32 fuse60; + u32 fuse61; + u32 fuse62; + u32 fuse63; + u32 fuse64; + u32 fuse65; + u32 fuse66; + u32 fuse67; + u32 fuse70; + u32 fuse71; + u32 fuse72; + u32 fuse73; + u32 fuse74; + u32 fuse75; + u32 fuse76; + u32 fuse77; + u32 fuse80; + u32 fuse81; + u32 fuse82; + u32 fuse83; + u32 fuse84; + u32 fuse85; + u32 fuse86; + u32 fuse87; + u32 fuse90; + u32 fuse91; + u32 fuse92; + u32 fuse93; + u32 fuse94; + u32 fuse95; + u32 fuse96; + u32 fuse97; + u32 fuse100; + u32 fuse101; + u32 fuse102; + u32 fuse103; + u32 fuse104; + u32 fuse105; + u32 fuse106; + u32 fuse107; + u32 fuse110; + u32 fuse111; + u32 fuse112; + u32 fuse113; + u32 fuse114; + u32 fuse115; + u32 fuse116; + u32 fuse117; + u32 fuse120; + u32 fuse121; + u32 fuse122; + u32 fuse123; + u32 fuse124; + u32 fuse125; + u32 fuse126; + u32 fuse127; + u32 fuse130; + u32 fuse131; + u32 fuse132; + u32 fuse133; + u32 fuse134; + u32 fuse135; + u32 fuse136; + u32 fuse137; + u32 fuse140; + u32 fuse141; + u32 fuse142; + u32 fuse143; + u32 fuse144; + u32 fuse145; + u32 fuse146; + u32 fuse147; + u32 fuse150; + u32 fuse151; + u32 fuse152; + u32 fuse153; + u32 fuse154; + u32 fuse155; + u32 fuse156; + u32 fuse157; + u32 apgencfg; + u32 apcorecfg0; + u32 apcorecfg1; + u32 apcorecfg2; + u32 apcorecfg3; + u32 rvbaraddr_low0; + u32 rvbaraddr_low1; + u32 rvbaraddr_low2; + u32 rvbaraddr_low3; + u8 _reserved1[0x10]; + u32 rvbaraddr_high0; + u32 rvbaraddr_high1; + u32 rvbaraddr_high2; + u32 rvbaraddr_high3; + u32 highvecremap; +}; + +check_member(mvmap2315_cpu_regs, highvecremap, 0x264); +static struct mvmap2315_cpu_regs * const mvmap2315_cpu + = (void *)MVMAP2315_CPU_BASE; + +enum boot_options { + NO_BOOT = 0, + CHARGING_SCREEN = 1, + FULL_BOOT = 2 +}; + +void no_boot(void); +void full_boot(void); +void charging_screen(void); +void mcu_start(void); +void ap_start(void *entry); +u32 get_boot_path(void); + +#endif /* __SOC_MARVELL_MVMAP2315_PMIC_H__ */ diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c new file mode 100644 index 0000000..f263804 --- /dev/null +++ b/src/soc/marvell/mvmap2315/pmic.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <soc/apmu.h> +#include <soc/clock.h> +#include <soc/pmic.h> + +static void syspwr_init(void) +{ + int result = 0; + + /* Start the PLLs */ + result |= apmu_set_pll(MAIN_PLL, D0, 2000); + result |= apmu_set_pll(CPU_PLL, D0, 2400); + result |= apmu_set_pll(MC_PLL, D0, 3200); + result |= apmu_set_pll(MCFLC_PLL, D0, 2133); + result |= apmu_set_pll(A2_PLL, D0, 1800); + result |= apmu_set_pll(GPU_PLL0, D0, 2000); + result |= apmu_set_pll(GPU_PLL1, D0, 2400); + result |= apmu_set_pll(MIPI_PLL, D0, 2000); + result |= apmu_set_pll(DISPLAY_PLL, D0, 1800); + + /* Start the peripheral devices */ + result |= apmu_set_dev(SDMMC, D0); + result |= apmu_set_dev(AES256, D0); + result |= apmu_set_dev(AP_AXI_HS, D0); + result |= apmu_set_dev(AP_UART0, D0); + result |= apmu_set_dev(AP_UART1, D0); + result |= apmu_set_dev(AP_M2M, D0); + result |= apmu_set_dev(AP_APB, D0); + result |= apmu_set_dev(AP_GIC, D0); + result |= apmu_set_dev(A2, D0); + result |= apmu_set_dev(MC, D0); + result |= apmu_set_dev(DDRPHY_0, D0); + result |= apmu_set_dev(DDRPHY_1, D0); + result |= apmu_set_dev(DDRPHY_2, D0); + result |= apmu_set_dev(DDRPHY_3, D0); + + if (result) + assert("ERRORS DURING system POWER-on"); +} + +void ap_start(void *entry) +{ + int result = 0; + + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTINNER); + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTOUTER); + clrbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTCACHEMAINT); + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU); + setbits_le32(&mvmap2315_cpu->apgencfg, + MVMAP2315_APGENCFG_SYSBARDISABLE); + + result |= apmu_set_dev(APCPU_L2, D0); + + setbits_le32(&mvmap2315_cpu->apcorecfg0, + MVMAP2315_APCORECFG0_AA64NAA32); + + write32(&mvmap2315_cpu->rvbaraddr_low0, ((uintptr_t)entry) >> 2); + + write32(&mvmap2315_cpu->rvbaraddr_high0, 0); + + result |= apmu_set_dev(APCPU_0, D0); + + if (result) + assert("ERRORS DURING AP POWER-on"); +} + +void no_boot(void) +{ + /*TODO: impelement no_boot */ +} + +void charging_screen(void) +{ + /*TODO: impelement charging_screen */ +} + +void full_boot(void) +{ + printk(BIOS_DEBUG, "Powering up the system.\n"); + syspwr_init(); +} + +void mcu_start(void) +{ + int result = 0; + + result |= apmu_set_pll(APLL0, D0, APLL_589P824); + result |= apmu_set_clk(M4CLK, NOCHANGE, 4, SRCSEL_APLL0); + + if (result) + assert("ERRORS DURING MCU POWER-on"); + + clrbits_le32(&mvmap2315_mpmu_clk->resetmcu, MVMAP2315_MCU_RST_EN); + setbits_le32(&mvmap2315_mpmu_clk->resetmcu, MVMAP2315_MCU_RST_EN); +} + +u32 get_boot_path(void) +{ + return FULL_BOOT; +}

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add MCU driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15529 -gerrit commit 44f0798a1e16878950e11c8dda5317a46fabc0b8 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:26:27 2016 -0700 soc/marvell/mvmap2315: Add MCU driver Testing: booted successfully. Change-Id: I003f6929b00476d46be931773cd35418fe6622a6 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/bootblock.c | 8 ++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 2 + src/soc/marvell/mvmap2315/include/soc/mcu.h | 116 ++++++++++++++++++ src/soc/marvell/mvmap2315/mcu.c | 130 +++++++++++++++++++++ src/soc/marvell/mvmap2315/pmic.c | 9 +- 6 files changed, 265 insertions(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index b1f7751..4b8a53f 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -26,6 +26,7 @@ bootblock-y += gic.c bootblock-y += gpio.c bootblock-y += flash.c bootblock-y += load_validate.c +bootblock-y += mcu.c bootblock-y += media.c bootblock-y += nvm.c bootblock-y += pinmux.c diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 7a8919c..04f2436 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -27,6 +27,7 @@ #include <soc/bdb.h> #include <soc/gic.h> #include <soc/load_validate.h> +#include <soc/mcu.h> #include <soc/pmic.h> #include <soc/uart.h> @@ -60,6 +61,13 @@ void bootblock_soc_init(void) boot_path = get_boot_path(); } else { printk(BIOS_DEBUG, "Low power restart. Skip MCU code load.\n"); + + sned_hash_msg(GET_HASH); + receive_hash_msg_respond(); + + printk(BIOS_DEBUG, + "MCU hash validation not currently implemented\n"); + boot_path = get_boot_path(); } diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index aefb5b8..33541c8 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -27,6 +27,8 @@ #define MVMAP2315_GPIOH_BASE 0xE0142200 #define MVMAP2315_WDT0_BASE 0XE1010000 #define MVMAP2315_WDT1_BASE 0XE1020000 +#define MVMAP2315_SP_IPC_BASE 0xED0C2000 +#define MVMAP2315_MCU_MSG_BUFF_BASE 0xEE03FF8C #define MVMAP2315_A2BUS_BANKED_BASE 0xF0000000 #define MVMAP2315_A2BUS_ALIAS6_BASE 0xF0002000 diff --git a/src/soc/marvell/mvmap2315/include/soc/mcu.h b/src/soc/marvell/mvmap2315/include/soc/mcu.h new file mode 100644 index 0000000..1d4014c --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/mcu.h @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_MCU_H__ +#define __SOC_MARVELL_MVMAP2315_MCU_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_MCU_MSG_OFFSET 0xCE000000 + +enum { + GET_HASH = 0x0, + ABORT_HASH = 0x1, + START_HASH = 0x2, + SYNC_HASH = 0x3, +}; + +enum { + ABORT = 0x0, + FINISHED = 0x1, + BUSY = 0x2 +}; + +enum { + MSG_READY = 1, + MSG_RECEIVED = 8, + MSG_READY_RECEIVED = 9, +}; + +struct sp_hash_request_msg { + u8 protocol_version; + u8 csum; + u16 cmd_id; + u8 cmd_version; + u8 reserved0; + u16 length; + u8 hash_subcmd; + u8 hash_type; + u8 nonce_size; + u8 reserved1; + u32 offset; + u32 size; + u8 nonce_data[64]; +}; + +check_member(sp_hash_request_msg, nonce_data, 0x14); +static struct sp_hash_request_msg * const mvmap2315_mcu_msg_buff + = (void *)MVMAP2315_MCU_MSG_BUFF_BASE; + +struct mcu_hash_msg { + u8 protocol_version; + u8 csum; + u16 result; + u16 length; + u8 status; + u8 type; + u8 digest_size; + u8 reserved0; + u32 offset; + u32 size; + u8 digest_data[64]; +}; + +struct mcu_pwr_status_msg { + u8 protocol_version; + u8 csum; + u16 cmd_id; + u8 cmd_version; + u8 reserved; + u16 length; + u8 status; +}; + +#define MVMAP2315_IPC_IRQSET_MSGSENT BIT(0) +#define MVMAP2315_IPC_IRQCLR_MSGREADY BIT(0) +#define MVMAP2315_IPC_IRQCLR_MSGRECEIVED BIT(3) +#define MVMAP2315_IPC_IRQACK BIT(3) +#define MVMAP2315_MCU_IPC_IRQ BIT(6) +struct mvmap2315_ipc_regs { + u32 isrr; + u32 wdr0; + u32 wdr1; + u32 isrw; + u32 icr; + u32 iir; + u32 rdr0; + u32 rdr1; + u32 maj_mid_rev; + u32 cfg_rev; + u32 dummy; +}; + +check_member(mvmap2315_ipc_regs, dummy, 0x28); +static struct mvmap2315_ipc_regs * const mvmap2315_sp_ipc + = (void *)MVMAP2315_SP_IPC_BASE; + +void mcu_irq(void); +void send_mcu_msg(void *msg, u32 size); +void *receive_mcu_msg(void); +void sned_hash_msg(u8 subcmd); +void *receive_hash_msg_respond(void); + +#endif /* __SOC_MARVELL_MVMAP2315_MCU_H__ */ diff --git a/src/soc/marvell/mvmap2315/mcu.c b/src/soc/marvell/mvmap2315/mcu.c new file mode 100644 index 0000000..c334cda --- /dev/null +++ b/src/soc/marvell/mvmap2315/mcu.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/gic.h> +#include <soc/mcu.h> + +static u8 mvmap2315_calc_checksum(const void *data, u32 size) +{ + u8 csum; + const u8 *bytes = data; + int i; + + for (i = csum = 0; i < size; i++) + csum += bytes[i]; + + return (~csum) && 0xFF; +} + +void mcu_irq(void) +{ + printk(BIOS_DEBUG, "waiting for MCU msg...\n"); + while (!(read32(&mvmap2315_bcm_gicd->ispendr2) & + MVMAP2315_MCU_IPC_IRQ)) + ; +} + +void send_mcu_msg(void *msg, u32 size) +{ + printk(BIOS_DEBUG, "sending msg to MCU...\n"); + write32(&mvmap2315_sp_ipc->wdr0, (u32)msg); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQSET_MSGSENT); +} + +void *receive_mcu_msg(void) +{ + void *msg; + + printk(BIOS_DEBUG, "receiving msg to MCU...\n"); + + write32(&mvmap2315_sp_ipc->dummy, 0xA5A5A5A5); + + switch (read32(&mvmap2315_sp_ipc->iir)) { + case MSG_READY: + msg = (void *)(read32(&mvmap2315_sp_ipc->rdr0) + + MVMAP2315_MCU_MSG_OFFSET); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGREADY); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQACK); + break; + case MSG_RECEIVED: + msg = NULL; + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGRECEIVED); + break; + case MSG_READY_RECEIVED: + msg = (void *)(read32(&mvmap2315_sp_ipc->rdr0) + + MVMAP2315_MCU_MSG_OFFSET); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGREADY); + setbits_le32(&mvmap2315_sp_ipc->icr, + MVMAP2315_IPC_IRQCLR_MSGRECEIVED); + setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQACK); + + break; + default: + msg = NULL; + write32(&mvmap2315_sp_ipc->icr, read32(&mvmap2315_sp_ipc->iir)); + break; + } + + return msg; +} + +void sned_hash_msg(u8 subcmd) +{ + printk(BIOS_DEBUG, "requesting MCU hash...\n"); + + mvmap2315_mcu_msg_buff->protocol_version = 0x3; + mvmap2315_mcu_msg_buff->cmd_id = 0x2A; + mvmap2315_mcu_msg_buff->reserved0 = 0x0; + mvmap2315_mcu_msg_buff->length = 76; + mvmap2315_mcu_msg_buff->csum = 0; + mvmap2315_mcu_msg_buff->hash_subcmd = subcmd; + mvmap2315_mcu_msg_buff->hash_type = 0; + mvmap2315_mcu_msg_buff->nonce_size = 0; + mvmap2315_mcu_msg_buff->reserved1 = 0; + mvmap2315_mcu_msg_buff->offset = 0; + mvmap2315_mcu_msg_buff->size = 32; + mvmap2315_mcu_msg_buff->csum = mvmap2315_calc_checksum( + (void *)mvmap2315_mcu_msg_buff, + sizeof(struct sp_hash_request_msg)); + + send_mcu_msg((void *)mvmap2315_mcu_msg_buff, + sizeof(struct sp_hash_request_msg)); +} + +void *receive_hash_msg_respond(void) +{ + struct mcu_hash_msg *mvmap2315_hash_msg_response; + + printk(BIOS_DEBUG, "waiting for MCU hash response msg...\n"); + + mcu_irq(); + + mvmap2315_hash_msg_response = receive_mcu_msg(); + + mcu_irq(); + + receive_mcu_msg(); + + return mvmap2315_hash_msg_response; +} diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c index f263804..89ea5eb 100644 --- a/src/soc/marvell/mvmap2315/pmic.c +++ b/src/soc/marvell/mvmap2315/pmic.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <soc/apmu.h> #include <soc/clock.h> +#include <soc/mcu.h> #include <soc/pmic.h> static void syspwr_init(void) @@ -121,5 +122,11 @@ void mcu_start(void) u32 get_boot_path(void) { - return FULL_BOOT; + struct mcu_pwr_status_msg *msg; + + mcu_irq(); + + msg = receive_mcu_msg(); + + return msg->status; }

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Add load_validate driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16148 -gerrit commit 6fa4fb530a9fc52881d7b0c0689318f21f88baed Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:24:08 2016 -0700 soc/marvell/mvmap2315: Add load_validate driver Load_validate: it loads and validates images from flash using hash values stored in the BDB. Testing: booted successfully. Change-Id: I0b00e8c60ed76622d03cb232d5c4273b4077aae7 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 3 + src/soc/marvell/mvmap2315/bdb.c | 79 +++++++++++++ src/soc/marvell/mvmap2315/bootblock.c | 12 ++ src/soc/marvell/mvmap2315/digest.c | 64 +++++++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 1 + src/soc/marvell/mvmap2315/include/soc/bdb.h | 110 ++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/digest.h | 35 ++++++ .../marvell/mvmap2315/include/soc/load_validate.h | 66 +++++++++++ src/soc/marvell/mvmap2315/load_validate.c | 123 +++++++++++++++++++++ 9 files changed, 493 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index c97ac01..85c526e 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -16,11 +16,14 @@ ifeq ($(CONFIG_SOC_MARVELL_MVMAP2315),y) bootblock-y += bootblock.c +bootblock-y += bdb.c bootblock-y += clock.c +bootblock-y += digest.c bootblock-y += fiq.S bootblock-y += gic.c bootblock-y += gpio.c bootblock-y += flash.c +bootblock-y += load_validate.c bootblock-y += media.c bootblock-y += pinmux.c bootblock-y += reset.c diff --git a/src/soc/marvell/mvmap2315/bdb.c b/src/soc/marvell/mvmap2315/bdb.c new file mode 100644 index 0000000..6be414c --- /dev/null +++ b/src/soc/marvell/mvmap2315/bdb.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/bdb.h> + +void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in) +{ + bdb_in->bdb_h + = (struct bdb_header *)start_addr; + + bdb_in->bdb_k + = (struct bdb_key *)(start_addr + + (bdb_in->bdb_h->struct_size)); + + bdb_in->bdb_oem_0 + = (u8 *)((u32)(bdb_in->bdb_k) + + (bdb_in->bdb_k->struct_size)); + + bdb_in->sub_k + = (struct bdb_key *)((u32)(bdb_in->bdb_oem_0) + + (bdb_in->bdb_h->oem_area_0_size)); + + bdb_in->bdb_h_s + = (struct bdb_sig *)((u32)(bdb_in->bdb_oem_0) + + (bdb_in->bdb_h->signed_size)); + + bdb_in->bdb_d + = (struct bdb_data *)((u32)(bdb_in->bdb_h_s) + + (bdb_in->bdb_h_s->struct_size)); + + bdb_in->oem_1 + = (u8 *)((u32)(bdb_in->bdb_d) + + (bdb_in->bdb_d->struct_size)); + + bdb_in->bdb_hash + = (struct bdb_hash *)((u32)(bdb_in->oem_1) + + (bdb_in->bdb_d->oem_area_1_size)); + + bdb_in->bdb_s + = (struct bdb_sig *)((u32)(bdb_in->bdb_d) + + (bdb_in->bdb_d->signed_size)); +} + +struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, u32 image_type) +{ + int i; + + if (!bdb_info) { + printk(BIOS_DEBUG, "can't find BDB\n"); + return NULL; + } + + for (i = 0; i < bdb_info->bdb_d->num_hashes; i++) { + if (bdb_info->bdb_hash[i].type == image_type) + return &bdb_info->bdb_hash[i]; + } + + printk(BIOS_DEBUG, "can't find image with type %d in the BDB\n", + image_type); + return NULL; +} diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 5aa9eb5..c02d1e5 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -21,7 +21,9 @@ #include <console/console.h> #include <timestamp.h> #include <console/uart.h> +#include <soc/bdb.h> #include <soc/gic.h> +#include <soc/load_validate.h> #include <soc/uart.h> void bootblock_soc_early_init(void) @@ -37,6 +39,16 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + struct bdb_pointer bdb_info; + + set_bdb_pointers((u8 *)MVMAP2315_BDB_LCM_BASE, &bdb_info); + + printk(BIOS_DEBUG, "loading and validating APMU firmware.\n"); + load_and_validate(&bdb_info, APMU_FIRMWARE); + + printk(BIOS_DEBUG, "loading and validating MCU firmware.\n"); + load_and_validate(&bdb_info, MCU_FIRMWARE); + /* initializing UART1 to free UART0 to be used by romstage */ uart_num = 1; uart_init(uart_num); diff --git a/src/soc/marvell/mvmap2315/digest.c b/src/soc/marvell/mvmap2315/digest.c new file mode 100644 index 0000000..35cd5b1 --- /dev/null +++ b/src/soc/marvell/mvmap2315/digest.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/digest.h> +#include <string.h> + +struct digest_ops digest_callbacks = { + .init = (security_init_F) MVMAP2315_DIGEST_INIT, + .sha_hash = (sha_hash_F) MVMAP2315_DIGEST_SHA_HASH, +}; + +u32 digest_init(void) +{ + int rc; + + rc = digest_callbacks.init(0); + + if (rc) + printk(BIOS_DEBUG, "digest_init failed with rc=%x.\n", rc); + + return rc; +} + +u32 digest_sha_hash(const u8 *msg, u32 msg_len, u8 *digest, u32 digest_len) +{ + int rc; + + rc = digest_callbacks.sha_hash(msg, msg_len, digest, digest_len); + + if (rc) + printk(BIOS_DEBUG, "digest_sha_hash failed with rc=%x.\n", rc); + + return rc; +} + +u32 digest_cmp(const u8 *msg, u8 *digest, u32 digest_len) +{ + int rc; + + rc = memcmp(msg, digest, digest_len); + + if (rc) + printk(BIOS_DEBUG, "image hash doesn't match BDB expected"); + + return rc; +} diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index b78257e..fb3b05f 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -33,6 +33,7 @@ #define MVMAP2315_APMU_CLK_BASE 0xE0125400 #define MVMAP2315_GENTIMER_BASE 0xE0137000 #define MVMAP2315_MPMU_CLK_BASE 0xEF000800 +#define MVMAP2315_MCU_SECCONFIG_BASE 0xED600000 #define MVMAP2315_RAM_BASE 0x00000000 #define MVMAP2315_DEVICE_BASE 0x80000000 diff --git a/src/soc/marvell/mvmap2315/include/soc/bdb.h b/src/soc/marvell/mvmap2315/include/soc/bdb.h new file mode 100644 index 0000000..92f4e8b --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/bdb.h @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_BDB_H__ +#define __SOC_MARVELL_MVMAP2315_BDB_H__ + +#define MVMAP2315_BDB_LCM_BASE 0xE0000000 + +enum { + BDB_RESERVED = 0, + SP_RW_FIRMWARE = 1, + AP_RW_FIRMWARE = 2, + MCU_FIRMWARE = 3, + APMU_FIRMWARE = 4, + KERNEL_IMAGE = 128, + KERNEL_COMMAND_LINE = 129, + SIXTEEN_BIT_VMLINUX_HEADER = 130 +}; + +struct bdb_header { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u64 bdb_load_address; + u32 bdb_size; + u32 signed_size; + u32 oem_area_0_size; + u8 reserved0[8]; +}__attribute__ ((packed)); + +struct bdb_key { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u8 hash_alg; + u8 sig_alg; + u8 reserved0[2]; + u32 key_version; + char description[128]; + u8 key_data[]; +}__attribute__ ((packed)); + +struct bdb_sig { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u8 hash_alg; + u8 sig_alg; + u8 reserved0[2]; + u32 signed_size; + char description[128]; + u8 sig_SOC_MARVELL_MVMAP2315_data[]; +}__attribute__ ((packed)); + +struct bdb_data { + u32 struct_magic; + u8 struct_major_version; + u8 struct_minor_version; + u16 struct_size; + u32 data_version; + u32 oem_area_1_size; + u8 num_hashes; + u8 hash_entry_size; + u8 reserved0[2]; + u32 signed_size; + u8 reserved1[8]; + char description[128]; +}__attribute__ ((packed)); + +struct bdb_hash { + u64 offset; + u32 size; + u8 partition; + u8 type; + u8 reserved0[2]; + u64 load_address; + u8 digest[32]; +}__attribute__ ((packed)); + +struct bdb_pointer { + struct bdb_header *bdb_h; + struct bdb_key *bdb_k; + u8 *bdb_oem_0; + struct bdb_key *sub_k; + struct bdb_sig *bdb_h_s; + struct bdb_data *bdb_d; + u8 *oem_1; + struct bdb_hash *bdb_hash; + struct bdb_sig *bdb_s; +}__attribute__ ((packed)); + +void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in); +struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, u32 image_type); + +#endif /* __SOC_MARVELL_MVMAP2315_BDB_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/digest.h b/src/soc/marvell/mvmap2315/include/soc/digest.h new file mode 100644 index 0000000..961dbd6 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/digest.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_DIGEST_H__ +#define __SOC_MARVELL_MVMAP2315_DIGEST_H__ + +#define MVMAP2315_DIGEST_INIT 0xFFE00040 +#define MVMAP2315_DIGEST_SHA_HASH 0xFFE00044 + +typedef u32 (*security_init_F)(u32 adv_ver); +typedef u32 (*sha_hash_F)(const u8 *msg, u32 msg_len, u8 *digest, + u32 digest_len); + +struct digest_ops { + security_init_F init; + sha_hash_F sha_hash; +}; + +u32 digest_init(void); +u32 digest_sha_hash(const u8 *msg, u32 msg_len, u8 *digest, u32 digest_len); +u32 digest_cmp(const u8 *msg, u8 *digest, u32 digest_len); + +#endif /* __SOC_MARVELL_MVMAP2315_DIGEST_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/load_validate.h b/src/soc/marvell/mvmap2315/include/soc/load_validate.h new file mode 100644 index 0000000..b8912f5 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/load_validate.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ +#define __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ + +#include <soc/addressmap.h> +#include <types.h> + +enum { + PRIMARY_BDB = 0, + ALTERNATE_BDB = 1, + RECOVERY_BDB = 2, +}; + +#define MVMAP2315_BDB_TYPE (BIT(0) | BIT(1)) +struct mvmap2315_bootrom_info { + u32 sp_ro_status; + u32 flash_media; +}; + +struct mvmap2315_mcu_secconfig_regs { + u8 _reserved0[0x04]; + u32 strap_override_sec_cfg; + u32 sec_mcu_cfg_sec_cfg; + u32 lcm_mcu_cfg_sec_cfg0; + u32 lcm_mcu_cfg_sec_cfg1; + u32 lcm_mcu_cfg_sec_cfg2; + u8 _reserved1[0xe8]; + u32 dap_debug_disable; + u32 boot_avs_status; + u32 pwr_clr_in; + u32 pwr_clr_recovery; + u32 pwr_clr_bdb; + u32 pwr_clr_fail_a; + u32 pwr_clr_fail_b; + u32 rst_clr_dev; + u32 rst_clr_wp1; + u32 rst_clr_wp2; + u32 rst_clr_lp; + u32 boot_gpio_out; + u32 boot_gpio_in; + u32 boot_hw_lockdown_nvm; + u32 boot_hw_lockdown_pinmux; + u32 boot_callback_pointer; +}; + +check_member(mvmap2315_mcu_secconfig_regs, boot_callback_pointer, 0x13c); +static struct mvmap2315_mcu_secconfig_regs * const mvmap2315_mcu_secconfig + = (void *)MVMAP2315_MCU_SECCONFIG_BASE; + +void load_and_validate(struct bdb_pointer *bdb_info, u32 image_type); + +#endif /* __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ */ diff --git a/src/soc/marvell/mvmap2315/load_validate.c b/src/soc/marvell/mvmap2315/load_validate.c new file mode 100644 index 0000000..422c57f --- /dev/null +++ b/src/soc/marvell/mvmap2315/load_validate.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/bdb.h> +#include <soc/digest.h> +#include <soc/flash.h> +#include <soc/load_validate.h> +#include <soc/reset.h> + +static void set_flash_parameters(struct flash_params *flash_info, + struct bdb_hash *image_info) +{ + (*flash_info).offset + = (u32)(image_info->offset); + (*flash_info).buff + = (u32)(image_info->load_address); + (*flash_info).size = image_info->size; + (*flash_info).id = 0x0; + (*flash_info).partition = (u32)image_info->partition; +} + +static void image_failure(void) +{ + struct mvmap2315_bootrom_info *bootrom_info + = (void *)read32( + &mvmap2315_mcu_secconfig->boot_callback_pointer); + + printk(BIOS_DEBUG, "Resetting system!!\n"); + + if ((bootrom_info->sp_ro_status & MVMAP2315_BDB_TYPE) + == PRIMARY_BDB) { + write32(&mvmap2315_mcu_secconfig->pwr_clr_fail_a, 1); + + if (read32( + &mvmap2315_mcu_secconfig->pwr_clr_fail_b)) { + printk(BIOS_DEBUG, "primary & ALT BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting to recovery mode...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_recovery, 1); + } else { + printk(BIOS_DEBUG, "primary BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting using AlT BDB...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_bdb, 1); + } + } else if ((bootrom_info->sp_ro_status & MVMAP2315_BDB_TYPE) + == ALTERNATE_BDB) { + write32(&mvmap2315_mcu_secconfig->pwr_clr_fail_b, 1); + + if (read32( + &mvmap2315_mcu_secconfig->pwr_clr_fail_a)) { + printk(BIOS_DEBUG, "primary & ALT BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting to recovery mode...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_recovery, 1); + } else { + printk(BIOS_DEBUG, "AlT BDB boot failed\n"); + printk(BIOS_DEBUG, "Rebooting using primary BDB...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_bdb, 0); + } + } else if ((bootrom_info->sp_ro_status & MVMAP2315_BDB_TYPE) + == RECOVERY_BDB) { + printk(BIOS_DEBUG, "Recovery image has errors!!!\n"); + printk(BIOS_DEBUG, "Re-entering recovery mode...\n"); + write32(&mvmap2315_mcu_secconfig->pwr_clr_recovery, 1); + } + + mvmap2315_reset(); +} + +void load_and_validate(struct bdb_pointer *bdb_info, u32 image_type) +{ + struct bdb_hash *image_info; + struct flash_params flash_info; + struct mvmap2315_bootrom_info *bootrom_info + = (void *)read32( + &mvmap2315_mcu_secconfig->boot_callback_pointer); + u8 image_digest[32]; + + image_info = find_bdb_image(bdb_info, image_type); + + if (!image_info) + image_failure(); + + set_flash_parameters(&flash_info, image_info); + + if (flash_init(bootrom_info->flash_media, MVMAP2315_MMC_CLK_MHZ)) + image_failure(); + + if (flash_partition(bootrom_info->flash_media, &flash_info)) + image_failure(); + + if (flash_read(bootrom_info->flash_media, &flash_info)) + image_failure(); + + if (flash_shutdown(bootrom_info->flash_media)) + image_failure(); + + if (digest_init()) + image_failure(); + + if (digest_sha_hash(((u8 *)(flash_info.buff)), image_info->size, + &image_digest[0], 32)) + image_failure(); + + if (digest_cmp(&image_digest[0], &image_info->digest[0], 32)) + image_failure(); +}

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Patch set updated for coreboot: soc/marvell/mvmap2315: Add A2BUS driver
by hakim giydan 17 Aug '16

17 Aug '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15523 -gerrit commit b2857f562f80da3ff27ddaffcdd602776ca27f68 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Aug 17 14:25:27 2016 -0700 soc/marvell/mvmap2315: Add A2BUS driver A2BUS is a custom fabric. Testing: booted successfully. Change-Id: If6e61f5aa30217eb601ac460d9306166b8433569 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/a2bus.c | 349 +++++++++++++++++++++ src/soc/marvell/mvmap2315/bootblock.c | 4 + src/soc/marvell/mvmap2315/include/soc/a2bus.h | 314 ++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 6 + 5 files changed, 674 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 1e0cdac..0d1ef2b 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOC_MARVELL_MVMAP2315),y) +bootblock-y += a2bus.c bootblock-y += apmu.c bootblock-y += bootblock.c bootblock-y += bdb.c diff --git a/src/soc/marvell/mvmap2315/a2bus.c b/src/soc/marvell/mvmap2315/a2bus.c new file mode 100644 index 0000000..5d205cf --- /dev/null +++ b/src/soc/marvell/mvmap2315/a2bus.c @@ -0,0 +1,349 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> + +#include <arch/io.h> +#include <console/console.h> +#include <soc/a2bus.h> + +const u32 NUM_SIO = 11; +const u32 SIO_UIDS[] = {15, 14, 13, 12, 10, 8, 7, 5, 3, 1, 0}; +const u32 SP_UID = 4; + +static void a2bus_enable_and_check(void) +{ + u32 reg; + u32 checkval; + + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + /* FIXME - remove once default fixed */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0); + reg |= MVMAP2315_CCU_RGF_WIN0_AHR << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win0, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win0, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN0_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN0_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN0_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0) == checkval) + printk(BIOS_DEBUG, " win0 checks\n"); + else + printk(BIOS_DEBUG, " win0 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win1); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win1, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN1_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN1_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN1_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win1) == checkval) + printk(BIOS_DEBUG, " win1 checks\n"); + else + printk(BIOS_DEBUG, " win1 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win1), checkval); + + /* FIXME - remove once default fixed */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2); + reg |= MVMAP2315_CCU_RGF_WIN2_UID << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win2, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win2, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN2_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN2_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN2_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2) == checkval) + printk(BIOS_DEBUG, " win2 checks\n"); + else + printk(BIOS_DEBUG, " win2 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win3); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win3, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN3_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN3_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN3_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win3) == checkval) + printk(BIOS_DEBUG, " win3 checks\n"); + else + printk(BIOS_DEBUG, " win3 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win3), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win4); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win4, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN4_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN4_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN4_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win4) == checkval) + printk(BIOS_DEBUG, " win4 checks\n"); + else + printk(BIOS_DEBUG, " win4 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win4), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win5); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win5, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN5_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN5_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN5_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win5) == checkval) + printk(BIOS_DEBUG, " win5 checks\n"); + else + printk(BIOS_DEBUG, " win5 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win5), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win6); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win6, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN6_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN6_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN6_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win6) == checkval) + printk(BIOS_DEBUG, " win6 checks\n"); + else + printk(BIOS_DEBUG, " win6 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win6), checkval); + + /* FIXME - remove once default fixed */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7); + reg |= MVMAP2315_CCU_RGF_WIN7_UID << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win7, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win7, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN7_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN7_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN7_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7) == checkval) + printk(BIOS_DEBUG, " win7 checks\n"); + else + printk(BIOS_DEBUG, " win7 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7), checkval); + + printk(BIOS_DEBUG, "Exiting %s\n", __func__); +} + +static void a2bus_open_map(void) +{ + u32 reg; + + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + /* send traffic by defaul to AON (smc0) */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_win_gcr); + reg &= ~MVMAP2315_CCU_WIN_CR_WINTARGET_MASK; + reg |= 2 << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win_gcr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN_GCR\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_alr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRLOW_MASK; + reg |= MVMAP2315_CCU_WIN1_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win1_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_ahr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRHIGH_MASK; + reg |= MVMAP2315_CCU_WIN1_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win1_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_cr); + reg &= ~MVMAP2315_CCU_WIN_CR_WINTARGET_MASK; + reg |= MVMAP2315_CCU_WIN1_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win1_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_cr); + reg |= MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win1_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN1\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_alr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRLOW_MASK; + reg |= MVMAP2315_CCU_WIN2_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win2_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_ahr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRHIGH_MASK; + reg |= MVMAP2315_CCU_WIN2_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win2_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_cr); + reg &= ~MVMAP2315_CCU_WIN_CR_WINTARGET_MASK; + reg |= MVMAP2315_CCU_WIN2_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win2_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_cr); + reg &= ~MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win2_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN2\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_alr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRLOW_MASK; + reg |= MVMAP2315_CCU_WIN3_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win3_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_ahr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRHIGH_MASK; + reg |= MVMAP2315_CCU_WIN3_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win3_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_cr); + reg &= ~MVMAP2315_CCU_WIN_CR_WINTARGET_MASK; + reg |= MVMAP2315_CCU_WIN3_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win3_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_cr); + reg |= MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win3_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN3\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_alr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRLOW_MASK; + reg |= MVMAP2315_CCU_WIN4_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win4_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_ahr); + reg &= ~MVMAP2315_CCU_WIN_ALR_ADDRHIGH_MASK; + reg |= MVMAP2315_CCU_WIN4_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win4_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_cr); + reg &= ~MVMAP2315_CCU_WIN_CR_WINTARGET_MASK; + reg |= MVMAP2315_CCU_WIN4_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win4_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_cr); + reg |= MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win4_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN4\n"); + + /* open all register space */ + a2bus_enable_and_check(); + + printk(BIOS_DEBUG, "Exiting %s\n", __func__); +} + +void init_a2bus_config(void) +{ + u32 reg; + int i; + + /* Open up the A2 address map */ + a2bus_open_map(); + + /* set the bit to enable long non-modifiable */ + for (i = 0; i < NUM_SIO; i++) { + printk(BIOS_DEBUG, "Writing LTC_ForceModifiable to SIO %d\n", + SIO_UIDS[i]); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_idacr); + reg |= SIO_UIDS[i] << MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT; + write32(&mvmap2315_a2bus_banked->ccu_b_idacr, reg); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr); + reg |= MVMAP2315_CCU_B_LTC_CR_USERDMODROB; + write32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr, reg); + } + + printk(BIOS_DEBUG, "Writing LTC_ForceModifiable to SP\n"); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_idacr); + reg |= SP_UID << MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT; + write32(&mvmap2315_a2bus_banked->ccu_b_idacr, reg); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr); + reg |= MVMAP2315_CCU_B_LTC_CR_USERDMODROB; + write32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr, reg); + + printk(BIOS_DEBUG, "FIXME - DISABLING MVN\n"); + + reg = read32(&mvmap2315_a2bus_alias6->ccu_b_smc_mvn); + reg &= ~MVMAP2315_CCU_B_SMC_MVN_MVNENABLE; + write32(&mvmap2315_a2bus_alias6->ccu_b_smc_mvn, reg); + + reg = read32(&mvmap2315_a2bus_alias9->ccu_b_smc_mvn); + reg &= ~MVMAP2315_CCU_B_SMC_MVN_MVNENABLE; + write32(&mvmap2315_a2bus_alias9->ccu_b_smc_mvn, reg); + + reg = read32(&mvmap2315_a2bus_alias11->ccu_b_smc_mvn); + reg &= ~MVMAP2315_CCU_B_SMC_MVN_MVNENABLE; + write32(&mvmap2315_a2bus_alias11->ccu_b_smc_mvn, reg); +} diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 4b2fd2100..7a8919c 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <timestamp.h> #include <console/uart.h> +#include <soc/a2bus.h> #include <soc/apmu.h> #include <soc/bdb.h> #include <soc/gic.h> @@ -74,6 +75,9 @@ void bootblock_soc_init(void) break; } + printk(BIOS_DEBUG, "initializing the A2 bus.\n"); + init_a2bus_config(); + printk(BIOS_DEBUG, "Powering up the AP core0.\n"); ap_start((void *)0xE0010000); diff --git a/src/soc/marvell/mvmap2315/include/soc/a2bus.h b/src/soc/marvell/mvmap2315/include/soc/a2bus.h new file mode 100644 index 0000000..d5fe777 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/a2bus.h @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_A2BUS_H__ +#define __SOC_MARVELL_MVMAP2315_A2BUS_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MVMAP2315_CCU_WIN1_ALR 0x00000000 +#define MVMAP2315_CCU_WIN1_AHR 0x000007FF +#define MVMAP2315_CCU_WIN1_UID 0x0000000B + +#define MVMAP2315_CCU_WIN2_ALR 0x00000000 +#define MVMAP2315_CCU_WIN2_AHR 0x000007FF +#define MVMAP2315_CCU_WIN2_UID 0x00000020 + +#define MVMAP2315_CCU_WIN3_ALR 0x00000800 +#define MVMAP2315_CCU_WIN3_AHR 0x00000EFF +#define MVMAP2315_CCU_WIN3_UID 0x00000002 + +#define MVMAP2315_CCU_WIN4_ALR 0x00008000 +#define MVMAP2315_CCU_WIN4_AHR 0x0000BFFF +#define MVMAP2315_CCU_WIN4_UID 0x0000000B + +#define MVMAP2315_CCU_RGF_WIN0_ALR 0x00000010 +#define MVMAP2315_CCU_RGF_WIN0_AHR 0x000001FF +#define MVMAP2315_CCU_RGF_WIN0_UID 0x00000006 + +#define MVMAP2315_CCU_RGF_WIN1_ALR 0x00000200 +#define MVMAP2315_CCU_RGF_WIN1_AHR 0x000004ff +#define MVMAP2315_CCU_RGF_WIN1_UID 0x00000003 + +#define MVMAP2315_CCU_RGF_WIN2_ALR 0x00000500 +#define MVMAP2315_CCU_RGF_WIN2_AHR 0x0000060F +#define MVMAP2315_CCU_RGF_WIN2_UID 0x0000000C + +#define MVMAP2315_CCU_RGF_WIN3_ALR 0x00000680 +#define MVMAP2315_CCU_RGF_WIN3_AHR 0x0000068F +#define MVMAP2315_CCU_RGF_WIN3_UID 0x00000001 + +#define MVMAP2315_CCU_RGF_WIN4_ALR 0x00000700 +#define MVMAP2315_CCU_RGF_WIN4_AHR 0x0000073F +#define MVMAP2315_CCU_RGF_WIN4_UID 0x00000000 + +#define MVMAP2315_CCU_RGF_WIN5_ALR 0x00000800 +#define MVMAP2315_CCU_RGF_WIN5_AHR 0x000008FF +#define MVMAP2315_CCU_RGF_WIN5_UID 0x00000005 + +#define MVMAP2315_CCU_RGF_WIN6_ALR 0x00000A00 +#define MVMAP2315_CCU_RGF_WIN6_AHR 0x00000FFF +#define MVMAP2315_CCU_RGF_WIN6_UID 0x0000000F + +#define MVMAP2315_CCU_RGF_WIN7_ALR 0x00001000 +#define MVMAP2315_CCU_RGF_WIN7_AHR 0x000017FF +#define MVMAP2315_CCU_RGF_WIN7_UID 0x0000000D + +#define MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT 4 +#define MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT 4 +#define MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT 8 +#define MVMAP2315_CCU_CR_WINEN BIT(0) +#define MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT 19 +#define MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT 6 +#define MVMAP2315_CCU_RGF_WIN_UID_SHIFT 2 +#define MVMAP2315_CCU_RGF_WIN_RGFWINEN BIT(0) +#define MVMAP2315_CCU_WIN_CR_WINTARGET_MASK 0x7f00 +#define MVMAP2315_CCU_WIN_ALR_ADDRLOW_MASK 0xfffff0 +#define MVMAP2315_CCU_WIN_ALR_ADDRHIGH_MASK 0xfffff0 +struct mvmap2315_a2bus_ccu_regs { + u32 ccu_win0_cr; + u32 ccu_win0_scr; + u32 ccu_win0_alr; + u32 ccu_win0_ahr; + u32 ccu_win1_cr; + u32 ccu_win1_scr; + u32 ccu_win1_alr; + u32 ccu_win1_ahr; + u32 ccu_win2_cr; + u32 ccu_win2_scr; + u32 ccu_win2_alr; + u32 ccu_win2_ahr; + u32 ccu_win3_cr; + u32 ccu_win3_scr; + u32 ccu_win3_alr; + u32 ccu_win3_ahr; + u32 ccu_win4_cr; + u32 ccu_win4_scr; + u32 ccu_win4_alr; + u32 ccu_win4_ahr; + u32 ccu_win5_cr; + u32 ccu_win5_scr; + u32 ccu_win5_alr; + u32 ccu_win5_ahr; + u32 ccu_win6_cr; + u32 ccu_win6_scr; + u32 ccu_win6_alr; + u32 ccu_win6_ahr; + u32 ccu_win7_cr; + u32 ccu_win7_scr; + u32 ccu_win7_alr; + u32 ccu_win7_ahr; + u8 _reserved0[0x10]; + u32 ccu_rgf_win0; + u32 ccu_rgf_win1; + u32 ccu_rgf_win2; + u32 ccu_rgf_win3; + u32 ccu_rgf_win4; + u32 ccu_rgf_win5; + u32 ccu_rgf_win6; + u32 ccu_rgf_win7; + u32 ccu_rgf_win8; + u32 ccu_rgf_win9; + u32 ccu_rgf_win10; + u32 ccu_rgf_win11; + u32 ccu_rgf_win12; + u32 ccu_rgf_win13; + u32 ccu_rgf_win14; + u32 ccu_rgf_win15; + u32 ccu_win_gcr; + u32 ccu_rgf_sidr0; + u32 ccu_rgf_sidr1; + u8 _reserved1[0x04]; + u32 ccu_rar0; + u32 ccu_rar1; + u8 _reserved2[0x18]; + u32 ccu_sl_hmr; + u32 ccu_sl_mimr0; + u32 ccu_sl_mimr1; + u32 ccu_sl_revid; + u32 ccu_sl_dtpr0; + u32 ccu_sl_dtpr1; + u32 ccu_sl_dtpr2; + u32 ccu_sl_dtpr3; + u32 ccu_sl_dtpr4; + u32 ccu_sl_dtpr5; + u32 ccu_sl_dtpr6; + u32 ccu_sl_dtpr7; + u32 ccu_sl_dtpr8; + u32 ccu_sl_dtpr9; + u32 ccu_sl_dtpr10; + u32 ccu_sl_dtpr11; + u32 ccu_sl_dtpr12; + u32 ccu_sl_dtpr13; + u32 ccu_sl_dtpr14; + u32 ccu_sl_dtpr15; + u8 _reserved3[0xb0]; + u32 ccu_htc_cr; + u32 ccu_htc_sr; + u32 ccu_htc_mnt_cr; + u8 _reserved4[0x04]; + u32 ccu_htc_acr0; + u32 ccu_htc_acr1; + u32 ccu_htc_acr2; + u32 ccu_htc_acr3; + u32 ccu_htc_acr4; + u32 ccu_htc_acr5; + u32 ccu_htc_acr6; + u32 ccu_htc_acr7; + u32 ccu_htc_acr8; + u32 ccu_htc_acr9; + u32 ccu_htc_acr10; + u32 ccu_htc_acr11; + u32 ccu_htc_acr12; + u32 ccu_htc_acr13; + u32 ccu_htc_acr14; + u32 ccu_htc_acr15; + u8 _reserved5[0x10]; + u32 ccu_htc_aasr; + u32 ccu_htc_aset; + u32 ccu_htc_aclr; + u32 ccu_sft_eir0; + u32 ccu_sft_eir1; + u8 _reserved6[0x8c]; + u32 ccu_ltc_cr; + u32 ccu_ltc_sr; + u32 ccu_ltc_hhr; + u32 ccu_ltc_cr1; + u8 _reserved7[0xe0]; + u32 ccu_gspmu_cr; + u32 ccu_gspmu_sr; + u8 _reserved8[0x18]; + u32 ccu_mc_cr; + u8 _reserved9[0x3ec]; + u32 ccu_rgf_cr; + u32 ccu_rgf_scr; +}; + +check_member(mvmap2315_a2bus_ccu_regs, ccu_rgf_scr, 0x804); +static struct mvmap2315_a2bus_ccu_regs * const mvmap2315_a2bus_ccu + = (void *)MVMAP2315_A2BUS_CCU_BASE; + +#define MVMAP2315_CCU_B_LTC_CR_USERDMODROB BIT(0) +#define MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT 0 +#define MVMAP2315_CCU_B_SMC_MVN_MVNENABLE BIT(0) +struct mvmap2315_a2bus_regs { + u32 ccu_b_uid; + u32 ccu_b_urd; + u32 ccu_b_sfwd; + u8 _reserved0[0x04]; + u32 ccu_b_rapc; + u32 ccu_b_dlapc; + u8 _reserved1[0x08]; + u32 ccu_b_rsc; + u32 ccu_b_rsu; + u8 _reserved2[0x08]; + u32 ccu_b_idacr; + u8 _reserved3[0x0c]; + u32 ccu_b_rsrv0; + u8 _reserved4[0x0c]; + u32 ccu_dbg_ltc_cr; + u32 ccu_dbg_ltc_sr; + u8 _reserved5[0x08]; + u32 ccu_dbg_htc_cr; + u32 ccu_dbg_htc_sr; + u8 _reserved6[0x08]; + u32 ccu_dbg_rsu_cr; + u32 ccu_dbg_rsu_sr; + u8 _reserved7[0x08]; + u32 ccu_dbg_smc_cr; + u32 ccu_dbg_smc_sr; + u8 _reserved8[0x98]; + u32 ccu_b_reicr; + u32 ccu_b_reimr; + u32 ccu_b_seicr; + u32 ccu_b_seimr; + u8 _reserved9[0xd0]; + u32 ccu_b_mpccr; + u32 ccu_b_pcr; + u32 ccu_b_drar; + u32 ccu_b_mpidr; + u32 ccu_b_pdcr; + u32 ccu_b_evar; + u32 ccu_b_l2efr; + u8 _reserved10[0x04]; + u32 ccu_b_psr; + u32 ccu_b_mpsr; + u32 ccu_b_adb_cr; + u32 ccu_b_adb_sr; + u32 ccu_b_pdr_sr; + u32 ccu_b_pdr_cr; + u32 ccu_b_l2dr_sr; + u32 ccu_b_l2dr_cr; + u32 ccu_b_rvbar0; + u32 ccu_b_rvbar1; + u32 ccu_b_rvbar2; + u32 ccu_b_rvbar3; + u32 ccu_b_prcr0; + u32 ccu_b_prcr1; + u32 ccu_b_prcr2; + u32 ccu_b_prcr3; + u32 ccu_b_wrcr0; + u32 ccu_b_wrcr1; + u32 ccu_b_wrcr2; + u32 ccu_b_wrcr3; + u32 ccu_b_drcr0; + u32 ccu_b_drcr1; + u32 ccu_b_drcr2; + u32 ccu_b_drcr3; + u32 ccu_b_crcr; + u32 ccu_b_rcr; + u8 _reserved11[0x78]; + u32 ccu_mc_rcr; + u32 ccu_mc_rsbr; + u32 ccu_mc_rtbr; + u32 ccu_b_smc; + u32 ccu_b_smc_mvn; + u8 _reserved12[0x2c]; + u32 ccu_b_ltc_sr; + u32 ccu_b_ltc_cr; + u32 ccu_b_ltc_qos_ovrd; + u32 qos_time_seg_cr; + u32 qos_bw_guarantee_th; + u32 qos_bw_peak_th; + u32 qos_bw_jam_th; + u32 qos_regulator_out_trans_block_cr0; + u32 qos_prio_cr; + u32 qos_critical_path_cr; + u32 qos_regulator_out_trans_block_cr1; + u32 ccu_b_ltc_tc_ovrd; + u8 _reserved13[0x30]; + u32 ccu_b_htc_sr; + u32 ccu_b_htc_prio_dl; + u32 ccu_b_sp_prio_mesh_lo; + u32 ccu_b_sp_prio_mesh_hi; + u32 ccu_b_sft_far_lo; + u32 ccu_b_sft_far_hi; + u32 ccu_b_htc_mnt_sr; +}; + +check_member(mvmap2315_a2bus_regs, ccu_b_htc_mnt_sr, 0x3b8); +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_banked + = (void *)MVMAP2315_A2BUS_BANKED_BASE; +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias6 + = (void *)MVMAP2315_A2BUS_ALIAS6_BASE; +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias9 + = (void *)MVMAP2315_A2BUS_ALIAS9_BASE; +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias11 + = (void *)MVMAP2315_A2BUS_ALIAS11_BASE; + +void init_a2bus_config(void); + +#endif /* __SOC_MARVELL_MVMAP2315_A2BUS_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index e3ee304..318bfc0 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -26,6 +26,12 @@ #define MVMAP2315_GPIOG_BASE 0xE0142100 #define MVMAP2315_GPIOH_BASE 0xE0142200 +#define MVMAP2315_A2BUS_BANKED_BASE 0xF0000000 +#define MVMAP2315_A2BUS_ALIAS6_BASE 0xF0002000 +#define MVMAP2315_A2BUS_ALIAS9_BASE 0xF0002C00 +#define MVMAP2315_A2BUS_ALIAS11_BASE 0xF0003400 +#define MVMAP2315_A2BUS_CCU_BASE 0xF0004000 + #define MVMAP2315_BCM_GICD_BASE 0xE0111000 #define MVMAP2315_BCM_GICC_BASE 0xE0112000

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Patch merged into coreboot/master: google/gru: Add new PWM regulator duty numbers for revision 6
by gerrit＠coreboot.org 17 Aug '16

17 Aug '16

the following patch was just integrated into master: commit 91f6e679ccce9cf90c98608fc2c24aef44db5bf0 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 11 16:37:57 2016 -0700 google/gru: Add new PWM regulator duty numbers for revision 6 We're changing the PWM regulator bounds on Kevin from rev6 onwards, so we'll need to use different duty cycle values for them. We really want a proper PWM regulator driver that can calculate these values automatically from voltages, but until we have that this patch just hardcodes the new numbers in. (Yes, this is a patch for the mainboard/google/gru board family that only touches a file from the rockchip/rk3399 SoC. That too is something that'll be fixed up in a later CL.) BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted Kevin rev4 (for whatever that's worth...). Change-Id: Ibb6ab5c6517d83ffb5e32cb17d0de33e8ec10293 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4cb2a939295e2b6443c5dbd3374982224322304b Original-Change-Id: I8757cc54f2478d20bb948a1a0a7398b0404a7b1f Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/368410 Original-Commit-Ready: Dan Shi <dshi(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-on: https://review.coreboot.org/16235 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/16235 for details. -gerrit

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coreboot-gerrit August 2016