the following patch was just integrated into master:
commit 504b8f2da211735e60b861106bf665a62091c36d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Aug 11 11:10:42 2016 -0500
lib/cbfs_spi: provide boot_device_rw() support
Provide the RW boot device operations for the common cbfs
SPI wrapper. The RW region_device is the same as the read-only
one. As noted in the boot_device_rw() introduction patch the
mmap() support should not be used in conjuction with writing
as that results in incoherent operations. That's fine as the
current mmap() support is only used in the cbfs layer which
does not support writing, i.e. no cbfs regions would be
written to with any previous or outstanding mmap() calls.
BUG=chrome-os-partner:56151
Change-Id: I7cc7309a68ad23b30208ac961b1999a79626b307
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16199
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/16199 for details.
-gerrit
the following patch was just integrated into master:
commit dcbccd6a1ef1ee70d6e96f01c55c8ed270f37716
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Aug 10 11:42:42 2016 -0500
lib/boot_device: add RW boot device construct
The current boot device usage assumes read-only semantics to
the boot device. Any time someone wants to write to the
boot device a device-specific API is invoked such as SPI flash.
Instead, provide a mechanism to retrieve an object that can
be used to perform writes to the boot device. On systems where
the implementations are symmetric these devices can be treated
one-in-the-same. However, for x86 systems with memory mapped SPI
the read-only boot device provides different operations.
BUG=chrome-os-partner:55932
Change-Id: I0af324824f9e1a8e897c2453c36e865b59c4e004
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16194
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16194 for details.
-gerrit
the following patch was just integrated into master:
commit e8e118dd324e32070a1550e3f8ff90dd6fad72f8
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Aug 12 15:00:10 2016 -0500
Kconfig: introduce writable boot device notion
Indicate to the build system that a platform provides support
for a writable boot device. The following will provide the
necessary support:
COMMON_CBFS_SPI_WRAPPER users
soc/intel/apollolake
soc/intel/baytrail
soc/intel/braswell
soc/intel/broadwell
soc/intel/skylake
The SPI_FLASH option is auto-selected if the platform provides
write supoprt for the boot device and SPI flash is the boot
device.
Other platforms may provide similar support, but they do that
in a device specific manner such as selecting SPI_FLASH
explicitly. This provides clearance against build failures
where chipsets don't provide SPI API implementations even
though the platform may use a SPI flash to boot.
BUG=chrome-os-partner:56151
Change-Id: If78160f231c8312a313f9b9753607d044345d274
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16211
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16211 for details.
-gerrit
the following patch was just integrated into master:
commit 3326f1599133fd070d378606d717cc9412fb3aab
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Aug 12 15:50:16 2016 -0500
drivers/spi: move cbfs_spi.c location
The common boot device spi implementation is very much
specific to SPI flash. As such it should be moved into
that subdirectory. It's still a high-level option but
it correctly depends on BOOT_DEVICE_SPI_FLASH. Additionally
that allows the auto-selection of SPI_FLASH by a platform
selecting COMMON_CBFS_SPI_WRAPPER which allows for culling
of SPI_FLASH selections everywhere.
BUG=chrome-os-partner:56151
Change-Id: Ia2ccfdc9e1a4348cd91b381f9712d8853b7d2a79
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16212
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16212 for details.
-gerrit
the following patch was just integrated into master:
commit 16c173fdf5d6060ecdd63ca4593fb76b2167ab9b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Aug 11 14:04:10 2016 -0500
Kconfig: separate memory mapped boot device from SPI
Make the indication of the boot device being memory mapped
separate from SPI. However, retain the same defaults that
previously existed.
BUG=chrome-os-partner:56151
Change-Id: I06f138078c47a1e4b4b3edbdbf662f171e11c9d4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16228
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16228 for details.
-gerrit
the following patch was just integrated into master:
commit d3d77beffa1e7c8d28deabeda0709e0a0beacce2
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed Aug 17 16:18:05 2016 -0700
google/reef: Configure NFC gpios correctly before entering sleep
Before entering sleep, ensure that the NFC gpios are configured
correctly to avoid leakage.
BUG=chrome-os-partner:56281
Change-Id: I2bb2e7ba468df445aa5f6c2b22ae0a74fcaa44f6
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-on: https://review.coreboot.org/16243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16243 for details.
-gerrit
the following patch was just integrated into master:
commit cb6096d71d40c0d15a0abe18ffad1f47c3e7ebf5
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed Aug 17 16:16:39 2016 -0700
intel/apollolake: Skip ITSS configuration in SMM
In SMM, gpio configuration could be done to avoid leakage. ITSS
configuration is not required when entering sleep. Thus, bail out early
from itss configuration if in SMM.
BUG=chrome-os-partner:56281
Change-Id: I4d8be0513aa202f001f980bb91986b50b8ed2a5b
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-on: https://review.coreboot.org/16242
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16242 for details.
-gerrit
the following patch was just integrated into master:
commit 82bd0c352ce75bdc699dbd0940b04e83986dcde5
Author: Felix Held <felix-coreboot(a)felixheld.de>
Date: Sat Aug 13 23:27:15 2016 +0200
bd82x6x/pch: move global variables to static variables in functions
Change-Id: I9e5795f9d601e5d2e7331715e5cd3848389cd594
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-on: https://review.coreboot.org/16213
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/16213 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16255
-gerrit
commit 809508fb4195b7f99fc8ad42e5623a8651ba6d8a
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Aug 18 18:56:45 2016 -0600
iPXE: Update stable version to the last commit of July 2016
Change-Id: I804d5a9100fdfea48383aaf5dc0eb154eda78f4d
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
payloads/external/iPXE/Kconfig | 4 ++--
payloads/external/iPXE/Makefile | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index aa8d92d..67b2111 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -42,12 +42,12 @@ choice
depends on BUILD_IPXE
config IPXE_STABLE
- bool "2016.2"
+ bool "2016.7"
help
iPXE uses a rolling release with no stable version, for
reproducibility, use the last commit of a given month as the
'stable' version.
- This is iPXE from the end of February, 2016.
+ This is iPXE from the end of July, 2016.
config IPXE_MASTER
bool "master"
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index 7e43bf8..8e07936 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -13,9 +13,9 @@
## GNU General Public License for more details.
##
-# 2016.2 - Last commit of February 2016
+# 2016.7 - Last commit of July 2016
# When updating, change the name both here and in payloads/external/iPXE/Kconfig
-STABLE_COMMIT_ID=99b5216b1c71dba22dab734e0945887525493cde
+STABLE_COMMIT_ID=2afd66eb55996500499eb3bcc39c66ff042679c8
TAG-$(CONFIG_IPXE_MASTER)=origin/master
TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID)
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16254
-gerrit
commit 80e9c8667d9f0b76559e31ccbbe316925ab1c4da
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Aug 18 18:11:30 2016 -0600
SeaBIOS: Update stable version to 1.9.3
The SeaBIOS Stable version 1.9.3 was released back in July. This has
just 4 fixes over 1.9.1:
fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL
fw/pci: Add support for mapping Intel IGD via QEMU
fw/pci: add Q35 S3 support
build: fix .text section address alignment
Change-Id: I527df85b5199942706d1188285c6678bf2f726a1
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
payloads/external/SeaBIOS/Kconfig | 2 +-
payloads/external/SeaBIOS/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index abfd291..cdc8017 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
default SEABIOS_STABLE
config SEABIOS_STABLE
- bool "1.9.1"
+ bool "1.9.3"
help
Stable SeaBIOS version
config SEABIOS_MASTER
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
index ba056a9..9ec3e60 100644
--- a/payloads/external/SeaBIOS/Makefile
+++ b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=b3ef39f532db52bf17457ba931da758eeb38d6b4
+TAG-$(CONFIG_SEABIOS_STABLE)=e2fc41e24ee0ada60fc511d60b15a41b294538be
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
project_git_repo=https://review.coreboot.org/p/seabios.git