coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel/skylake: Do not halt in poweroff if in SMM
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16259 -gerrit commit cf8e4d91b9be4a427c2e01ec9c72b7b61bcac56f Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:42:36 2016 -0700 intel/skylake: Do not halt in poweroff if in SMM Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 Change-Id: I3addc1ea065346fbc5dbec9d1ad49bbd0ae05696 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/skylake/pmutil.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 807579d..31de242 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <halt.h> +#include <rules.h> #include <stdlib.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -435,5 +436,12 @@ uint16_t smbus_tco_regs(void) void poweroff(void) { enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - halt(); + + /* + * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM + * to transition to S5 state. If halt is called in SMM, then it prevents + * the SMI handler from being triggered and system never enters S5. + */ + if (!ENV_SMM) + halt(); }

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Patch set updated for coreboot: google/chromeec: Ensure data is ready before reading it
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16258 -gerrit commit 35469d5699d4034df0cb305570a11d472900f7fc Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:39:14 2016 -0700 google/chromeec: Ensure data is ready before reading it Before reading the data provided by EC to the host, ensure that data ready flag is set. Otherwise, it could result in reading stale/incorrect data from the data buffer. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is read correctly by host on reef. Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/ec/google/chromeec/ec_lpc.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 06b506b..51a6e53 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -96,7 +96,7 @@ static inline u8 write_byte(u8 val, u16 port) return byte; } -static int google_chromeec_wait_ready(u16 port) +static int google_chromeec_status_check(u16 port, u8 mask, u8 cond) { u8 ec_status = read_byte(port); u32 time_count = 0; @@ -108,8 +108,7 @@ static int google_chromeec_wait_ready(u16 port) */ #define MAX_EC_TIMEOUT_US 1000000 - while (ec_status & - (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) { + while ((ec_status & mask) != cond) { udelay(1); if (time_count++ == MAX_EC_TIMEOUT_US) return -1; @@ -118,6 +117,13 @@ static int google_chromeec_wait_ready(u16 port) return 0; } +static int google_chromeec_wait_ready(u16 port) +{ + return google_chromeec_status_check(port, + EC_LPC_CMDR_PENDING | + EC_LPC_CMDR_BUSY, 0); +} + #if CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP /* Read memmap data through ACPI port 66/62 */ static int read_memmap(u8 *data, u8 offset) @@ -481,6 +487,12 @@ struct chip_operations ec_google_chromeec_ops = { #endif /* __SMM__ */ +static int google_chromeec_data_ready(u16 port) +{ + return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, + EC_LPC_CMDR_DATA); +} + u8 google_chromeec_get_event(void) { if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { @@ -496,6 +508,11 @@ u8 google_chromeec_get_event(void) return 0; } + if (google_chromeec_data_ready(EC_LPC_ADDR_ACPI_CMD)) { + printk(BIOS_ERR, "Timeout waiting for data ready!\n"); + return 0; + } + /* Event (or 0 if none) is returned directly in the data byte */ return read_byte(EC_LPC_ADDR_ACPI_DATA); }

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Patch set updated for coreboot: intel/apollolake: Do not halt in poweroff if in SMM
by Furquan Shaikh 19 Aug '16

19 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16257 -gerrit commit 4af9371a2335058b4c8b39e0b8b75f7922b05832 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Aug 18 21:31:50 2016 -0700 intel/apollolake: Do not halt in poweroff if in SMM Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified lidclose behavior on reef. Change-Id: If116c8f4e867543abdc2ff235457c167b5073767 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/pmutil.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index dabc268..aaa4018 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -443,5 +443,12 @@ void vboot_platform_prepare_reboot(void) void poweroff(void) { enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - halt(); + + /* + * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM + * to transition to S5 state. If halt is called in SMM, then it prevents + * the SMI handler from being triggered and system never enters S5. + */ + if (!ENV_SMM) + halt(); }

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New patch to review for coreboot: arch/riscv: Map the kernel space into RAM (2GiB+)
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16263 -gerrit commit d73062e5111ef48bb7cc6efc9a7133b788bf184b Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:21 2016 +0200 arch/riscv: Map the kernel space into RAM (2GiB+) Change-Id: I273e9d20e02f0333f28e0fc2adcc7940578ea93e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/virtual_memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 18d2862..eb219e7 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -186,9 +186,9 @@ void initVirtualMemory(void) { } printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff81000000; - uintptr_t pageTableStart = 0x1400000; + uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs + uintptr_t virtualStart = 0xffffffff80000000; + uintptr_t pageTableStart = 0x91400000; init_vm(virtualStart, physicalStart, pageTableStart); mb();

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New patch to review for coreboot: arch/riscv: Enable U-mode/S-mode counters (stime, etc.)
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16262 -gerrit commit a7c298cff1d052f8c67e71856faacb756cac3667 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:20 2016 +0200 arch/riscv: Enable U-mode/S-mode counters (stime, etc.) Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/virtual_memory.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index fa30c54..c68ed4d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -218,4 +218,8 @@ void mstatus_init(void) | (1 << CAUSE_FAULT_STORE) | (1 << CAUSE_USER_ECALL) ); + + /* Enable all user/supervisor-mode counters */ + write_csr(mscounteren, 0b111); + write_csr(mucounteren, 0b111); }

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New patch to review for coreboot: arch/riscv: Fix unaligned memory access emulation
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16261 -gerrit commit 2a94c8d0de0eff25608a25849cca8f4b4221643f Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:20 2016 +0200 arch/riscv: Fix unaligned memory access emulation Change-Id: I06c6493355f25f3780f75e345c517b434912696f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/trap_handler.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 9f3f07f..d8ac784 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -14,10 +14,11 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/exception.h> +#include <console/console.h> #include <spike_util.h> #include <string.h> +#include <vm.h> #define HART_ID 0 #define CONSOLE_PUT 1 @@ -171,14 +172,16 @@ void trap_handler(trapframe *tf) { die("Can't recover from trap. Halting.\n"); } +static uint32_t fetch_instruction(uintptr_t vaddr) { + printk(BIOS_SPEW, "fetching instruction at 0x%016zx\n", (size_t)vaddr); + return mprv_read_u32((uint32_t *) vaddr); +} + void handle_misaligned_load(trapframe *tf) { printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); - insn_t faultingInstruction = 0; uintptr_t faultingInstructionAddr = tf->epc; - asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); - asm("lw t0, 0(t0)"); - asm("move %0, t0" : "=r"(faultingInstruction)); + insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr); printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); insn_t widthMask = 0x7000; insn_t memWidth = (faultingInstruction & widthMask) >> 12; @@ -188,7 +191,12 @@ void handle_misaligned_load(trapframe *tf) { if (memWidth == 3) { // load double, handle the issue void* badAddress = (void*) tf->badvaddr; - memcpy(&(tf->gpr[destRegister]), badAddress, 8); + uint64_t value = 0; + for (int i = 0; i < 8; i++) { + value <<= 8; + value += mprv_read_u8(badAddress+i); + } + tf->gpr[destRegister] = value; } else { // panic, this should not have happened printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n"); @@ -203,11 +211,8 @@ void handle_misaligned_load(trapframe *tf) { void handle_misaligned_store(trapframe *tf) { printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); - insn_t faultingInstruction = 0; uintptr_t faultingInstructionAddr = tf->epc; - asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); - asm("lw t0, 0(t0)"); - asm("move %0, t0" : "=r"(faultingInstruction)); + insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr); printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); insn_t widthMask = 0x7000; insn_t memWidth = (faultingInstruction & widthMask) >> 12; @@ -217,8 +222,11 @@ void handle_misaligned_store(trapframe *tf) { if (memWidth == 3) { // store double, handle the issue void* badAddress = (void*) tf->badvaddr; - long valueToStore = tf->gpr[srcRegister]; - memcpy(badAddress, &valueToStore, 8); + uint64_t value = tf->gpr[srcRegister]; + for (int i = 0; i < 8; i++) { + mprv_write_u8(badAddress+i, value); + value >>= 8; + } } else { // panic, this should not have happened printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n");

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New patch to review for coreboot: arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16260 -gerrit commit f01cdd6a71314df27e9634abddec09da3f0820da Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:20 2016 +0200 arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode Normally machine-mode code operates completely within physical address space. When emulating less privileged memory accesses (e.g. when the hardware doesn't support unaligned read/write), it is useful to access memory through the MMU (and with virtual addresses); this patch implements this functionality using the MPRV bit. Change-Id: Ic3b3301f348769faf3ee3ef2a78935dfbcbd15fd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/include/vm.h | 47 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index cd82b0a..a32efc5 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -30,6 +30,7 @@ #include <string.h> #include <stdint.h> +#include <arch/encoding.h> #define SUPERPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS)) #define VM_CHOICE VM_SV39 @@ -70,4 +71,50 @@ void mstatus_init(void); // need to setup mstatus so we know we have virtual mem void flush_tlb(void); + +#define DEFINE_MPRV_READ(name, type, insn) \ + static inline type name(type *p); \ + static inline type name(type *p) \ + { \ + int mprv = MSTATUS_MPRV; \ + type value; \ + asm ( \ + "csrs mstatus, %1\n" \ + STRINGIFY(insn) " %0, 0(%2)\n" \ + "csrc mstatus, %1\n" \ + : "=r"(value) : "r"(mprv), "r"(p) : "memory" \ + ); \ + return value; \ + } + +#define DEFINE_MPRV_WRITE(name, type, insn) \ + static inline void name(type *p, type value); \ + static inline void name(type *p, type value) \ + { \ + int mprv = MSTATUS_MPRV; \ + asm ( \ + "csrs mstatus, %0\n" \ + STRINGIFY(insn) " %1, 0(%2)\n" \ + "csrc mstatus, %0\n" \ + :: "r"(mprv), "r"(value), "r"(p) : "memory" \ + ); \ + } + +DEFINE_MPRV_READ(mprv_read_u8, uint8_t, lbu) +DEFINE_MPRV_READ(mprv_read_u16, uint16_t, lhu) +DEFINE_MPRV_READ(mprv_read_u32, uint32_t, lwu) +DEFINE_MPRV_READ(mprv_read_u64, uint32_t, ld) +DEFINE_MPRV_READ(mprv_read_long, long, ld) +DEFINE_MPRV_READ(mprv_read_ulong, unsigned long, ld) +DEFINE_MPRV_WRITE(mprv_write_u8, uint8_t, sb) +DEFINE_MPRV_WRITE(mprv_write_u16, uint16_t, sh) +DEFINE_MPRV_WRITE(mprv_write_u32, uint32_t, sw) +DEFINE_MPRV_WRITE(mprv_write_u64, uint64_t, sd) +DEFINE_MPRV_WRITE(mprv_write_long, long, sd) +DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd) + +#undef DEFINE_MPRV_READ +#undef DEFINE_MPRV_WRITE + + #endif

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Patch set updated for coreboot: arch/riscv: Delegate exceptions to supervisor mode if appropriate
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16160 -gerrit commit bf3ffa52906d612d2ae7c1c8a33d282938b312ab Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:19 2016 +0200 arch/riscv: Delegate exceptions to supervisor mode if appropriate Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/virtual_memory.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index f48c413..fa30c54 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -208,4 +208,14 @@ void mstatus_init(void) clear_csr(mip, MIP_MSIP); set_csr(mie, MIP_MSIP); + + /* Configure which exception causes are delegated to supervisor mode */ + set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) + | (1 << CAUSE_FAULT_FETCH) + | (1 << CAUSE_ILLEGAL_INSTRUCTION) + | (1 << CAUSE_BREAKPOINT) + | (1 << CAUSE_FAULT_LOAD) + | (1 << CAUSE_FAULT_STORE) + | (1 << CAUSE_USER_ECALL) + ); }

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Patch set updated for coreboot: arch/riscv: Dump the page table structures after construction
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16015 -gerrit commit f43241180cf954429a5cae7295470ee9db2625e3 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:18 2016 +0200 arch/riscv: Dump the page table structures after construction Change-Id: I52a863d8bc814ab3ed3a1f141d0a77edc6e4044d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/Kconfig | 8 ++++ src/arch/riscv/include/vm.h | 2 +- src/arch/riscv/virtual_memory.c | 85 +++++++++++++++++++++++++++++++++++++---- 3 files changed, 86 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7db491f..cb095c4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1127,6 +1127,14 @@ config DEBUG_BOOT_STATE Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. +config DEBUG_DUMP_PAGE_TABLES + bool "Dump the page tables after construction" + default n + depends on ARCH_RISCV + help + After the page tables have been built, print them on the debug + console. + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 5bf03c7..cd82b0a 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -63,7 +63,7 @@ size_t pte_ppn(pte_t pte); pte_t ptd_create(uintptr_t ppn); pte_t pte_create(uintptr_t ppn, int prot, int user); -void walk_page_table(void); +void dump_page_table(void); void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); void mstatus_init(void); // need to setup mstatus so we know we have virtual memory diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index bbbba7a..f48c413 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -23,11 +23,77 @@ pte_t* root_page_table; -void walk_page_table(void) { - // TODO: implement a full walk to make sure memory was set up - //const size_t pte_per_page = RISCV_PGSIZE/sizeof(void*); - pte_t* t = root_page_table; - printk(BIOS_DEBUG, "root_page_table: %p\n", t); +/* Indent the following text by 2*level spaces */ +static void indent(int level) +{ + int i; + for (i = 0; i < level; i++) + printk(BIOS_DEBUG, " "); +} + +/* + * Convert a page table index at a given page table level to a virtual address + * offset + */ +static uintptr_t index_to_virt_addr(int index, int level) +{ + /* + * Index is at most RISCV_PGLEVEL_BITS bits wide (not considering the + * leading zeroes. If level==0, the below expression thus shifts index + * into the highest bits of a 64-bit number, and then shifts it down + * with sign extension. + * + * If level>0, then the expression should work as expected, without any + * magic. + */ + return ((intptr_t)index) + << (64 - RISCV_PGLEVEL_BITS - level * RISCV_PGLEVEL_BITS) + >> (64 - VA_BITS); +} + +/* Dump the page table structures to the console -- helper function */ +static void dump_page_table_at(pte_t *pt, intptr_t virt_addr, int level) +{ + int i; + + indent(level); + printk(BIOS_DEBUG, "Level %d page table at 0x%p\n", level, pt); + + for (i = 0; i < RISCV_PGSIZE/sizeof(pte_t); i++) { + char urwx[8]; + uintptr_t pointer; + intptr_t next_virt_addr; + + if (!(pt[i] & PTE_V)) + continue; + + urwx[0] = (pt[i] & PTE_U)? 'u' : '-'; + urwx[1] = (pt[i] & PTE_R)? 'r' : '-'; + urwx[2] = (pt[i] & PTE_W)? 'w' : '-'; + urwx[3] = (pt[i] & PTE_X)? 'x' : '-'; + urwx[4] = '\0'; + + next_virt_addr = virt_addr + index_to_virt_addr(i, level); + + pointer = ((uintptr_t)pt[i] >> 10) << RISCV_PGSHIFT; + + indent(level+1); + printk(BIOS_DEBUG, "Valid PTE at index %d (0x%016zx -> 0x%zx), ", + i, (size_t) next_virt_addr, (size_t) pointer); + if (PTE_TABLE(pt[i])) + printk(BIOS_DEBUG, "page table\n"); + else + printk(BIOS_DEBUG, "protections %s\n", urwx); + + if (PTE_TABLE(pt[i])) { + dump_page_table_at((pte_t *)pointer, next_virt_addr, level + 1); + } + } +} + +/* Dump the page table structures to the console */ +void dump_page_table(void) { + dump_page_table_at(root_page_table, 0, 0); } void flush_tlb(void) @@ -124,14 +190,17 @@ void initVirtualMemory(void) { uintptr_t pageTableStart = 0x1400000; init_vm(virtualStart, physicalStart, pageTableStart); mb(); + +#if IS_ENABLED(CONFIG_DEBUG_DUMP_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); - walk_page_table(); + dump_page_table(); +#else + printk(BIOS_DEBUG, "Finished initializing virtual memory\n"); +#endif } void mstatus_init(void) { - // supervisor support is required - uintptr_t ms = 0; ms = INSERT_FIELD(ms, MSTATUS_FS, 3); ms = INSERT_FIELD(ms, MSTATUS_XS, 3);

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Patch set updated for coreboot: arch/riscv: Implement the SBI again
by Jonathan Neuschäfer 19 Aug '16

19 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16119 -gerrit commit 50a82d968b544555ae973453cce3940e45a5a58f Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Aug 19 12:10:20 2016 +0200 arch/riscv: Implement the SBI again Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OF… Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/include/arch/sbi.h | 36 +++++++ src/arch/riscv/sbi.S | 117 +++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 43 ++++----- src/arch/riscv/virtual_memory.c | 3 +- src/mainboard/emulation/spike-riscv/spike_util.c | 22 ++--- 6 files changed, 183 insertions(+), 39 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 718aad9..4bab459 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -95,6 +95,7 @@ ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c +ramstage-y += sbi.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/include/arch/sbi.h b/src/arch/riscv/include/arch/sbi.h new file mode 100644 index 0000000..df7f6cc --- /dev/null +++ b/src/arch/riscv/include/arch/sbi.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _ARCH_SBI_H +#define _ARCH_SBI_H + +#define SBI_ECALL_HART_ID 0 +#define SBI_ECALL_CONSOLE_PUT 1 +#define SBI_ECALL_SEND_DEVICE_REQUEST 2 +#define SBI_ECALL_RECEIVE_DEVICE_RESPONSE 3 +#define SBI_ECALL_SEND_IPI 4 +#define SBI_ECALL_CLEAR_IPI 5 +#define SBI_ECALL_SHUTDOWN 6 +#define SBI_ECALL_SET_TIMER 7 +#define SBI_ECALL_QUERY_MEMORY 8 +#define SBI_ECALL_NUM_HARTS 9 + +#ifndef __ASSEMBLY__ +struct opaque; +extern struct opaque sbi_page; +#endif + +#endif diff --git a/src/arch/riscv/sbi.S b/src/arch/riscv/sbi.S new file mode 100644 index 0000000..f4d5411 --- /dev/null +++ b/src/arch/riscv/sbi.S @@ -0,0 +1,117 @@ +/* + * RISC-V supervisor binary interface (SBI) trampoline page + * + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#define __ASSEMBLY__ +#include <arch/encoding.h> +#include <arch/sbi.h> + +.section ".text.sbi", "ax", %progbits + +/* align to a page boundary */ +.align RISCV_PGSHIFT + +.globl sbi_page +sbi_page: + + /* + * None of the SBI entry points is located in the first half of the + * page + */ + .skip 0x800 + + /* -2048: size_t sbi_hart_id(void); */ + li a7, SBI_ECALL_HART_ID + ecall + jr ra + .align 4 + + /* -2032: size_t sbi_num_harts(void); */ + li a7, SBI_ECALL_NUM_HARTS + ecall + jr ra + .align 4 + + /* -2016: unsigned long sbi_query_memory(unsigned long id, + memory_block_info *p); */ + li a7, SBI_ECALL_QUERY_MEMORY + ecall + jr ra + .align 4 + + /* -2000: int sbi_console_putchar(uint8_t ch); */ + li a7, SBI_ECALL_CONSOLE_PUT + ecall + jr ra + .align 4 + + /* -1984: int sbi_console_getchar(void); */ + li a0, -1 /* failure: Coreboot doesn't support console input */ + jr ra + .align 4 + + /* -1968: Not allocated */ + ebreak + .align 4 + + /* -1952: int sbi_send_ipi(size_t hart_id); */ + ebreak + .align 4 + + /* -1936: int bool sbi_clear_ipi(void); */ + ebreak + .align 4 + + /* -1920: unsigned long sbi_timebase(void); */ + li a0, 1000000000 /* I have no idea. */ + jr ra + .align 4 + + /* -1904: void sbi_shutdown(void); */ + li a7, SBI_ECALL_SHUTDOWN + ecall + jr ra + .align 4 + + /* -1888: void sbi_set_timer(unsigned long long stime_value); */ + li a7, SBI_ECALL_SET_TIMER + ecall + jr ra + .align 4 + + /* -1872: int sbi_mask_interrupt(int which); */ + ebreak + .align 4 + + /* -1856: int sbi_unmask_interrupt(int which); */ + ebreak + .align 4 + + /* -1840: void sbi_remote_sfence_vm(const uintptr_t* harts, + size_t asid); */ + ebreak + .align 4 + + /* -1824: void sbi_remote_sfence_vm_range(const uintptr_t* harts, + size_t asid, uintptr_t start, uintptr_t size); */ + ebreak + .align 4 + + /* -1808: void sbi_remote_fence_i(const uintptr_t* harts); */ + ebreak + .align 4 + +/* Fill the remainder of the page */ +.align RISCV_PGSHIFT diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index d8ac784..29d5a0b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -15,63 +15,56 @@ */ #include <arch/exception.h> +#include <arch/sbi.h> #include <console/console.h> #include <spike_util.h> #include <string.h> #include <vm.h> -#define HART_ID 0 -#define CONSOLE_PUT 1 -#define SEND_DEVICE_REQUEST 2 -#define RECEIVE_DEVICE_RESPONSE 3 -#define SEND_IPI 4 -#define CLEAR_IPI 5 -#define SHUTDOWN 6 -#define SET_TIMER 7 -#define QUERY_MEMORY 8 - -int loopBreak2 = 1; - void handle_supervisor_call(trapframe *tf) { - uintptr_t call = tf->gpr[17]; - uintptr_t arg0 = tf->gpr[10]; - uintptr_t arg1 = tf->gpr[11]; + uintptr_t call = tf->gpr[17]; /* a7 */ + uintptr_t arg0 = tf->gpr[10]; /* a0 */ + uintptr_t arg1 = tf->gpr[11]; /* a1 */ uintptr_t returnValue; switch(call) { - case HART_ID: + case SBI_ECALL_HART_ID: printk(BIOS_DEBUG, "Getting hart id...\n"); - returnValue = mcall_hart_id(); + returnValue = read_csr(mhartid); break; - case CONSOLE_PUT: + case SBI_ECALL_NUM_HARTS: + /* TODO: parse the hardware-supplied config string and + return the correct value */ + returnValue = 1; + case SBI_ECALL_CONSOLE_PUT: returnValue = mcall_console_putchar(arg0); break; - case SEND_DEVICE_REQUEST: + case SBI_ECALL_SEND_DEVICE_REQUEST: printk(BIOS_DEBUG, "Sending device request...\n"); returnValue = mcall_dev_req((sbi_device_message*) arg0); break; - case RECEIVE_DEVICE_RESPONSE: + case SBI_ECALL_RECEIVE_DEVICE_RESPONSE: printk(BIOS_DEBUG, "Getting device response...\n"); returnValue = mcall_dev_resp(); break; - case SEND_IPI: + case SBI_ECALL_SEND_IPI: printk(BIOS_DEBUG, "Sending IPI...\n"); returnValue = mcall_send_ipi(arg0); break; - case CLEAR_IPI: + case SBI_ECALL_CLEAR_IPI: printk(BIOS_DEBUG, "Clearing IPI...\n"); returnValue = mcall_clear_ipi(); break; - case SHUTDOWN: + case SBI_ECALL_SHUTDOWN: printk(BIOS_DEBUG, "Shutting down...\n"); returnValue = mcall_shutdown(); break; - case SET_TIMER: + case SBI_ECALL_SET_TIMER: printk(BIOS_DEBUG, "Setting timer to %p (current time is %p)...\n", (void *)arg0, (void *)rdtime()); returnValue = mcall_set_timer(arg0); break; - case QUERY_MEMORY: + case SBI_ECALL_QUERY_MEMORY: printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0); returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1); break; diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index c68ed4d..18d2862 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -16,6 +16,7 @@ #include <arch/barrier.h> #include <arch/encoding.h> +#include <arch/sbi.h> #include <atomic.h> #include <console/console.h> #include <stdint.h> @@ -151,7 +152,7 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable // map SBI at top of vaddr space uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface - uintptr_t sbiStartAddress = 0x2000; // the start of the sbi mapping + uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index f0f5301..7ddf16b 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -25,12 +25,13 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <spike_util.h> #include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> -#include <string.h> #include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> uintptr_t translate_address(uintptr_t vAddr) { // TODO: implement the page table translation algorithm @@ -41,13 +42,13 @@ uintptr_t translate_address(uintptr_t vAddr) { return translationResult; } -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) { - uintptr_t physicalAddr = translate_address((uintptr_t) p); - memory_block_info *info = (memory_block_info*) physicalAddr; if (id == 0) { - info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later - info->size = 0x7F000000 - info->base; + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); return 0; } @@ -79,7 +80,7 @@ uintptr_t mcall_shutdown(void) uintptr_t mcall_set_timer(unsigned long long when) { - die("mcall_set_timer is currently not implemented"); + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); return 0; } @@ -95,11 +96,6 @@ uintptr_t mcall_dev_resp(void) return 0; } -uintptr_t mcall_hart_id(void) -{ - return HLS()->hart_id; -} - void hls_init(uint32_t hart_id) { memset(HLS(), 0, sizeof(*HLS()));

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coreboot-gerrit August 2016